Commit Graph

1584 Commits

Author SHA1 Message Date
refractionpcsx2 24e73b3134
Savestates: Add missing things from Savestates (#4917)
Savestates: Add missing variables from Savestates
2021-10-20 10:41:50 +01:00
refractionpcsx2 5011b9ead5 EE: Cyclerate > 1 caused some cycles to be lost 2021-10-19 20:09:07 +01:00
refractionpcsx2 6746578120 VU JIT: Include ADDi in flag calculations
Fixes #4916
2021-10-18 12:32:44 +01:00
Connor McLaughlin 44bc273590 microVU: Use uncached reg when clamping for FMAC instructions 2021-10-17 15:54:58 +01:00
TellowKrinkle f22ba886d9 Fix unparenthesized macro input 2021-10-17 04:17:58 +01:00
refractionpcsx2 a96f900760 COP2: Simplify reg allocation 2021-10-14 10:06:13 +01:00
Ziemas 45bb57a38c IOP Recompiler: Fix BIOS trace logging on 64bit 2021-10-13 22:42:51 +02:00
refractionpcsx2 ae1f1599f6 COP2: Fix reg allocation issue
Really fixes Devil May Cry which was a bug hidden by clamping hidden by a bug, yeah i think that covers it all...
2021-10-07 23:29:04 +01:00
Connor McLaughlin ca523edf0e Config: Move folders to their own namespace
Don't duplicate in EmuOptions.
2021-10-01 23:46:52 -04:00
Connor McLaughlin 4d8905abd6 Config: Swap out wxString for std::string
Also in CDVD.
2021-10-01 23:46:52 -04:00
Connor McLaughlin 77a890ff4a Config: Move Folders/BaseFilenames to base config 2021-10-01 23:46:52 -04:00
Connor McLaughlin 8e1470f637 iR5900: Use fastjmp instead of longjmp 2021-10-01 23:30:39 +01:00
Connor McLaughlin 91627b28b4 R5900: Get rid of ScopedBools 2021-10-01 23:30:39 +01:00
lightningterror a25dc9c38c ICore: Cleanup Wsign-compare warnings. 2021-09-30 01:07:59 +02:00
refractionpcsx2 7faa5db9e5 VU/GameDB: Move Mac/Status overflow flag checks to a gamefix
We can't really do this reliably on x86 without soft floats, but superman still needs it, but it breaks other games.
2021-09-29 17:33:13 +01:00
Ty Lamontagne aef731fdbe MicroVU: Fix branch type detection
amendment of 589aba
2021-09-26 05:13:28 +01:00
refractionpcsx2 f5f44286bf EE: 64bit compare for 64bit mode, not 32bit 2021-09-22 19:57:40 +01:00
TellowKrinkle 65e57a8230 iR5900: Use 64-bit math on x86-64 2021-09-22 12:47:49 +01:00
TellowKrinkle e74ba82093 iR5900: Move repeated code into functions 2021-09-22 12:47:49 +01:00
TellowKrinkle 0d7f141279 EERec: Don't load in skip case of SW[LR] 2021-09-21 22:57:41 +01:00
TellowKrinkle 23578e963f EERec: Don't load in skip case of SD[LR] 2021-09-21 22:57:41 +01:00
TellowKrinkle e9518f78c7 vtlb: Switch read64 and read128 handlers to return in sse regs 2021-09-21 22:57:41 +01:00
TellowKrinkle 7563f54e83 EERec: Clean up [LS]D[LR] a bit 2021-09-21 22:57:41 +01:00
refractionpcsx2 e127ca0cd1 COP2: Set correct number of XMM's per COP2 OP + Fix some hidden bugs
Corrects XMM count for COP2 ops (some might be wrong, keep an eye out in the logs)
Fixes a hidden microVU bug with a SUB shortcut + some reg allocation bugs in QMFC/QMTC hidden by flushes.
2021-09-21 22:46:33 +01:00
refractionpcsx2 752957604e COP2: Flush only needed register slots 2021-09-21 22:46:33 +01:00
refractionpcsx2 fba9c6c04d COP2: never flush EE regs but back them up conditionally 2021-09-21 22:46:33 +01:00
refractionpcsx2 8fe0061751 VU: Sync tighter when VU Kickstart is disabled + Improved M-Bit Sync 2021-09-19 18:49:24 +01:00
Connor McLaughlin e2992cbc02 Remove gui/ directory from target-wide includes 2021-09-17 22:03:00 -04:00
refractionpcsx2 a546cb8f7f microVU: Use 16 xmm's in x64 2021-09-17 14:37:11 +01:00
refractionpcsx2 862d606514 EE Rec: Added LDR/LDL
Also fixed slight optimisation bug in SDL
2021-09-17 13:06:47 +01:00
refractionpcsx2 5f58c325ca EE JIT: Implement SDR/SDL instructions 2021-09-17 13:06:47 +01:00
refractionpcsx2 d9c4ace613 VU: Put XGKick 1 cycle behind to fix sync issues with Jaws Unleashed
Also added Jaws unleashed xgkick gamefixes to the DB
2021-09-17 13:04:26 +01:00
refractionpcsx2 59dfe52b52 microVU: Replace XGKick hack with synced XGKick option
Fixes Tennis Court Smash and Love Smash games which previously couldn't be fixed.
WRC no longer requires a patch, just the xgkickhack option.

Note: it's not a hack anymore, it just has to be called that :P
2021-09-17 13:04:26 +01:00
refractionpcsx2 73bb8e4fdf VU Int: Make XGKick flush on VU program end
Some games like to write directly to VU memory once the program has finished and I have no easy way to update the kick without being super slow. so for now, we'll just flush it.
2021-09-12 16:12:31 +01:00
refractionpcsx2 3f56414824 VIF/VU: Cleaned up VIF Stall behaviour, sync XGKick with Unpacks.
Also cleaned up a bunch of bad/old code
Fixed branches on E-Bit and M-Bit (VU0)
Fixed up VU Int behaviour with VU Instant on/off

Savestate bump
2021-09-12 16:12:31 +01:00
refractionpcsx2 b4eaf3722f VU: Adjust timings of VU calls 2021-09-12 16:12:31 +01:00
Ty Lamontagne ab64023e56 MicroVU: Cleanup stale comments and code 2021-09-11 01:33:02 +01:00
Ty Lamontagne 18311d6a4c MicroVU: Purge Min/Max speedhack 2021-09-06 21:36:10 +01:00
Ty Lamontagne 589aba3713 [MicroVU] Revert "bla"
This reverts commit 6800753f09.
2021-09-06 19:53:08 +01:00
Ty Lamontagne f91286dbf3 MicroVU: Skip VU1 instructions on VU0 2021-09-05 21:18:19 +01:00
refractionpcsx2 b919de9dd1 VU: Adjust sync timing for VU Kickstart
Fixes Crash Twinsanity
2021-09-05 18:14:53 +01:00
lightningterror c2dad218e5 microVU: Combine mVU0cacheReserve and mVU1cacheReserve. 2021-09-05 18:06:46 +02:00
refractionpcsx2 ddb300027c VU: Improve sync during interlock and Scratchpad VU mem writes
Also added some setting of next block cycles to 0 in cases where we don't know ahead of compile time or the VU is ending.
2021-09-05 16:37:43 +01:00
TellowKrinkle dae8e0d233 Core: Remove unused mmx stuff 2021-09-04 18:28:24 -04:00
TellowKrinkle 5260d63565 Core: Format recompilers 2021-09-04 18:28:24 -04:00
kojin 8fdaaa2eab common: reorganize 2021-09-04 18:28:07 -04:00
refractionpcsx2 bda80fc748 Clang Format VU files 2021-08-31 21:29:31 +01:00
refractionpcsx2 d8dfe0a1e9 VU: optimise entering VU JITs
Keeps note on how many cycles it needs for the next block to save exiting the EE JIT and entering the microVU JIT for no reason
2021-08-31 21:29:31 +01:00
Connor McLaughlin d7de81aaaa iR5900: Make const register write clearer
This was apparently sign extending anyway, but using SD makes it clear
that the 32-bit assignment will sign extend to 64-bit.
2021-08-17 14:43:24 -04:00
Connor McLaughlin a216f28c9d iR5900: Use a signed multiply for MULT1 const prop 2021-08-17 14:43:24 -04:00
Connor McLaughlin 6844849305 microVU: Don't emit add reg, 0 in a few instructions 2021-08-15 08:02:34 +01:00
refractionpcsx2 8f82cd11b9 microVU: avoid half completed program loading null block 2021-08-03 11:52:15 +01:00
lightningterror ea759d7b68 microVU: Clean up a few warnings. 2021-07-28 22:10:47 +02:00
refractionpcsx2 7584571fbc GameDB: Removed Ratchet Dynamic patch. 2021-07-18 01:24:29 +01:00
refractionpcsx2 03b0d2eb00 RatchetDynaHack: Actually enable it when enabling the gamefix 2021-07-17 16:54:59 +01:00
refractionpcsx2 56372cc46d GameDB: Rename VU0Kickstart -> VUKickstart
Clean up a couple of bits in microVU
2021-07-15 13:58:34 +01:00
refractionpcsx2 c31d6b9ca3 GameDB: Add dynamic patching for Ratchet & Clank games
Removed IPUWait hack as it is no longer required
2021-07-15 13:43:16 +01:00
refractionpcsx2 6d9ace148e VU: Improve sync with VU Kickstart, loosen without kickstart 2021-07-15 13:42:52 +01:00
refractionpcsx2 45c1579a15 Debug: ignore perfectly timed DIV's, cycle count is off by one 2021-07-13 10:26:42 +01:00
refractionpcsx2 14be2649cf Debug: Detect bad COP2 DIV Unit Timing in Devel Builds 2021-07-12 20:45:50 +01:00
refractionpcsx2 c77e0a3a56 microVU: Enable T-Bit to work with MTVU 2021-07-05 10:26:50 +01:00
refractionpcsx2 973ebd153d microVU: Consolidate I-bit hacks in to one generic one 2021-07-05 10:26:09 +01:00
Gauvain 'GovanifY' Roussel-Tarbouriech fa9b30fa9e pcsx2: remove relative imports
gosh that was a pain, please don't make me do that again
2021-07-03 18:16:11 -04:00
TellowKrinkle f3b17cf021 iR5900: Move recConstBuf memory near recompiler memory 2021-06-18 00:44:02 +01:00
Ty Lamontagne 1097e246a4 Differentiate Impossible block clearing message from IOP & EE 2021-05-26 10:14:20 +01:00
kozarovv 0ad5680597 FPU: Remove FPU Compare Hack
FULL clamping mode fix games where hack was used, so is no longer required.
This commit remove hack, adjust GameDB according to that change, and rename fpuFloat4 function to fpuFloat3.
Last change is because fpuFloat3 was just wrapper for fpuFloat4 with added check for compare hack.
Additionally fpuFloat2 was only function that called fpuFloat4 directly, so that one call was changed to fpuFloat3 to respect previous changes.
2021-05-08 17:04:09 +02:00
refractionpcsx2 6f7890b709 microVU: Fix mistake when setting Status Flag bits for Signed/Zero 2021-04-19 10:55:33 +01:00
Gauvain 'GovanifY' Roussel-Tarbouriech 8a9ec4c706 core: purge sse2 2021-04-10 19:16:42 +02:00
refractionpcsx2 951cce7543 microVU: move the overflow flags to the correct position... 2021-02-28 05:21:18 +00:00
refractionpcsx2 f9d96f55a5 microVU: Remove SSE4 op from Overflow flag checks + clean up the code 2021-02-28 01:20:38 +00:00
ty b088ee69cd COP0: Preserve read only fields IC and DC in the config register 2021-02-24 17:44:14 +00:00
Christian Kenny e9e7974b15 Common: Remove obsolete/unused code 2021-02-23 00:28:53 +00:00
tellowkrinkle 1470315356 Fix compile of eeProfiler 2021-02-03 20:44:03 -06:00
kozarovv 983f6e28f5 microVU: Fix Esin opcode
Fix X2 - Wolverine's Revenge
2021-01-31 18:33:01 +00:00
refractionpcsx2 89991594de Vif: Clean up some old (incorrect) code. 2021-01-10 11:02:19 +00:00
Maxim Nikitin 7dbf01b024
Implements IOP breakpoints (#3011)
IOP: Implement IOP Breakpoints
2021-01-08 23:34:08 +00:00
refractionpcsx2 0f7044a90f mVU: Removed full flag optimisations
They were unused, broken and cluttering up the code, so gotten rid.
2021-01-03 16:17:19 +00:00
refractionpcsx2 c9bc6eac69 mVU: Fix P flag instance on Ebit
Also small fix for flag statuses on M-Bit on Branch
2021-01-03 12:03:55 +00:00
refractionpcsx2 413fd004da mVU: Fix jump caching when using doJumpAsSameProgram. This is by default 2021-01-02 08:35:32 +00:00
refractionpcsx2 ee07f860fc microVU: Implement Overflow checks. Fixes Superman Returns
Removed patches for Superman Returns
2021-01-01 20:55:11 +00:00
refractionpcsx2 155cf385bd microVU: Flush running VU1 program when toggling MTVU on 2020-12-18 20:55:02 +00:00
Tellow Krinkle 096bb8bf74 x86emitter: Remove virtual methods from register types
Allows methods to generate variable-sized registers
2020-12-16 20:31:19 -06:00
Tyler Wilding 9fa484dbab GameDB/MSVC: renamed _Target_ to _InstrucTarget_ to avoid collisions 2020-12-16 09:31:58 +00:00
refractionpcsx2 03445d0b55 microVU: Add sanity check when loading quick block from program.
Sometimes (CoD Finest Hour) can somehow end up with blocks missing from a program, not sure how, but it still finds the current program, so we check if the block exists, if not, recompile new ones.
2020-12-15 20:26:41 +00:00
refractionpcsx2 7138769182 VU: Synchronise VU1, added speedhack for old behaviour 2020-12-13 22:02:37 +00:00
refractionpcsx2 16d33f8960 VIF/MTVU: Correctly increment tag addr on VIF when using MTVU
Fixes Def Jam Fight for NY when using MTVU
2020-12-06 07:06:51 +00:00
refractionpcsx2 4595aae0de mVU: Keep start PC, modify prog search to avoid recompilation
Also fix some M-Bit stuff
2020-12-06 07:06:51 +00:00
GovanifY a3695f1cfd JIT: fix FPU IEEE float conversion on x64 2020-10-30 00:25:03 +00:00
refractionpcsx2 3dc44bafb3 microVU: Fix program range wrapping 2020-10-26 22:44:52 +00:00
refractionpcsx2 9ebcb3b141 microVU: Sort out when the Status flag is de/normalized
Properly clear non-stick invalid/zero flags on DIV/SQRT/RSQRT COP2 instructions
2020-10-26 22:44:36 +00:00
refractionpcsx2 4b0dc9c0df microVU: properly normalise Status flags when exiting a VU program
Fixes shadows in Ratchet Gladiator
2020-10-26 22:44:36 +00:00
refractionpcsx2 f25e7ff004 microVU: Save valid flag instances at the end of a VU0 program.
Fixes State of Emergency 2 black screens and BIOS reboot in Driving Emotion Type-S
2020-10-26 22:44:36 +00:00
refractionpcsx2 0448b4902c microVU: Fixed bug in E-bit conditional branches. Fixes DT Racer
GameDB: Added VU0 Kickstart hack for DT Racer
2020-10-25 21:41:29 +00:00
refractionpcsx2 2409486c2d VIF: Fixed undefined behaviour of Unpack V3-16 in final QW write.
Fixes Homerun
2020-10-18 17:24:43 +01:00
refractionpcsx2 cf05f6ca40
Cop2: Make sure the status flag gets updated on DIV/SQRT/RSQRT (#3813)
Fixes Yanya Caballista (patches removed)
Fixes Disney's Treasure Plantet's crazy camera (that flies off) and ground displacement. Fixes #3441
2020-10-16 09:47:23 +01:00
refractionpcsx2 bec587164b
microVU: Make sure flags are exact on M-bit (#3797)
* microVU: Don't break on M-Bit if previous instruction was M-Bit

Fixes Gungrave
2020-10-05 21:49:15 +01:00
kozarovv 491b6e12f7
Core: Fix recLUT_SetPage in recResetIOP for ROM1, and ROM2 (#3753) 2020-09-30 11:44:20 +01:00
refractionpcsx2 197eaf3899 VU: Also update Status/Mac instances after COP2, just in case 2020-09-10 12:25:52 +01:00
refractionpcsx2 19ab48c280 VU: Copy CLIP flag instance back to VU0 int and microVU when COP2 modifies it
Fixes Soul Calibur 3 hair
2020-09-10 11:52:47 +01:00
refractionpcsx2 4629c8363c microVU: Fix state saving when m-bit is reached
microVU: Fix range merging to encompass whole ranges of programs
2020-09-01 20:49:07 +01:00
refractionpcsx2 87dc885a4a VU: Improved EE Cycle Skipping hack to work better with the new VU0 sync changes 2020-08-30 17:15:18 +01:00
TellowKrinkle 56f2d307bc microVU: Fix empty register use 2020-08-30 04:31:10 +01:00
refractionpcsx2 ecebaca3f0 VU: Fix x64 crash introduced with VU Sync PR
Thanks to TellowKrinkle for helping me debug this one
2020-08-30 04:08:23 +01:00
kozarovv df79a17baa VU: Improve VU0/EE sync, Implement better M-Bit Handling, Fix VU program handing on VIF 2020-08-29 21:56:26 +01:00
Tellow Krinkle cd813edb1b x86emitter: Remove deprecated codegen functions
Successfully moved off of all of them
2020-08-24 16:20:09 -05:00
Tellow Krinkle 0711e0cd52 recompiler: Add comments to recLUT_SetPage
It's kind of confusing
2020-08-24 16:20:09 -05:00
Tellow Krinkle dc57270fb8 EE/IOP/VU: x86-64 recompiler support 2020-08-24 16:20:09 -05:00
tellowkrinkle 850efdc690
Move VTLB manipulation to class (#3524)
Another small piece of #3451

Moves all VTLB pointer manipulation into dedicated classes for the purpose, which should allow the algorithm to be changed much more easily in the future (only have to change the class and recVTLB.cpp assembly since it obviously can't use the class)

Also some of the functions that manipulated the VTLB previously used POINTER_SIGN_BIT (which 1 << 63 on 64-bit) while others used a sign-extended 0x80000000. Now they all use the same one (POINTER_SIGN_BIT)

Note: recVTLB.cpp was updated to keep it compiling but the rest of the x86-64 compatibility changes were left out

Also, Cache.cpp seems to assume VTLB entries are both sides of the union at the same time, which is impossible. Does anyone know how this actually worked (and if this patch breaks it) or if it never worked properly in the first place?
2020-08-19 09:37:23 +01:00
tellowkrinkle 75aac90452
Allocate memory in an x86-64-compatible way (#3523)
Allocate memory in an x86-64-compatible way

Another part of #3451

Note: While this shouldn't change how anything works, it's been the #1 source of breakage of 32-bit builds in #3451 (it was the cause for the failure of win32 to allocate memory and the failure of linux-32 afterward) so we should definitely make sure it gets tested

see #3523 for more information
2020-08-19 09:20:48 +01:00
kozarovv 6794bbbd6a
Add rom2: support (Fix Chinese Bios) (#3439)
* Add rom2 support

* Add rom2 support on IOP

* Valid memory range for rom2

* Add rom2 support to IopMem.cpp
2020-08-08 20:59:46 +01:00
refractionpcsx2 54f47572af EE REC: Prevent crash when DI instruction is in branch delay slot 2020-07-16 20:09:12 +01:00
arcum42 2b115d031e
Remove superVU. (#3386)
* Remove superVU, as well as the VUClipFlagHack, which was SuperVU only.
2020-05-24 19:08:12 -07:00
water111 94e1635882
Make recLUT not hardcoded to 32 MB. (#3095)
This change makes the EE recompiler not hardcoded to working with 32 MB of RAM, and instead work with the amount of RAM set in Ps2MemSize::MainRam. The rest of PCSX2 seems to work fine with more than 32 MB of RAM - it is only the EE recompiler that has trouble. If the Ps2MemSize::MainRam value is not changed from the default 32 MB, there should be no change: 32 MB / 0x10000 = 0x200, the value that was there previously.

This may be helpful if anybody else in the future wants to emulate a PS2 dev kit with 128 MB or RAM, or maybe the PSX dvr thing which I think has 64 MB of RAM. I've confirmed that with the change, you could set Ps2MemSize::MainRam to 128 MB, and execute code with the recompiler that's above the first 32 MB of RAM, and do VIF and scratchpad DMA transfers from this upper memory as well.
2020-05-12 23:03:38 -07:00
refractionpcsx2 184f0df2c5
Modify VU PC addressing so it only multiplies by 8 before entering the p… (#3362)
* Modify VU addressing so it only multiplies by 8 before entering the program
Fixes issues with VU1 TPC being read multiplied by 8 (bad)

* Removed assert on SuperVU which no longer makes sense
2020-05-12 23:59:42 +01:00
refractionpcsx2 4ce3fdfcb2 Fix up debugger stepping 2020-05-02 04:53:03 +01:00
refractionpcsx2 10dd9412a1 Fix CMSAR1 execution to use correct multiplier
Fix ILW/ISW/LQ/SQ on microVU for reading VU1 regs

Marvel Nemesis - Rise of the Imperfects goes ingame now, but it's quite messy
2019-12-30 15:26:44 +00:00
refractionpcsx2 908049a0fb pcsx2: DI execution is delayed by one instruction.
Fixes booting issues in the following games:
Jak X, Namco 50th anniversary, Spongebob the Movie, Spongebob Battle for Bikini Bottom,
The Incredibles, The Incredibles rize of the underminer, Soukou kihei armodyne, Garfield Saving Arlene, Tales of Fandom Vol. 2.

The games will no longer require a patch to boot.
2019-12-22 20:58:29 +01:00
gibbed b739e9187d pcsx2: Fix microVU debug logging. 2019-07-12 06:25:12 +02:00
arcum42 cc1a320c61 Remove sVU_Compare.h and iVU1micro.cpp, both of which appear unused. 2019-07-06 15:47:26 -07:00
Shanoah Alkire cc6a58da18 Remove sVU_Debug.h, as nothing in it is actually used anywhere. 2019-06-16 19:31:02 -07:00
hibye8313 56a976e277 microVU: Add gamefix for Crash Tag Team Racing. Fixes constant recompilation problems. 2019-04-30 22:57:11 +01:00
FlatOutPS2 17ac536116 pcsx2: Fix stall on branch .. in delay slot.
Fixes stall when loading a stage in WRC 3.

Original pr https://github.com/PCSX2/pcsx2/pull/1783

Collaborator: lightningterror
2019-04-10 04:06:18 +02:00
lightningterror 6905d4d883 x86emitter: Purge empty file sse_helpers.h.
Code was removed in
60a9463e7a
Right now it's useless.
Update VS/cmake project files to remove any mentions of the file as
well.
2019-02-18 11:51:06 +01:00
lightningterror ea38e2eba5 pcsx2: Remove/disable unused variables.
Removed:
MC2_SIZE in MemoryCardFile.cpp,
length in microVU_Log.inl
VU_Neg_Infinity in sVU_Upper.cpp.

Commented out:
mc_sizeinfo_8mb in Sio.cpp
2019-01-09 16:01:56 +01:00
Shanoah Alkire 51ceec74a3 A bit of cleanup. 2018-11-15 00:55:49 -08:00
Iritscen a3c6ad636b PCSX2: Add ability to pass launch arguments to games with CLI option '--gameargs="-arg1 -arg2 -etc (#2576)
For more information please check the PR (#2576) since it's a bit detailed.
2018-11-07 19:07:17 +01:00
Shanoah Alkire 122871654e Expand out a define to get rid of a warning. Get rid of other compiler warnings. Re-indent so that it doesn't look like a statement is part of an if statement when it isn't. 2018-10-27 02:49:03 -07:00
lightningterror d5700a8508 pcsx2: Update some redirect links. 2018-10-05 02:01:53 +02:00
refractionpcsx2 3c5fad7ef6 Reverted shift register stuff back to how it was, my changes made no difference now and it was slightly more optimal before.
Also fixed spaces (blame PSI :P )
2018-09-04 20:45:28 +01:00
refractionpcsx2 f7fb0f686b Fixed MFSA/MTSA, of course there's a game that abuses it (Rayman 3) 2018-09-04 20:26:36 +01:00
RedPanda4552 4dc4892588 Rename VU Cycle stealing to EE Cycle Skipping, and change tool tips for
EE Cycle Stealing and EE Cycle Skipping
2018-08-25 18:50:26 +02:00
refractionpcsx2 69888e5ab0 EE Rec/Int: Removed micro optimisation in QFSRV/MSTAB/MSTAH. Reverted functionality to match the documentation. There were some scenarios that weren't really accounted for, like developers doing what they're told not to do. 2018-07-15 13:14:46 +01:00
refractionpcsx2 9b82449542 Fixed optimisation problem on branch in branch delay slot. Fixes Dropship - United Peace Force. Props to MrCK1 for finding the issue. 2018-05-19 02:23:58 +01:00
Gregory Hainaut 02861fabc8 pcsx2|common: replace throw() by noexcept 2017-05-13 10:38:35 +02:00
Gregory Hainaut 47264dc350 core: use = default for trivial destructor
Again not reported by clang-tidy and done with sed
2017-05-13 10:38:35 +02:00
Gregory Hainaut 2ff43f2ed8 core: remove throw specifier on destructor
It is the 'default' on C++11
2017-05-13 10:38:35 +02:00
Jonathan Li 29eed182c2 pcsx2: Remove unnecessary aMax/aMin macros 2017-04-30 23:41:19 +01:00
Gregory Hainaut 0d3f02ee34 svu: cast variable to int to avoid unsigned vs int comparison 2017-04-30 21:20:23 +02:00
Volodymyr Kutsenko 6862106dee VU0: added a special case to the CFC2 instruction if it copies the value
from the TPC register (fixes Street Fighter EX3 #954 and R Racing
Evolution the invisible cars issue)
2017-02-23 04:38:26 +02:00
Gregory Hainaut bccc3ef253 Merge pull request #1770 from np511/gcc-cleanup
Cleanup GCC warnings - still needs some work
2017-01-30 15:28:33 +01:00
np511 15d66cf337 Properly format 2017-01-29 09:06:21 -05:00
Gregory Hainaut 5d119bec31 vif: init field in constructor + remove empty function 2017-01-22 16:23:40 +01:00
Gregory Hainaut ad7892bd15 svu: init all field of RANGE struct 2017-01-22 16:10:43 +01:00
Jonathan Li 285bcbcec0 vifUnpack: Report the correct number of bytes
It now reports 6904 bytes instead of just less than 4GB.
2017-01-07 14:49:33 +00:00
Gregory Hainaut 58e4076620 vif: update alignment constraint
16B alignment is now useless for nVifBlock (no more SSE)
However update the alignment of bucket to 64B. It will reduce cache miss
probability in the find loop
2016-12-18 22:51:23 +01:00
Gregory Hainaut d812222061 vif: use u32 code instead of u8/u16
It avoids memory stalls and greatly reduces the overhead of the dVifUnpack function

Here a vtune summary of this branch (done on SotC init)

dVifUnpack<1> was 14.5% of effective VU thread time
dVifUnpack<1> is now 3.8% of effective VU thread time

I hope it will translate to better fps
2016-12-18 22:44:24 +01:00
Gregory Hainaut ef75b36013 vif: move back the cache seach in the unpack function
Avoid the various move to return the value (actually due to the pointer)
2016-12-18 22:44:22 +01:00
Gregory Hainaut e4c2c53b19 vif: inline dVifsetVUptr function
It avoid a double cmp/jmp on the dynarec/interpreter mode.
2016-12-18 22:44:01 +01:00
Gregory Hainaut 6ae082dab2 vif: compute the length during the compilation stage 2016-12-18 22:44:00 +01:00
Gregory Hainaut 7a33cda122 vif: replace sse cmp code with standard cmp
Standard instruction are faster to execute besides the CPU can optimize the cmp/jne

SSE

  e0:	add    ecx,0x10
  e3:	cmp    eax,0x7
  e6:	jg     1b0 <void dVifUnpack<0>(unsigned char const*, bool)+0x1b0>
enter_loop:
  ec:	vpcmpeqd xmm0,xmm1,XMMWORD PTR [ecx]
  f0:	vmovmskps eax,xmm0
  f4:	cmp    eax,0x7
  f7:	jne    e0 <void dVifUnpack<0>(unsigned char const*, bool)+0xe0>

Standard cmp

  d8:	add    eax,0x10
  db:	mov    esi,DWORD PTR [eax+0xc]
  de:	test   esi,esi
  e0:	je     190 <void dVifUnpack<0>(unsigned char const*, bool)+0x190>
enter_loop:
  e6:	cmp    ecx,DWORD PTR [eax+0x4]
  e9:	jne    d8 <void dVifUnpack<0>(unsigned char const*, bool)+0xd8>
  eb:	cmp    DWORD PTR [eax+0x8],ebx
  ee:	jne    d8 <void dVifUnpack<0>(unsigned char const*, bool)+0xd8>

v2: use reference instead of a pointer for find parameter
2016-12-18 22:43:07 +01:00
Gregory Hainaut 2320efeb55 vif: increase buckets number to 64K
It allow to compare only 8B in the lookup so SSE could be replaced with general instruction

As a bonus, it allow to compute the hash key with a mov rather than modulo (which was an 'and')
2016-12-18 14:05:55 +01:00
Gregory Hainaut 1a32062439 vif: repack nVifBlock struct
cl/wl can fit in a single byte. Add a 2B length field instead.
It will contains the pre computed length to reduce dVifsetVUptr overhead
2016-12-18 14:05:55 +01:00
Gregory Hainaut d34e99b38b vif: handle the special case 0 in the compilation stage (rather than lookup) 2016-12-18 14:05:55 +01:00
Gregory Hainaut 555c96a941 vif: reorganize dVifUnpack
Inline the execution part
Add a num parameter to dVifsetVUptr
Use a local variable for the nVifBlock instead of a global struct state

The goal is to ease future update of the nVifBlock struct
2016-12-18 14:05:55 +01:00
Gregory Hainaut 10b3d429fe vif: new implementation of the hash bucket
Previous implementation saved the both the chain pointer and the chain size
Rational: size is useful to add new element and to detect the end of the chain
Vif cache is rarely miss. So 'add' is barely called and the end of a chain is
barely reached.

New implementation will add a null cell at the end of the chain. As a
cell contains a x86 pointer, if is null you could conclude that you
reach the end of the chain.

The 'add' function will traverse the chain to get the current size. It is
a cold path besides the chain is often short (< 4).

The 'find' function only need to check the startPtr bytes to detect the end
of the loop.

Note: SizeChain was replaced with a std::array
2016-12-18 14:05:53 +01:00
Gregory Hainaut c58b04979f vif: remove the type template of HashBucket
The class is designed and optimized for the layout of nVifBlock.
Besides it will ease future improvement.
2016-12-18 13:41:14 +01:00
Gregory Hainaut c368618d09 vif: use intrinsic cast instead of ugly define 2016-12-18 13:41:14 +01:00
Gregory Hainaut 1acc81c25d vif: don't allocate vifblock hash on the heap
Avoid an extra indirection to access the hash bucket (Find function)
2016-12-18 13:41:14 +01:00
Gregory Hainaut 3dc7dc0cdc vif: improve block compilation management
Safety:
* check remaining space before compilation
* clear hash if recompiler is reset

Perf:
* don't research the hash after a miss
* reduce branching in Unpack/ExecuteUnpack

Note: a potential speed optimization for dVifsetVUptr
Precompute the length and store in the cache. However it need 2B on the
nVifBlock struct. Maybe we can compact cl/wl. Or merge aligned with upkType
(if some bits are useless)
2016-12-18 13:41:13 +01:00
Gregory Hainaut b0b5c27fec vif: remove useless state from nVifStruct 2016-12-18 13:23:07 +01:00
Gregory Hainaut c2587abcea mVU: always call perf before leaving the compilation function
I misses some early return in my first tentative. Now VTune shows me
properly the time in VU recompiler.

Note: It seem some block overlap (likely due to the branching mess). But it is still way better than no data
2016-12-16 22:01:06 +01:00
Gregory Hainaut 632b4971de common: remove memset duplicates
Use standard memset instead of memset_8

Move memzero/memset8 in a common OS file.
2016-12-16 20:45:22 +01:00
Gregory Hainaut b9369e7c00 pcsx2: remove the reserve feature of recompiler memory
Cons:
* requires ~180MB of physical memory (virtual memory is the same so it
  doesn't impact the 4GB limit)

From steam: 98.81% got at least 2GB of RAM. 83.62% got at least 4GB of RAM.
That being said, it might not really increase RAM requirements as OS could put the
new allocation in the swap.

Pro:
* code is much easier
* remove at least half of the signal listener
* last but not least, it is way easier for profiler/debugger
2016-12-09 09:28:19 +01:00
Gregory Hainaut 2b8a808fe3 remove trailing white space (until I run clang-format on the full code) 2016-11-29 22:59:06 +01:00
Gregory Hainaut 4c3e98754e vif JIT: increment based on sizeof(T)
Struct on x64 will be 32B so +2 instead of +1
2016-11-28 19:07:04 +01:00
Gregory Hainaut 9862e5d207 vif hash: move bucket size check in the 'add' path instead of 'find' path
More logical this way
2016-11-28 19:07:04 +01:00
Gregory Hainaut c9db1c6c4b vtune: plug PCSX2 core + add missing profiling (VU/VIF/TLB)
Doesn't fully work yet
* Unknown stack frame
* Outside any known module

Potential root cause:
* Nvidia driver
* VU code as ebp is required for emulation so likely no frame
2016-11-28 19:07:04 +01:00
Gregory Hainaut 4fca5f4d88 mvu: use static array for dispatcher code
I don't understand why but standard mmap blew up Vtune
2016-11-28 19:07:04 +01:00
Gregory Hainaut a7e76438b2 iop: use const on some variables
Avoid coverity warning
2016-11-12 18:26:28 +01:00
Gregory Hainaut 056ecb1c39 pcsx2: add some cast to fix gcc (int vs uint) warning
I'm pretty sure that .RMSK (which is an u32:31) warnings are false positives
2016-11-12 17:36:40 +01:00
Gregory Hainaut 63c825d0e0 pcsx2: check return value of std functions
Avoid noisy gcc warnings
2016-11-12 17:36:06 +01:00
Gregory Hainaut 18f677d530 oups miss one minus 2016-11-08 23:11:12 +01:00
Gregory Hainaut f6c27c2abf pcsx2: use ASCII minus 2016-11-08 23:09:20 +01:00
Pseudonym b3b1f3ac68 IOP: Convert most IOP memory access in the IRX HLE and debugging module to
safe access through iopMem* functions.
2016-11-08 19:08:51 +00:00
Gregory Hainaut 253bd1aea3 linux compilation fix of previous iop change 2016-11-05 15:44:57 +01:00
Pseudonym 8259b29896 IOP: PSX bios console output 2016-11-05 12:14:01 +00:00
refractionpcsx2 ae57b960c2 Vif-Rec: Initialise IsAligned for VifUnpackSSE_Simple. Should fix the valgrind reported issue (no compatibility changes expected) 2016-11-04 22:31:07 +00:00
refractionpcsx2 471f33ceef Vif Unpack: initialise UnpkNoOfIterations before use. 2016-10-02 17:18:49 +01:00
Gregory Hainaut 6e6eae7844 pcsx2:gsdx:spu2x: use parenthesis around macro parameters
For safety reasons.
2016-09-18 16:13:55 +02:00
Gregory Hainaut b3d31869d6 recompiler: use a function to replace HWADDR macro 2016-09-18 16:13:55 +02:00
Gregory Hainaut 35cf2638e8 Vif: replace makeMergeMask macro with a function 2016-09-18 16:13:28 +02:00
Gregory Hainaut 4796803c33 pcsx2: Remove == true/false for boolean logic (#1556)
As discussed in #1553

Clang Tidy reports goes from 156 to 9.

Remain some macro in spu2x + a deadcode line
2016-09-10 20:08:14 +02:00
Gregory Hainaut 4ebe739b44 pcsx2: remove various unused variable
Warning can be reenabled on GCC

A warning isn't fixed as potentially the code is wrong
../pcsx2/gui/MemoryCardFolder.cpp: In member function ‘void FolderMemoryCard::FlushFileEntries(u32, u32, const wxString&, MemoryCardFileMetadataReference*)’:
../pcsx2/gui/MemoryCardFolder.cpp:1027:10: warning: unused variable ‘filenameCleaned’ [-Wunused-variable]
     bool filenameCleaned = FileAccessHelper::CleanMemcardFilename( cleanName );
2016-09-10 00:09:05 +02:00
Gregory Hainaut c8e9207879 svu: avoid a maybe uninitialized warning
False positive but compilers aren't reliable
2016-09-10 00:03:53 +02:00
Gregory Hainaut 244bb555f9 Merge pull request #1532 from ssakash/Coverity
PCSX2: Fix a bunch of coverity defects
2016-09-05 20:16:13 +02:00
Akash 022e650dc6 SuperVU: Initialize class members
CID 146985 (#1 of 1): Uninitialized pointer field (UNINIT_CTOR)8.
uninit_member: Non-static class member vuxy is not initialized in this
constructor nor in any functions that it calls
2016-09-03 20:29:50 +05:30
Gregory Hainaut 774d98991c iop rec: fully enable COP2 support 2016-09-02 21:05:28 +02:00
Gregory Hainaut b47c50ae5d iop rec: add the missing LWC2/SWC2 (CP2 reg from/to mem) 2016-09-01 21:50:13 +02:00
Gregory Hainaut 1ee0526e41 iop rec: add constant propagation for COP2
Inspirated from COP0
2016-09-01 21:16:43 +02:00
Gregory Hainaut bdc29dbbbf iop rec: put cop2 comment in the good position... 2016-09-01 20:47:12 +02:00
Gregory Hainaut d78d515acb iop rec: plug GTE (aka COP2) in the recompiler
Code isn't enabled yet to avoid any breakage

Edit iR3000ATables.cpp line 1446
2016-08-27 17:23:37 +02:00
Gregory Hainaut 1a8825b374 pcsx2|common|gsdx: use empty() instead of .size() ==/!= 0 check
Enhance readability reported by clang tidy
2016-08-21 17:20:13 +02:00
Gregory Hainaut bf0e5dc5bd Merge pull request #1516 from PCSX2/emitter-manual-void-cast
pcsx2: manually cast function pointer to void*
2016-08-17 18:56:55 +02:00
Gregory Hainaut cc68776069 pcsx2: manually cast function pointer to void*
Templace is nicer but give a hard time to compiler.

New version compile in both gcc&clang without hack

v2: add an uptr cast too for VS2013 sigh...
v3: use an ugly function pointer cast to please VS2013
2016-08-17 09:53:30 +02:00
Gregory Hainaut ef7530af29 microVU: fix aliasing issue
Union is safer for the compiler
2016-08-14 20:49:12 +02:00
Gregory Hainaut f28ab4c280 pcsx2: gcc warning sign compare 2016-08-12 19:30:14 +02:00
Akash bc54e3d01b R5900: Add a mild overclock option
* Adds a mild overclock option to have the 0 at middle of the slider.
2016-08-08 19:20:44 +05:30
Akash e738acbe3c R5900: Minor clean up (no functional change)
* Rename some variables as the previous names didn't make much sense.

* Convert unnecessary int data types to bool.
2016-08-08 18:45:00 +05:30
Gregory Hainaut 2844facae5 FPU/sVU: Fix GCC warning
may be used uninitialized in this function

Jump pointer are false positive but it helps to make compiler happy
2016-08-02 15:29:38 +02:00
Avi Halachmi (:avih) 6db1844656 patches: load correctly for the bios on full boot
We already had loading of the patches (and applying patch=0) before the
game elf recompiles, now do the same when the bios starts too.
2016-07-31 20:05:04 +03:00
Avi Halachmi (:avih) 5e3c2f0c6a eeCycleRage: negligible fix for the milest underclock calculation
This now makes the mildest underclock really identical to before 90b11b2 .
2016-07-30 18:11:35 +03:00
Avi Halachmi (:avih) 460b7be47a eeCycleRate: add/restore a milder underclock value to the slider
Also slightly modify the textual description of the other underclock items.

All previous values available at the slider are still there, but since
the new value is now the mildest (slider == -1), it "pushes" the previous
-1 and -2 values one notch down.

This restores the mildest value to be identical to how it behaved before
90b11b2f , which is measured as about 75% speed.

Because the "balanced" preset uses the -1 slider value, it means this
restored mild value is now also used by the balanced preset.

As a note, while the message for the mildest value was always "reduce by
about 33%", before 90b11b2f it was actually about 25% reduction (75% speed,
like with this commit now), and after that commit it was about 40% reduction
(60% speed).

Also, since we add new value to the slider only on one side, the "0"
(default) slider position is now not at the exact middle. That's fine,
but maybe we could also add a milder overclock value on the other side
to have that symetric again.
2016-07-30 17:36:34 +03:00
Avi Halachmi (:avih) 67dc3eef4b gui: eeCycleRate: more accurate description based on measurements
The ee cyclerate percentage values at the slider text were inaccurate,
and sometimes wildely so.

Add some code to measure the actual speed at runtime (disabled by default)
and update the (static) slider text values according to the measurements.

Also change the description from increase/reduce "by AA %" to "to BB %".

This makes it slightly easier to grasp. E.g. "reduce speed to 10%" is
easier to grasp than "reduce speed by 90%", and similarly, "increase
speed to 300%" is easier to grasp than "increase speed by 200%".
2016-07-30 16:04:27 +03:00
Pseudonym c782b6222c More robust eeload hooking to monitor and interfere with bios and game loading.
Maybe some other cruft can go now this should be reliable.
2016-07-29 16:51:18 +01:00
Robert Neumann eacd789a88 Fix an oversight (missing an include) 2016-07-29 14:06:27 +02:00
Avi Halachmi (:avih) 27e7ecce65 patches: load before recompiling the elf entry block
Commit 330704a added code which applies the patches before recompiling the
elf entry block, but because at that stage the patches for the current
CRC were not yet loaded, effectively it did nothing.

Now it actually loads the patches before applying them.

As a result, it should now be possible for patches (with place=0) to be
effective before the elf is executed.

This is a hack, because the emulation loads the patches while it's not
paused. It works, but it's not great. A better way would be to pause the
emulation once the entry point is detected, then make the setting get
applied normally (which also loads the patches normally), and then resume
the emulation.

This _should_ properly fix #627 (the test case works as expected now).
2016-07-28 22:25:00 +03:00
Gregory Hainaut 55bc7a678a pcsx2: ICC warning: type qualifier on return type is meaningless 2016-07-28 10:36:58 +02:00
Jonathan Li a9f9c1406c Merge pull request #1474 from turtleli/windows-64-bit-fixes
Windows 64-bit compile fixes
2016-07-28 00:19:04 +01:00
Avi Halachmi (:avih) cff8cb137c patches: simplify by unifying patches/cheats (effectively no-op)
patches and cheats are exactly the same (pnach style patch line) but we
stored two sets of them depending on their source: "patches" for
GameIndex.dbf patches, and "cheats" for all the rest (cheats, widescreen,
etc).

Unify patches and cheats and keep only "patches", cleanup and rename the
public API at Patch.h, and add documentation.

Also: add some console messages on invalid "place" value, and when we skip
searching cheats_ws.zip because a pnach file was found at cheats_ws dir.

Also: removed checks before applying different kinds of patches/cheats
because we don't need them (we didn't have disabled patches loaded anyway).

The checks removal _shouldn't_ have any effect, except that the checks were
wrong and accidentally prevented loading widescreen hacks which have a place
value of 0. No one probably noticed it since all the widescreen patches
which I looked at have a place value of 1. So now ws patches with place=0
would load correctly too. If we'll ever have such.
2016-07-27 18:15:17 +03:00
Avi Halachmi (:avih) eb1e890278 patches/cheats: document "place" value and use it explicitly
This commit doesn't change any behavior, but documents the "places" value
of the patch structure ("place" is 1 in patch=1,... and 0 in patch=0,...)
and also uses an enum to make its use explicit.
2016-07-27 14:21:37 +03:00
Jonathan Li 8387de09e2 pcsx2: Use _M_X86_64 for Baseblock static_assert ifdef
Fixes a 64-bit compilation issue.
2016-07-23 10:51:56 +01:00
Akash 72661e7c16 PCSX2-Core: Clean up some warnings on MSVC
x86emitter : Convert variable type from u8 to bool.
recVTLB: Cast "sign" to bool to prevent a warning.
R5900OpcodeImpl: Cast all the values in array to u64 instead of s64.
2016-06-30 16:49:18 +05:30
Pseudonym 36dd50005a Changed the M[FT]P[CS] instruction decoding logic to match results from this test:
https://github.com/unknownbrackets/ps2autotests/blob/master/tests/cpu/ee_cop0/performance.cpp
2016-06-23 20:57:43 +01:00
refractionpcsx2 67288b4735 A wild bracket has appeared! I choose you, delete button! 2016-05-29 14:13:45 +01:00
refractionpcsx2 bbecc3d0c2 microVU: Only spam "Reading VU1 Regs" warning in Dev mode and only when MTVU is enabled. It's useless when it isn't. 2016-05-29 13:23:25 +01:00
Gregory Hainaut e96b29f84f mVU: init microRegAlloc
CID 146988
2016-03-30 19:56:19 +02:00
NZJenkins ba706b6dab Check delay breakpoint condition
isBreakpointNeeded returns if breakpoints are needed for any combination
of the current pc and delay slot.
dynarecCheckBreakpoint checks conditions for each breakpoint slot.
2016-03-04 11:26:37 +13:00
Gregory Hainaut 40b1a3996a VU: port BaseVUmicroCPU to std::atomic 2016-02-28 15:29:31 +01:00
Gregory Hainaut e5d4f2c24f EE: use std::atomic<bool> for reset variable 2016-02-28 15:29:00 +01:00
Gregory Hainaut 38b9198dba Merge pull request #1173 from turtleli/replace-scoped-ptr
Replace ScopedPtr with unique_ptr
2016-02-13 13:49:18 +01:00
Gregory Hainaut 50caca4002 EE: replace EE/FPU mov opcode when FPU_RECOMPILE isn't enabled
It will be easier for testing if we change the format of the FPU register
2016-02-11 18:53:28 +01:00
Jonathan Li 499fed40f2 pcsx2: Convert ScopedPtr to unique_ptr 2016-02-08 22:31:45 +00:00
Jonathan Li 92bb849e7c Use unique_ptr instead of ScopedPtr for exceptions 2016-02-08 22:31:45 +00:00
Gregory Hainaut 5b74374bb2 Merge pull request #1169 from PCSX2/remove-mmx
Remove mmx
2016-02-08 19:17:24 +01:00
Gregory Hainaut fe0229aed0 EE: remove dead code 2016-02-08 09:52:31 +01:00
Gregory Hainaut 0f81482ed1 EE: remove most of MMX allocator code 2016-02-07 13:21:11 +01:00
Gregory Hainaut 278411898a EE: drop MMX/FPU state management
Useless as MMX code is removed
2016-02-07 13:07:55 +01:00
Gregory Hainaut 9af112b38f EE: remove _clearNeededMMXregs and deadcode
Nop because needed is always 0
2016-02-07 13:00:48 +01:00
Gregory Hainaut 095437d0c7 EE: _flushMMXregs is a nop because inuse==0 2016-02-07 12:57:56 +01:00
Gregory Hainaut 45443b48ef EE: freeMMXreg is a nop because inuse == 0 2016-02-07 12:56:30 +01:00
Gregory Hainaut 6f561d6bd7 EE: delete the nop _deleteMMXreg() 2016-02-07 12:53:17 +01:00
Gregory Hainaut c3afcffc50 EE: replace _checkMMXreg and _allocCheckGPRtoMMX
Both functions return -1

Remove all conditions (-1 >= 0)
2016-02-07 12:46:34 +01:00
Gregory Hainaut e1651c752a EE: mmxregs[i].inuse is never set to true
Let's remove code that depends on it

_deleteMMXreg/_checkMMXreg/_getNumMMXwrite/_flushMMXunused are now stub
2016-02-07 12:23:15 +01:00
Gregory Hainaut 054d8c4c9f EE: remove more unused MMX functions 2016-02-07 12:08:33 +01:00
Gregory Hainaut a0e619bcd7 VTLB: disable MMX optimization
memory copy will be done in SSE or X86 only. It is very unlikely that
it was used anyway (need 64 bits transfer and no XMM register available)

Remove the now useless _allocMMXreg and _getFreeMMXreg too
2016-02-07 12:06:41 +01:00
Gregory Hainaut 15390cd966 EE: remove unused MMX path
All commented and disabled code
2016-02-07 12:02:17 +01:00
Gregory Hainaut ea1a9943fc EE: disable the old mmx code
Time to test and report bug or speed issue.
2016-02-07 11:35:03 +01:00
Gregory Hainaut c2aa56ac38 EE: fix shift constant propagation in new SSE code
It seems constant must be flushed before any call to _allocGPRtoXMMreg
2016-02-06 16:47:44 +01:00
Gregory Hainaut fd4bc63854 EE: disable VF delete when SVU is disabled 2016-02-06 15:51:59 +01:00
Gregory Hainaut a9a955f8b9 EE: port MMX code to SSE for shift opcode
Code need to be enabled with a define (NO_MMX 1)

Code was tested with ps2autotest but it need more tests. I need to check
alignement issue too.

Globally code is potentially a little slower than SSE.
The trick is that we need to shift only the 64 lsb whereas SSE will
shift the full 128 bits register.

Current implementation flush the lsb and drop the full register. It is
unlikely that next intruction will be done in SSE anyway.

Note: it would be easier in x64 arch
2016-02-06 15:24:26 +01:00
Gregory Hainaut 119f6deb24 EE: add some assert(0) on likely unused code
if someone hit the assertion please report it
2016-02-05 00:27:29 +01:00
Gregory Hainaut 6ac76c86d7 recompiler: document the register allocation 2016-02-05 00:27:29 +01:00
Gregory Hainaut c20dc61f16 EE: fix compilation when branch recompilation is disabled 2016-01-31 23:45:08 +01:00
Johannes Obermayr ec3170752a Fix Linux build.
pcsx2/Dump.cpp: In function 'void iDumpBlock(u32, u32, uptr, u32)':
pcsx2/Dump.cpp:258:4: error: cannot convert 'wxString' to 'const char*' for argument '1' to 'int system(const char*)'

pcsx2/x86/iR3000A.cpp: In function 'void iIopDumpBlock(int, u8*)':
pcsx2/x86/iR3000A.cpp:285:45: error: cannot convert 'wxString' to 'const char*' for argument '1' to 'int system(const char*)'
2016-01-30 17:56:35 +01:00
refractionpcsx2 e5e0f85b50 Vif Rec: Emulate Mode = 3 for test, not sure any games use it.
Interpreter is still wrong, but currently crashy on this test, as it doesn't get this far I'm scared to change it in case it kills other stuff
2016-01-29 23:01:54 +00:00
Gregory Hainaut eaa211212d ee-fpu: upgrade the FPU to 3.0
properly return reserved register

Fix FCR test :)
2016-01-29 23:24:11 +01:00
refractionpcsx2 cf993c2a36 Vif-Rec: Fix skip size calculation.
(also a line ending issue, hope it doesn't mess it up lol)
2016-01-29 21:03:02 +00:00
Gregory Hainaut 2662809900 pcsx2:miss a rename of branch to g_branch
Fix compilation issue with no fpu recompiler
2016-01-29 19:53:21 +01:00
Gregory Hainaut c037686a26 iop: don't load any value in r0
Fix lsu.irx test
2016-01-27 20:08:37 +01:00
Gregory Hainaut b21ce8c9fb iop: fix division handling based on the EE div operator
Division will now handle properly division by 0 and signed overflow
2016-01-27 19:13:31 +01:00