mirror of https://github.com/PCSX2/pcsx2.git
EE: remove _clearNeededMMXregs and deadcode
Nop because needed is always 0
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095437d0c7
commit
9af112b38f
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@ -312,15 +312,9 @@ struct _mmxregs {
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};
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void _initMMXregs();
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void _clearNeededMMXregs();
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u8 _hasFreeMMXreg();
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int _getNumMMXwrite();
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// returns new index of reg, lower 32 bits already in mmx
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// shift is used when the data is in the top bits of the mmx reg to begin with
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// a negative shift is for sign extension
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extern int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift);
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extern _mmxregs mmxregs[iREGCNT_MMX], s_saveMMXregs[iREGCNT_MMX];
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extern u16 x86FpuState;
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@ -481,36 +481,6 @@ void _initMMXregs()
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s_mmxchecknext = 0;
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}
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__fi void* _MMXGetAddr(int reg)
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{
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pxAssert( reg != MMX_TEMP );
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if( reg == MMX_LO ) return &cpuRegs.LO;
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if( reg == MMX_HI ) return &cpuRegs.HI;
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if( reg == MMX_FPUACC ) return &fpuRegs.ACC;
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if( reg >= MMX_GPR && reg < MMX_GPR+32 ) return &cpuRegs.GPR.r[reg&31];
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if( reg >= MMX_FPU && reg < MMX_FPU+32 ) return &fpuRegs.fpr[reg&31];
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if( reg >= MMX_COP0 && reg < MMX_COP0+32 ) return &cpuRegs.CP0.r[reg&31];
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pxAssume( false );
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return NULL;
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}
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void _clearNeededMMXregs()
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{
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uint i;
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for (i=0; i<iREGCNT_MMX; i++) {
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if( mmxregs[i].needed ) {
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// setup read to any just written regs
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if( mmxregs[i].inuse && (mmxregs[i].mode&MODE_WRITE) )
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mmxregs[i].mode |= MODE_READ;
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mmxregs[i].needed = 0;
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}
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}
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}
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int _getNumMMXwrite()
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{
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uint num = 0, i;
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@ -532,18 +502,3 @@ void _signExtendSFtoM(uptr mem)
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xCWDE();
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xMOV(ptr[(void*)(mem)], eax);
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}
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int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift)
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{
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pxAssert( to >= 0 && shift >= 0 );
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SetMMXstate();
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if( shift > 0 ) xPSRA.D(xRegisterMMX(to), shift);
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xMOVD(ptr[&cpuRegs.GPR.r[gprreg].UL[0]], xRegisterMMX(to));
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xPSRA.D(xRegisterMMX(to), 31);
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xMOVD(ptr[&cpuRegs.GPR.r[gprreg].UL[1]], xRegisterMMX(to));
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mmxregs[to].inuse = 0;
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return -1;
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}
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@ -1309,7 +1309,6 @@ void recompileNextInstruction(int delayslot)
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case 0: case 1: case 2: case 3: case 0x10: case 0x11: case 0x12: case 0x13:
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Console.Warning("branch %x in delay slot!", cpuRegs.code);
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_clearNeededX86regs();
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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return;
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}
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@ -1318,7 +1317,6 @@ void recompileNextInstruction(int delayslot)
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case 2: case 3: case 4: case 5: case 6: case 7: case 0x14: case 0x15: case 0x16: case 0x17:
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Console.Warning("branch %x in delay slot!", cpuRegs.code);
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_clearNeededX86regs();
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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return;
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}
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@ -1359,7 +1357,6 @@ void recompileNextInstruction(int delayslot)
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//CHECK_XMMCHANGED();
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_clearNeededX86regs();
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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// _freeXMMregs();
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@ -186,7 +186,6 @@ void recSetBranchEQ(int info, int bne, int process)
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}
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}
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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}
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@ -211,7 +210,6 @@ void recSetBranchL(int ltz)
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if( ltz ) j32Ptr[ 0 ] = JGE32( 0 );
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else j32Ptr[ 0 ] = JL32( 0 );
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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}
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@ -586,7 +584,6 @@ void recBLEZ()
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x86SetJ8( j8Ptr[ 0 ] );
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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SaveBranchState();
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@ -634,7 +631,6 @@ void recBGTZ()
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x86SetJ8( j8Ptr[ 0 ] );
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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SaveBranchState();
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@ -807,7 +803,6 @@ void recBLEZL()
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if( !(g_cpuConstRegs[_Rs_].SD[0] <= 0) )
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SetBranchImm( pc + 4);
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else {
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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recompileNextInstruction(1);
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SetBranchImm( branchTo );
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@ -826,7 +821,6 @@ void recBLEZL()
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x86SetJ32( j32Ptr[ 0 ] );
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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SaveBranchState();
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@ -853,7 +847,6 @@ void recBGTZL()
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if( !(g_cpuConstRegs[_Rs_].SD[0] > 0) )
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SetBranchImm( pc + 4);
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else {
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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recompileNextInstruction(1);
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SetBranchImm( branchTo );
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@ -872,7 +865,6 @@ void recBGTZL()
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x86SetJ32( j32Ptr[ 0 ] );
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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SaveBranchState();
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@ -144,7 +144,6 @@ void recJALR()
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}
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}
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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recompileNextInstruction(1);
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