mirror of https://github.com/PCSX2/pcsx2.git
iop: fix division handling based on the EE div operator
Division will now handle properly division by 0 and signed overflow
This commit is contained in:
Gregory Hainaut
parent
11f59ada16
commit
b21ce8c9fb
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@ -506,114 +506,71 @@ void rpsxDIV_const()
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*/
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// Of course x86 cpu does overflow !
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if (g_psxConstRegs[_Rs_] == 0x80000000u && g_psxConstRegs[_Rt_] == 0xFFFFFFFFu) {
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// FIXME depends if div/divu
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xMOV(ptr32[&psxRegs.GPR.n.hi], 0);
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xMOV(ptr32[&psxRegs.GPR.n.lo], 0x80000000);
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return;
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}
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if (g_psxConstRegs[_Rt_] == 0) {
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// FIXME
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// hi must be rs
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// lo must be 0xFFFF_FFFFF is rs >= 0, 0x1 otherwise if rs < 0 and sign
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}
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if (g_psxConstRegs[_Rt_] != 0) {
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lo = *(int*)&g_psxConstRegs[_Rs_] / *(int*)&g_psxConstRegs[_Rt_];
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hi = *(int*)&g_psxConstRegs[_Rs_] % *(int*)&g_psxConstRegs[_Rt_];
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xMOV(ptr32[&psxRegs.GPR.n.hi], hi);
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xMOV(ptr32[&psxRegs.GPR.n.lo], lo);
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}
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}
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void rpsxDIVsuperconsts(int info, int sign)
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{
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u32 imm = g_psxConstRegs[_Rs_];
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if (imm == 0x80000000u) {
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// FIXME if RT is 0xFFFFFFFFu
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// hi must be 0
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// lo must be 0x80000000
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// FIXME depends if div/divu
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//
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// Otherwise standard division
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}
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if( imm ) {
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// Lo/Hi = Rs / Rt (signed)
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rt_]]);
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xCMP(ecx, 0);
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j8Ptr[0] = JE8(0);
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xMOV(eax, imm);
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if( sign ) {
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xCDQ();
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xDIV(ecx);
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}
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else {
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xXOR(edx, edx);
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xUDIV(ecx);
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}
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xMOV(ptr[&psxRegs.GPR.n.lo], eax);
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xMOV(ptr[&psxRegs.GPR.n.hi], edx);
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x86SetJ8(j8Ptr[0]);
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}
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else {
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xXOR(eax, eax);
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xMOV(ptr[&psxRegs.GPR.n.hi], eax);
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xMOV(ptr[&psxRegs.GPR.n.lo], eax);
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// FIXME lo must be 0xFFFF_FFFFF if rt is 0
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}
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}
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void rpsxDIVsuperconstt(int info, int sign)
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{
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u32 imm = g_psxConstRegs[_Rt_];
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if (imm == 0xFFFFFFFFu) {
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// FIXME if RS is 0x80000000
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// hi must be 0
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// lo must be 0x80000000
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// FIXME depends if div/divu
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//
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// Otherwise standard division
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}
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if( imm ) {
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xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
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xMOV(ecx, imm);
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//xCDQ();
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if( sign ) {
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xCDQ();
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xDIV(ecx);
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}
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else {
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xXOR(edx, edx);
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xUDIV(ecx);
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}
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xMOV(ptr[&psxRegs.GPR.n.lo], eax);
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xMOV(ptr[&psxRegs.GPR.n.hi], edx);
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} else {
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// FIXME
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// hi must be rs
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// lo must be 0xFFFF_FFFFF is rs >= 0, 0x1 otherwise if rs < 0 and sign
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xMOV(ptr32[&psxRegs.GPR.n.hi], g_psxConstRegs[_Rs_]);
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if (g_psxConstRegs[_Rs_] & 0x80000000u) {
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xMOV(ptr32[&psxRegs.GPR.n.lo], 0x1);
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} else {
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xMOV(ptr32[&psxRegs.GPR.n.lo], 0xFFFFFFFFu);
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}
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}
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}
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void rpsxDIVsuper(int info, int sign)
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void rpsxDIVsuper(int info, int sign, int process = 0)
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{
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// Lo/Hi = Rs / Rt (signed)
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rt_]]);
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xCMP(ecx, 0);
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j8Ptr[0] = JE8(0);
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xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
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if( process & PROCESS_CONSTT )
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xMOV(ecx, g_psxConstRegs[_Rt_]);
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else
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rt_]]);
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if( process & PROCESS_CONSTS )
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xMOV(eax, g_psxConstRegs[_Rs_]);
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else
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xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
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u8 *end1;
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if (sign) //test for overflow (x86 will just throw an exception)
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{
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xCMP(eax, 0x80000000 );
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u8 *cont1 = JNE8(0);
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xCMP(ecx, 0xffffffff );
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u8 *cont2 = JNE8(0);
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//overflow case:
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xXOR(edx, edx); //EAX remains 0x80000000
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end1 = JMP8(0);
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x86SetJ8(cont1);
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x86SetJ8(cont2);
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}
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xCMP(ecx, 0 );
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u8 *cont3 = JNE8(0);
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//divide by zero
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xMOV(edx, eax);
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if (sign) //set EAX to (EAX < 0)?1:-1
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{
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xSAR(eax, 31 ); //(EAX < 0)?-1:0
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xSHL(eax, 1 ); //(EAX < 0)?-2:0
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xNOT(eax); //(EAX < 0)?1:-1
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}
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else
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xMOV(eax, 0xffffffff );
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u8 *end2 = JMP8(0);
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// Normal division
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x86SetJ8(cont3);
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if( sign ) {
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xCDQ();
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xDIV(ecx);
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@ -623,22 +580,15 @@ void rpsxDIVsuper(int info, int sign)
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xUDIV(ecx);
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}
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if (sign) x86SetJ8( end1 );
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x86SetJ8( end2 );
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xMOV(ptr[&psxRegs.GPR.n.lo], eax);
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xMOV(ptr[&psxRegs.GPR.n.hi], edx);
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x86SetJ8(j8Ptr[0]);
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// FIXME if RS is 0x80000000 and RT is 0xFFFF_FFFFF
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// hi must be 0
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// lo must be 0x80000000
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// FIXME depends if div/divu
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// FIXME
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// hi must be rs
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// lo must be 0xFFFF_FFFFF is rs >= 0, 0x1 otherwise
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}
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void rpsxDIV_consts(int info) { rpsxDIVsuperconsts(info, 1); }
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void rpsxDIV_constt(int info) { rpsxDIVsuperconstt(info, 1); }
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void rpsxDIV_consts(int info) { rpsxDIVsuper(info, 1, PROCESS_CONSTS); }
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void rpsxDIV_constt(int info) { rpsxDIVsuper(info, 1, PROCESS_CONSTT); }
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void rpsxDIV_(int info) { rpsxDIVsuper(info, 1); }
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PSXRECOMPILE_CONSTCODE3_PENALTY(DIV, 1, psxInstCycles_Div);
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@ -653,11 +603,14 @@ void rpsxDIVU_const()
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hi = g_psxConstRegs[_Rs_] % g_psxConstRegs[_Rt_];
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xMOV(ptr32[&psxRegs.GPR.n.hi], hi);
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xMOV(ptr32[&psxRegs.GPR.n.lo], lo);
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} else {
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xMOV(ptr32[&psxRegs.GPR.n.hi], g_psxConstRegs[_Rs_]);
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xMOV(ptr32[&psxRegs.GPR.n.lo], 0xFFFFFFFFu);
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}
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}
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void rpsxDIVU_consts(int info) { rpsxDIVsuperconsts(info, 0); }
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void rpsxDIVU_constt(int info) { rpsxDIVsuperconstt(info, 0); }
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void rpsxDIVU_consts(int info) { rpsxDIVsuper(info, 0, PROCESS_CONSTS); }
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void rpsxDIVU_constt(int info) { rpsxDIVsuper(info, 0, PROCESS_CONSTT); }
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void rpsxDIVU_(int info) { rpsxDIVsuper(info, 0); }
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PSXRECOMPILE_CONSTCODE3_PENALTY(DIVU, 1, psxInstCycles_Div);
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