mirror of https://github.com/PCSX2/pcsx2.git
remove trailing white space (until I run clang-format on the full code)
This commit is contained in:
Gregory Hainaut
parent
704776027b
commit
2b8a808fe3
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@ -79,10 +79,10 @@ __fi void VifUnpackSSE_Dynarec::SetMasks(int cS) const {
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const vifStruct& vif = MTVU_VifX;
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//This could have ended up copying the row when there was no row to write.1810080
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u32 m0 = vB.mask; //The actual mask example 0x03020100
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u32 m0 = vB.mask; //The actual mask example 0x03020100
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u32 m3 = ((m0 & 0xaaaaaaaa)>>1) & ~m0; //all the upper bits, so our example 0x01010000 & 0xFCFDFEFF = 0x00010000 just the cols (shifted right for maskmerge)
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u32 m2 = (m0 & 0x55555555) & (~m0>>1); // 0x1000100 & 0xFE7EFF7F = 0x00000100 Just the row
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if((m2&&doMask)||doMode) { xMOVAPS(xmmRow, ptr128[&vif.MaskRow]); MSKPATH3_LOG("Moving row");}
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if (m3&&doMask) {
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MSKPATH3_LOG("Merging Cols");
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@ -97,10 +97,10 @@ __fi void VifUnpackSSE_Dynarec::SetMasks(int cS) const {
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void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const {
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pxAssertDev(regX.Id <= 1, "Reg Overflow! XMM2 thru XMM6 are reserved for masking.");
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int cc = aMin(vCL, 3);
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u32 m0 = (vB.mask >> (cc * 8)) & 0xff; //The actual mask example 0xE4 (protect, col, row, clear)
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u32 m3 = ((m0 & 0xaa)>>1) & ~m0; //all the upper bits (cols shifted right) cancelling out any write protects 0x10
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u32 m3 = ((m0 & 0xaa)>>1) & ~m0; //all the upper bits (cols shifted right) cancelling out any write protects 0x10
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u32 m2 = (m0 & 0x55) & (~m0>>1); // all the lower bits (rows)cancelling out any write protects 0x04
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u32 m4 = (m0 & ~((m3<<1) | m2)) & 0x55; // = 0xC0 & 0x55 = 0x40 (for merge mask)
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@ -110,15 +110,15 @@ void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const {
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if (doMask&&m2) { mergeVectors(regX, xmmRow, xmmTemp, m2); } // Merge MaskRow
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if (doMask&&m3) { mergeVectors(regX, xRegisterSSE(xmmCol0.Id+cc), xmmTemp, m3); } // Merge MaskCol
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if (doMask&&m4) { xMOVAPS(xmmTemp, ptr[dstIndirect]);
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if (doMask&&m4) { xMOVAPS(xmmTemp, ptr[dstIndirect]);
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mergeVectors(regX, xmmTemp, xmmTemp, m4); } // Merge Write Protect
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if (doMode) {
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u32 m5 = ~(m2|m3|m4) & 0xf;
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if (!doMask) m5 = 0xf;
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if (m5 < 0xf)
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{
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if (m5 < 0xf)
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{
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xPXOR(xmmTemp, xmmTemp);
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if (doMode == 3)
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{
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@ -130,7 +130,7 @@ void VifUnpackSSE_Dynarec::doMaskWrite(const xRegisterSSE& regX) const {
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xPADD.D(regX, xmmTemp);
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if (doMode == 2) mergeVectors(xmmRow, regX, xmmTemp, m5);
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}
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}
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else
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{
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@ -173,7 +173,7 @@ static void ShiftDisplacementWindow( xAddressVoid& addr, const xRegisterLong& mo
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void VifUnpackSSE_Dynarec::ModUnpack( int upknum, bool PostOp )
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{
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switch( upknum )
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{
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case 0:
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@ -199,7 +199,7 @@ void VifUnpackSSE_Dynarec::ModUnpack( int upknum, bool PostOp )
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pxFailRel( wxsFormat( L"Vpu/Vif - Invalid Unpack! [%d]", upknum ) );
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break;
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}
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}
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void VifUnpackSSE_Dynarec::CompileRoutine() {
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const int upkNum = vB.upkType & 0xf;
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@ -207,32 +207,32 @@ void VifUnpackSSE_Dynarec::CompileRoutine() {
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const int cycleSize = isFill ? vB.cl : vB.wl;
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const int blockSize = isFill ? vB.wl : vB.cl;
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const int skipSize = blockSize - cycleSize;
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uint vNum = vB.num ? vB.num : 256;
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doMode = (upkNum == 0xf) ? 0 : doMode; // V4_5 has no mode feature.
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UnpkNoOfIterations = 0;
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MSKPATH3_LOG("Compiling new block, unpack number %x, mode %x, masking %x, vNum %x", upkNum, doMode, doMask, vNum);
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pxAssume(vCL == 0);
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// Value passed determines # of col regs we need to load
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SetMasks(isFill ? blockSize : cycleSize);
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while (vNum) {
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ShiftDisplacementWindow( dstIndirect, ecx );
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if(UnpkNoOfIterations == 0)
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if(UnpkNoOfIterations == 0)
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ShiftDisplacementWindow( srcIndirect, edx ); //Don't need to do this otherwise as we arent reading the source.
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if (vCL < cycleSize) {
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ModUnpack(upkNum, false);
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xUnpack(upkNum);
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xMovDest();
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ModUnpack(upkNum, true);
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dstIndirect += 16;
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srcIndirect += vift;
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@ -266,7 +266,7 @@ _vifT static __fi u8* dVifsetVUptr(uint cl, uint wl, bool isFill) {
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vifStruct& vif = MTVU_VifX;
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const VURegs& VU = vuRegs[idx];
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const uint vuMemLimit = idx ? 0x4000 : 0x1000;
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u8* startmem = VU.Mem + (vif.tag.addr & (vuMemLimit-0x10));
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u8* endmem = VU.Mem + vuMemLimit;
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uint length = (v.block.num > 0) ? (v.block.num * 16) : 4096; // 0 = 256
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@ -39,7 +39,7 @@ void mergeVectors(xRegisterSSE dest, xRegisterSSE src, xRegisterSSE temp, int xy
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|| (xyzw==12) || (xyzw==11) || (xyzw==8) || (xyzw==3)) {
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mVUmergeRegs(dest, src, xyzw);
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}
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else
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else
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{
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if(temp != src) xMOVAPS(temp, src); //Sometimes we don't care if the source is modified and is temp reg.
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if(dest == temp)
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@ -78,7 +78,7 @@ void VifUnpackSSE_Base::xShiftR(const xRegisterSSE& regX, int n) const {
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void VifUnpackSSE_Base::xPMOVXX8(const xRegisterSSE& regX) const {
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if (usn) xPMOVZX.BD(regX, ptr32[srcIndirect]);
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else xPMOVSX.BD(regX, ptr32[srcIndirect]);
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else xPMOVSX.BD(regX, ptr32[srcIndirect]);
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}
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void VifUnpackSSE_Base::xPMOVXX16(const xRegisterSSE& regX) const {
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@ -88,8 +88,8 @@ void VifUnpackSSE_Base::xPMOVXX16(const xRegisterSSE& regX) const {
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void VifUnpackSSE_Base::xUPK_S_32() const {
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switch(UnpkLoopIteration)
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{
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switch(UnpkLoopIteration)
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{
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case 0:
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xMOV128 (workReg, ptr32[srcIndirect]);
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xPSHUF.D (destReg, workReg, _v0);
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@ -104,12 +104,12 @@ void VifUnpackSSE_Base::xUPK_S_32() const {
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xPSHUF.D (destReg, workReg, _v3);
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break;
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}
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}
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void VifUnpackSSE_Base::xUPK_S_16() const {
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if (!x86caps.hasStreamingSIMD4Extensions)
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if (!x86caps.hasStreamingSIMD4Extensions)
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{
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xMOV16 (workReg, ptr32[srcIndirect]);
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xPUNPCK.LWD(workReg, workReg);
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@ -119,8 +119,8 @@ void VifUnpackSSE_Base::xUPK_S_16() const {
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return;
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}
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switch(UnpkLoopIteration)
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{
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switch(UnpkLoopIteration)
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{
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case 0:
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xPMOVXX16 (workReg);
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xPSHUF.D (destReg, workReg, _v0);
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@ -135,12 +135,12 @@ void VifUnpackSSE_Base::xUPK_S_16() const {
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xPSHUF.D (destReg, workReg, _v3);
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break;
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}
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}
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void VifUnpackSSE_Base::xUPK_S_8() const {
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if (!x86caps.hasStreamingSIMD4Extensions)
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if (!x86caps.hasStreamingSIMD4Extensions)
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{
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xMOV8 (workReg, ptr32[srcIndirect]);
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xPUNPCK.LBW(workReg, workReg);
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@ -151,8 +151,8 @@ void VifUnpackSSE_Base::xUPK_S_8() const {
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return;
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}
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switch(UnpkLoopIteration)
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{
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switch(UnpkLoopIteration)
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{
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case 0:
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xPMOVXX8 (workReg);
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xPSHUF.D (destReg, workReg, _v0);
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@ -167,7 +167,7 @@ void VifUnpackSSE_Base::xUPK_S_8() const {
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xPSHUF.D (destReg, workReg, _v3);
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break;
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}
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}
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// The V2 + V3 unpacks have freaky behaviour, the manual claims "indeterminate".
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@ -177,19 +177,19 @@ void VifUnpackSSE_Base::xUPK_S_8() const {
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void VifUnpackSSE_Base::xUPK_V2_32() const {
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if(UnpkLoopIteration == 0)
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{
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if(UnpkLoopIteration == 0)
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{
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xMOV128 (workReg, ptr32[srcIndirect]);
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xPSHUF.D (destReg, workReg, 0x44); //v1v0v1v0
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xPSHUF.D (destReg, workReg, 0x44); //v1v0v1v0
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if(IsAligned)xAND.PS( destReg, ptr128[SSEXYZWMask[0]]); //zero last word - tested on ps2
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}
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else
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{
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xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2
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if(IsAligned)xAND.PS( destReg, ptr128[SSEXYZWMask[0]]); //zero last word - tested on ps2
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}
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}
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void VifUnpackSSE_Base::xUPK_V2_16() const {
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@ -199,7 +199,7 @@ void VifUnpackSSE_Base::xUPK_V2_16() const {
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if (x86caps.hasStreamingSIMD4Extensions)
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{
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xPMOVXX16 (workReg);
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}
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else
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{
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@ -213,19 +213,19 @@ void VifUnpackSSE_Base::xUPK_V2_16() const {
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{
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xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2
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}
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}
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void VifUnpackSSE_Base::xUPK_V2_8() const {
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if(UnpkLoopIteration == 0 || !x86caps.hasStreamingSIMD4Extensions)
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{
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if (x86caps.hasStreamingSIMD4Extensions)
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if (x86caps.hasStreamingSIMD4Extensions)
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{
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xPMOVXX8 (workReg);
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}
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else
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else
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{
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xMOV16 (workReg, ptr32[srcIndirect]);
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xPUNPCK.LBW(workReg, workReg);
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@ -238,23 +238,23 @@ void VifUnpackSSE_Base::xUPK_V2_8() const {
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{
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xPSHUF.D (destReg, workReg, 0xEE); //v3v2v3v2
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}
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}
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void VifUnpackSSE_Base::xUPK_V3_32() const {
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xMOV128 (destReg, ptr128[srcIndirect]);
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if(UnpkLoopIteration != IsAligned)
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if(UnpkLoopIteration != IsAligned)
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xAND.PS( destReg, ptr128[SSEXYZWMask[0]]);
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}
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void VifUnpackSSE_Base::xUPK_V3_16() const {
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if (x86caps.hasStreamingSIMD4Extensions)
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if (x86caps.hasStreamingSIMD4Extensions)
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{
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xPMOVXX16 (destReg);
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}
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else
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else
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{
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xMOV64 (destReg, ptr32[srcIndirect]);
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xPUNPCK.LWD(destReg, destReg);
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@ -270,15 +270,15 @@ void VifUnpackSSE_Base::xUPK_V3_16() const {
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if ((UnpkLoopIteration & 0x1) == 0 && result == 0){
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xAND.PS(destReg, ptr128[SSEXYZWMask[0]]); //zero last word on QW boundary if whole 32bit word is used - tested on ps2
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}
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}
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}
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void VifUnpackSSE_Base::xUPK_V3_8() const {
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if (x86caps.hasStreamingSIMD4Extensions)
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if (x86caps.hasStreamingSIMD4Extensions)
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{
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xPMOVXX8 (destReg);
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}
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else
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else
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{
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xMOV32 (destReg, ptr32[srcIndirect]);
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xPUNPCK.LBW(destReg, destReg);
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@ -294,11 +294,11 @@ void VifUnpackSSE_Base::xUPK_V4_32() const {
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void VifUnpackSSE_Base::xUPK_V4_16() const {
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if (x86caps.hasStreamingSIMD4Extensions)
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if (x86caps.hasStreamingSIMD4Extensions)
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{
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xPMOVXX16 (destReg);
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}
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else
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else
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{
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xMOV64 (destReg, ptr32[srcIndirect]);
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xPUNPCK.LWD(destReg, destReg);
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@ -308,11 +308,11 @@ void VifUnpackSSE_Base::xUPK_V4_16() const {
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void VifUnpackSSE_Base::xUPK_V4_8() const {
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if (x86caps.hasStreamingSIMD4Extensions)
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if (x86caps.hasStreamingSIMD4Extensions)
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{
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xPMOVXX8 (destReg);
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}
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else
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else
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{
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xMOV32 (destReg, ptr32[srcIndirect]);
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xPUNPCK.LBW(destReg, destReg);
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@ -448,4 +448,4 @@ void VifUnpackSSE_Init()
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void VifUnpackSSE_Destroy()
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{
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safe_delete( nVifUpkExec );
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}
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}
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