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1584 Commits

Author SHA1 Message Date
refractionpcsx2 7ee62b8222 GameDB/Patching: Add dynamic EE JIT patching 2022-12-28 13:55:26 +00:00
Stenzek 30b1129d60 Dump: Remove unused routines 
Sounds like these have been broken for some time, and I added new
dumping functions with the EErec refactor anyway.
 2022-12-25 09:27:44 +00:00
Stenzek a1ffe4deff x86: Warning fixes for clang-cl 2022-12-25 09:27:44 +00:00
Stenzek 96a1c77577 Core: Remove PCSX2_CORE define and leftovers from wx 2022-12-24 08:42:23 +00:00
Ty Lamontagne 2f0b244f48 Debugger: Initial debugger implementation 2022-12-24 07:21:49 +00:00
Ty Lamontagne 78c9b7f33e Debugger Core: Initial QT core work 
Revert 3ce242886b (Disabled force symbol loading) until solution is found

If this isn't caught when the game is loaded, the symbols will not be properly loaded while the game is running.

DisassemblyManager: Don't spin continuously if the guest CPU is dead
 2022-12-24 07:21:49 +00:00
Stenzek 2abbda924b x86/iR5900: Ignore double jr/jalr branches like others 2022-12-21 09:32:48 +00:00
TellowKrinkle 3204b98aaf microVU: Fix mVUcustomSearch 
Apparently NOT doesn't set flags
 2022-12-16 08:18:49 +00:00
Connor McLaughlin 1920bff007 x86/iR5900: Fix msub.s/madd.s when ACC isn't live 
Don't read EEREC_nnn without checking the process/valid bit first.
 2022-12-11 05:43:49 +00:00
Connor McLaughlin 05c12e2505 x86/iR5900: Don't flush regcache for store logging 
Makes it a bit easier to debug register cache issues.
 2022-12-11 05:43:49 +00:00
refractionpcsx2 40cb41399f VU: Correct XGKick timing when using XGKickSync 2022-12-04 19:44:15 +00:00
TellowKrinkle 44e69a9603 microVU: Adjust microRegInfo to match size of mVUCustomSearch 2022-12-03 00:52:10 -06:00
TellowKrinkle 91cba0ec45 microVU: Fix up mVUCustomSearch 
Fixes SSE4 version to follow WIN32 x86-64 calling convention (don't clobber xmm6 or xmm7)
Fixes AVX version to properly include fourth ymm register in result
 2022-12-03 00:52:10 -06:00
TellowKrinkle e0a0e0b00c microVU: Choose AVX2/SSE at runtime 2022-12-03 00:52:10 -06:00
lightningterror 276b1b5539 iR3000A: Fix variable is assigned a value that is never used warning. 
Codacy.
 2022-11-28 01:33:01 +01:00
TellowKrinkle 314c840293 VIF: Reduce alignment of empty hash buckets 
They'll never be in hot codepaths (since they're empty) and memalign with 64-byte alignment is noticeably slower than 16-byte alignment
 2022-11-25 20:20:24 +00:00
Connor McLaughlin edb9a5ba3c Qt: Add -testconfig option 2022-11-23 15:55:39 +00:00
Connor McLaughlin ef8e35032e x86/iR5900: Don't swap loadstore delay slots for BC0/BC2 conditions 
Swapping the loadstore could affect the condition of the instruction,
leading to incorrect code execution.

Fixes lock up in Oni after intro FMVs.
 2022-11-20 04:47:08 +00:00
lightningterror 93b24f98a6 microVU_Macro: Fix Wunused-variable warning. 2022-11-19 19:28:52 +01:00
lightningterror 32d52cb0dd recVTLB: Fix Wsign-compare warnings. 2022-11-19 19:28:52 +01:00
lightningterror 552d5d8928 iR5900Templates: Fix Wunused-variable warnings. 2022-11-19 19:28:52 +01:00
Connor McLaughlin 6793a84f9b x86/iR5900: Fix compiling with DUMP_BLOCKS 2022-11-19 06:16:44 +00:00
Connor McLaughlin 1ccddb92d4 EE Rec/IOP Rec: Rewrite large portions 
- Add fastmem
 - Add delay slot swapping
 - Add COP2 sync elision
 - Add block analysis and use analysis
 - Add GPR register caching and renaming
 2022-11-19 04:59:10 +00:00
Connor McLaughlin 8de4e190dc EERec: Disable large block splitting 2022-11-19 04:59:10 +00:00
Connor McLaughlin d17ceec14b EERec: Add block dumping 2022-11-19 04:59:10 +00:00
Connor McLaughlin fd194124a9 x86: Move cycle/writeback fields to CPU structs 
[SAVEVERSION+] Potentially better locality, keeps everything we're
accessing from the rec together.
 2022-11-19 03:54:02 +00:00
refractionpcsx2 be438587c7 mVU: Clean up range function and improve merging. Slim down cmpProg. 2022-11-19 02:35:25 +00:00
Connor McLaughlin a7af3cd483 x86/microVU: Write VIs from CTC2 as 16 bits 
The micro recompilers only write as 16 bit, so in case the value in the
register was greater than 0xFFFF, we don't want to store higher bits
that get stuck.
 2022-11-13 16:15:36 +00:00
Connor McLaughlin a12accf3fa x86/iR5900: Align LQC2/SQC2 to 16 bytes 
LQ/SQ were already 16 byte aligned.
 2022-11-13 16:15:36 +00:00
Connor McLaughlin 9daedf6f09 x86/microVU: Fix last block comparison for AVX2 2022-10-22 23:19:54 +01:00
refractionpcsx2 7aa05c08f1 EEJIT/COP2: Remove redundant instruction/allocation 2022-10-22 03:42:31 +01:00
refractionpcsx2 112ba57729 EE/JIT: Flush Rt on LDR/LDL before write 2022-10-22 03:42:31 +01:00
Florin9doi 8fbb1e5565 BIOS: Map the entire ROM1 file to PS2 memory 
EROM is part of ROM1, its exact location vary and can't be predicted
 2022-10-18 10:04:52 +01:00
Connor McLaughlin 48926a7ec4 x86/iR5900: Fix quadword stores on Linux 
Linux counts vector and GPR registers separately for which register
they get passed in when calling functions.

Windows uses the argument position.
 2022-10-16 14:41:33 +02:00
Connor McLaughlin d446e40741 System: Remove/move out a bunch more leftover stuff from wx 
The exceptions are particularly nasty, because there's nothing which
catches them.
 2022-10-14 22:24:42 +01:00
Connor McLaughlin 00bcb4cf02 System: Revamp memory allocation 
Guest memory is now mapped into a shared memory/file mapping, for use
with fastmem.

64-bit and 128-bit arguments are passed by register/value instead of by
reference/address.

LDL/LDR/SDL/SDR now use 64-bit GPRs instead of SSE.
 2022-10-14 22:24:42 +01:00
Connor McLaughlin ab295f0f10 x86/microVU: Add a reference list for quick block lookups 
This way, we can pack 8 entries in a single cache line, instead of one.
 2022-10-14 20:54:39 +01:00
Connor McLaughlin 197d4d1c81 x86/microVU: Use AVX2 for full block comparisons 2022-10-14 20:54:39 +01:00
Connor McLaughlin bf95193d5b x86/microVU: Use 64-bit comparisons for quick lookup 2022-10-14 20:54:39 +01:00
TellowKrinkle 738c8cb630 Core: Remove trailing whitespace from all files 2022-09-16 00:52:28 -05:00
Connor McLaughlin bc3729c930 iR5900: Skip reloading COP2 flags register when it's not used 2022-09-10 15:26:30 +01:00
Connor McLaughlin 5a0c8c9f32 iR5900Analysis: Always set COP2 status flag bit for VSQRT/VRSQRT/VDIV 
These update flags unconditional on FMAC.
 2022-09-10 15:26:30 +01:00
Connor McLaughlin 97960a2232 microVU: Fix program dumping 2022-09-02 11:21:30 +01:00
lightningterror 205cb2c29d iCore: Fix more negative array index warnings. 
Forgot these.
Codacy.
 2022-07-15 17:50:41 +02:00
lightningterror 1594b46f68 iCore: Fix negative array index warning. 
Codacy.
 2022-07-15 15:55:38 +02:00
Goatman13 df1e19dd47 COP2: Fix CTC2 to R register 
Only 23 bits are writable. Upper 9 bits are hardcoded to 001111111.
 2022-07-12 10:02:28 +01:00
refractionpcsx2 73c29d44c3 GS: Don't vmalloc inside fifo_alloc to avoid logic confusion. 
Also remove a pointless check from my previous COP2 fix.
 2022-06-28 09:29:47 +01:00
refractionpcsx2 bf0243c253 iR5900: Ignore Non delayed COP2 commands when not interlocked 2022-06-27 23:32:25 +01:00
refractionpcsx2 391bd119b8 VU: Don't clamp VF00 or I Reg 2022-06-27 14:44:57 +01:00
Connor McLaughlin cdd9b1fa3b iR5900: Elide VU0 micro finish calls when safe 
This makes a difference in COP2-heavy games, where a chain of
instructions will repeatedly test the VU0 idle bit unnecessarily, as it
is impossible for a micro to be started inbetween the instruction chain.

Saves a bit of code size (for register backup/restore), as well as
getting rid of branches. Seems to make a 1-2% difference in performance
in Ratchet on a 3900X, but if we're lucky, more on slower chips.
 2022-06-27 14:44:48 +01:00
Ty Lamontagne 15d8b891d6 Core: Replace old include guard with pragma once 2022-06-26 12:42:10 +02:00
lightningterror cf568d2782 iR5900: Cleanup variable scope. 
Codacy.
 2022-06-25 11:20:53 +02:00
lightningterror ba07e46cf8 iR3000A: Cleanup variable scope. 
Codacy.
 2022-06-25 11:20:53 +02:00
lightningterror f19ba1b0db iFPUd: Cleanup variable scope. 
Codacy.
 2022-06-25 11:20:53 +02:00
lightningterror 51887f1cbc BaseBlockEx: Cleanup variable scope. 
Codacy.
 2022-06-25 11:20:53 +02:00
lightningterror b54521de51 iR5900: Cleanup variable scope. 
Codacy.
 2022-06-24 23:32:30 +02:00
lightningterror d7e09167fa iMMI: Cleanup variable scope. 
Codacy.
 2022-06-24 23:32:30 +02:00
lightningterror 26d20e458c iFPU: Cleanup variable scope. 
Codacy.
 2022-06-24 23:32:30 +02:00
Connor McLaughlin aa47018197 Qt: Apply patches on entry point compile 
Fixes WRC4's entrypoint patch not being used.
 2022-05-24 18:00:59 +01:00
Connor McLaughlin ea051c6d5f Everything: Get rid of wx entirely from the Qt build 2022-05-22 13:58:56 +01:00
Connor McLaughlin 893b3c629d Everything: Remove a **lot** of wx, and px nonsense 
- common has no wx left except for Path.
 - pcsx2core only has it in a few places (memory cards and path related
   stuff).
 2022-05-22 13:58:56 +01:00
Connor McLaughlin d535331b4b Misc: Remove __fastcall, __fc, __concall and friends 
These have no meaning in x64 (apart from throwing compiler warnings),
and we don't do 32-bit anymore. Also saves needing to include
`Pcsx2Defs.h` in files which don't otherwise need it.
 2022-05-12 14:58:03 +01:00
Connor McLaughlin d2347d9972 Common/Threading: Replace TLS macros with standard thread_local 2022-05-09 16:06:33 +01:00
Connor McLaughlin f8dcff9fc4 Common: Remove references to pthreads4w 
It's only needed for wx now.
 2022-05-09 16:06:33 +01:00
Connor McLaughlin 756cd1ee47 System: Move old SysThread junk to gui 2022-05-08 05:40:59 +01:00
Connor McLaughlin 599626b709 MTVU: Purge pxThread 2022-05-07 15:43:03 +01:00
Mrlinkwii c86dd7397d microVU : correct logging and remove not needed comments 2022-05-05 23:13:33 +01:00
arcum42@gmail.com d45f34ee8b Remove iMisc.cpp, and move the code to System.cpp/h. 2022-05-01 11:43:14 +01:00
Connor McLaughlin 2634134481 microVU: Remove unused VSync() callback 2022-05-01 11:36:37 +01:00
refractionpcsx2 68c2a68087 microVU: Clean up warnings 2022-04-16 03:20:54 +01:00
kenshen112 fdabc82342 Remove IopCommon.h added proper includes to files. Removing circle includes in several files that sometimes was several layers deep 2022-04-11 21:25:20 +01:00
Connor McLaughlin 3801825793 R3000A/R5900: Refactor interpreter/recompiler exits 
Now, IOP breakpoints work nice and reliably in both interpreter and
recompiler, exiting as soon as possible, without leaving the event state
indeterminate.
 2022-04-06 15:27:15 +01:00
Connor McLaughlin 5ac9419703 R5900: Make CPU exits consistent and safe 
Previously, we would either throw an exception (ints), or longjmp out of
the recompiler when the execution state was checked. Unfortunately for
our stability, this happened at the end of the frame, just before it was
pushed to the GS, and in the middle of processing EE events (!).

Doing so not only meant that we executed a bunch of event
testing/exception code twice (once after we paused, again when we
resumed), but it also could potentially leave things in an inconsistent
state.

So instead, let's do it safely with a flag, replacing the old
iopBreakpoint flag, so there's no additional overhead on the hot path.
 2022-04-06 15:27:15 +01:00
Connor McLaughlin e6c8354ec8 EERec: Purge PCSX2_SEH define 
No longer needed since we don't have 32-bit.
 2022-04-03 07:57:02 +01:00
Connor McLaughlin a1e77002c3 iR5900: Exit on NeedsReset not IsReset 
This is an edge case which can be hit in Goemon, but also when changing
settings in Qt, as they will be applied at guest vsync time, which is
called within the JIT.

Also, do the reset before entering JIT code, rather than when the first
block is compiled.
 2022-04-03 07:57:02 +01:00
lightningterror 0d4394a749 core: Clean up 32bit code. 2022-03-21 20:21:36 +01:00
arcum42@gmail.com 33e0ac729e Core: Remove memcmp_mmx. 2022-03-20 12:54:58 +00:00
Christian Kenny 26561261bc Core: Remove unused code 2022-03-20 04:00:27 +00:00
refractionpcsx2 ccd86a242c EE/VU JIT: Remove 32bit code 2022-03-20 00:39:39 +00:00
refractionpcsx2 fd4a5acc40 MTVU: Try to make T-Bit more reliable. 
Add MTVUSpeedHack option to GameDB so it can be forcefully disabled
 2022-03-11 10:25:15 +00:00
refractionpcsx2 b4e6a715fc EE/JIT: Flush const on LDL/LDR instructions 2022-03-03 16:18:16 +00:00
refractionpcsx2 e833a67bb7 VU: Rework VUKickstart in to VUSync, swap behaviour 2022-02-28 19:29:53 +00:00
refractionpcsx2 6dc5087cbd VU: Run sync ahead on small blocks 2022-02-28 19:29:53 +00:00
Connor McLaughlin 845e7930d7 microVU: Move VU0 micro flag instance setup to program start 
They're only used in micro mode, so no point updating them in a cop2
chain.
 2022-02-28 15:07:15 +00:00
Connor McLaughlin d20bfa240d EE: Add COP2 flag hack 2022-02-28 15:07:15 +00:00
Ty Lamontagne 6ab77be8fc COP2: Move COP2 timing messages to release builds. 2022-02-14 01:52:44 +00:00
C.W. Betts 9b7e87c043 Mark static functions in headers as static inline: 
This quiets unused function warnings (-Wunused-function) which is on by default on Xcode.
 2022-02-07 02:32:56 +00:00
Ty Lamontagne a632f3c5cb Core: Lighten IOP breakpoint load 
standardizeBreakpintAddress calls on the IOP just return the address unmodified. Considering this is called at least once every load / store instruction when there is an IOP OR EE memcheck enabled, it's pretty hot.
 2022-02-04 16:52:27 +00:00
refractionpcsx2 bcade5bb9d mVU: Clean up branch chain handling 2022-01-23 20:31:08 +00:00
refractionpcsx2 59ab303c5c mVU: Rework multiple branch chaining 2022-01-23 20:31:08 +00:00
refractionpcsx2 e5a4f27e79 VU: Adjust path for conditional evil blocks 
Add patch for Pac-man World Rally
 2022-01-22 21:43:45 +00:00
Connor McLaughlin 08ecf3f582 iR5900: Use unsigned math for constant prop of add/sub 
Signed overflow is undefined.
 2022-01-17 20:08:11 +01:00
Connor McLaughlin 252562db90 Misc: #ifdef out last bits of wx-dependent code 2021-12-28 05:22:45 +00:00
Connor McLaughlin 9166218d07 EERec: Remove zero-distance jmp in full fpu mode 2021-12-13 00:56:50 +00:00
refractionpcsx2 0a79892923 microVU: Preserve XGKIck cycles in delay slot 
Also added handling for xgkick sync on single instructions
 2021-11-21 17:18:34 +00:00
TellowKrinkle f7476dfb63 Core: Replace alignment macros with alignas 2021-11-14 13:52:20 -06:00
TellowKrinkle 2351431d71 Misc: Remove custom countof macros in favor of std::size 2021-11-14 13:52:20 -06:00
refractionpcsx2 6a8287ea9f EE JIT: Backup shift on LDR/L if rs==rt 2021-11-03 18:03:09 +00:00
lightningterror 667f98334a iR5900: Fix Wodr warnings. 2021-10-27 01:00:38 +02:00
refractionpcsx2 bfbe86a3d5 COP2: Tighten LQC2/SQC2 sync 
Fixes some small glitches with the R&C games
 2021-10-26 00:05:46 +01:00
refractionpcsx2 24e73b3134
Savestates: Add missing things from Savestates (#4917) 
Savestates: Add missing variables from Savestates
 2021-10-20 10:41:50 +01:00
refractionpcsx2 5011b9ead5 EE: Cyclerate > 1 caused some cycles to be lost 2021-10-19 20:09:07 +01:00
refractionpcsx2 6746578120 VU JIT: Include ADDi in flag calculations 
Fixes #4916
 2021-10-18 12:32:44 +01:00
Connor McLaughlin 44bc273590 microVU: Use uncached reg when clamping for FMAC instructions 2021-10-17 15:54:58 +01:00
TellowKrinkle f22ba886d9 Fix unparenthesized macro input 2021-10-17 04:17:58 +01:00
refractionpcsx2 a96f900760 COP2: Simplify reg allocation 2021-10-14 10:06:13 +01:00
Ziemas 45bb57a38c IOP Recompiler: Fix BIOS trace logging on 64bit 2021-10-13 22:42:51 +02:00
refractionpcsx2 ae1f1599f6 COP2: Fix reg allocation issue 
Really fixes Devil May Cry which was a bug hidden by clamping hidden by a bug, yeah i think that covers it all...
 2021-10-07 23:29:04 +01:00
Connor McLaughlin ca523edf0e Config: Move folders to their own namespace 
Don't duplicate in EmuOptions.
 2021-10-01 23:46:52 -04:00
Connor McLaughlin 4d8905abd6 Config: Swap out wxString for std::string 
Also in CDVD.
 2021-10-01 23:46:52 -04:00
Connor McLaughlin 77a890ff4a Config: Move Folders/BaseFilenames to base config 2021-10-01 23:46:52 -04:00
Connor McLaughlin 8e1470f637 iR5900: Use fastjmp instead of longjmp 2021-10-01 23:30:39 +01:00
Connor McLaughlin 91627b28b4 R5900: Get rid of ScopedBools 2021-10-01 23:30:39 +01:00
lightningterror a25dc9c38c ICore: Cleanup Wsign-compare warnings. 2021-09-30 01:07:59 +02:00
refractionpcsx2 7faa5db9e5 VU/GameDB: Move Mac/Status overflow flag checks to a gamefix 
We can't really do this reliably on x86 without soft floats, but superman still needs it, but it breaks other games.
 2021-09-29 17:33:13 +01:00
Ty Lamontagne aef731fdbe MicroVU: Fix branch type detection 
amendment of 589aba
 2021-09-26 05:13:28 +01:00
refractionpcsx2 f5f44286bf EE: 64bit compare for 64bit mode, not 32bit 2021-09-22 19:57:40 +01:00
TellowKrinkle 65e57a8230 iR5900: Use 64-bit math on x86-64 2021-09-22 12:47:49 +01:00
TellowKrinkle e74ba82093 iR5900: Move repeated code into functions 2021-09-22 12:47:49 +01:00
TellowKrinkle 0d7f141279 EERec: Don't load in skip case of SW[LR] 2021-09-21 22:57:41 +01:00
TellowKrinkle 23578e963f EERec: Don't load in skip case of SD[LR] 2021-09-21 22:57:41 +01:00
TellowKrinkle e9518f78c7 vtlb: Switch read64 and read128 handlers to return in sse regs 2021-09-21 22:57:41 +01:00
TellowKrinkle 7563f54e83 EERec: Clean up [LS]D[LR] a bit 2021-09-21 22:57:41 +01:00
refractionpcsx2 e127ca0cd1 COP2: Set correct number of XMM's per COP2 OP + Fix some hidden bugs 
Corrects XMM count for COP2 ops (some might be wrong, keep an eye out in the logs)
Fixes a hidden microVU bug with a SUB shortcut + some reg allocation bugs in QMFC/QMTC hidden by flushes.
 2021-09-21 22:46:33 +01:00
refractionpcsx2 752957604e COP2: Flush only needed register slots 2021-09-21 22:46:33 +01:00
refractionpcsx2 fba9c6c04d COP2: never flush EE regs but back them up conditionally 2021-09-21 22:46:33 +01:00
refractionpcsx2 8fe0061751 VU: Sync tighter when VU Kickstart is disabled + Improved M-Bit Sync 2021-09-19 18:49:24 +01:00
Connor McLaughlin e2992cbc02 Remove gui/ directory from target-wide includes 2021-09-17 22:03:00 -04:00
refractionpcsx2 a546cb8f7f microVU: Use 16 xmm's in x64 2021-09-17 14:37:11 +01:00
refractionpcsx2 862d606514 EE Rec: Added LDR/LDL 
Also fixed slight optimisation bug in SDL
 2021-09-17 13:06:47 +01:00
refractionpcsx2 5f58c325ca EE JIT: Implement SDR/SDL instructions 2021-09-17 13:06:47 +01:00
refractionpcsx2 d9c4ace613 VU: Put XGKick 1 cycle behind to fix sync issues with Jaws Unleashed 
Also added Jaws unleashed xgkick gamefixes to the DB
 2021-09-17 13:04:26 +01:00
refractionpcsx2 59dfe52b52 microVU: Replace XGKick hack with synced XGKick option 
Fixes Tennis Court Smash and Love Smash games which previously couldn't be fixed.
WRC no longer requires a patch, just the xgkickhack option.

Note: it's not a hack anymore, it just has to be called that :P
 2021-09-17 13:04:26 +01:00
refractionpcsx2 73bb8e4fdf VU Int: Make XGKick flush on VU program end 
Some games like to write directly to VU memory once the program has finished and I have no easy way to update the kick without being super slow. so for now, we'll just flush it.
 2021-09-12 16:12:31 +01:00
refractionpcsx2 3f56414824 VIF/VU: Cleaned up VIF Stall behaviour, sync XGKick with Unpacks. 
Also cleaned up a bunch of bad/old code
Fixed branches on E-Bit and M-Bit (VU0)
Fixed up VU Int behaviour with VU Instant on/off

Savestate bump
 2021-09-12 16:12:31 +01:00
refractionpcsx2 b4eaf3722f VU: Adjust timings of VU calls 2021-09-12 16:12:31 +01:00
Ty Lamontagne ab64023e56 MicroVU: Cleanup stale comments and code 2021-09-11 01:33:02 +01:00
Ty Lamontagne 18311d6a4c MicroVU: Purge Min/Max speedhack 2021-09-06 21:36:10 +01:00
Ty Lamontagne 589aba3713 [MicroVU] Revert "bla" 
This reverts commit 6800753f09.
 2021-09-06 19:53:08 +01:00
Ty Lamontagne f91286dbf3 MicroVU: Skip VU1 instructions on VU0 2021-09-05 21:18:19 +01:00
refractionpcsx2 b919de9dd1 VU: Adjust sync timing for VU Kickstart 
Fixes Crash Twinsanity
 2021-09-05 18:14:53 +01:00
lightningterror c2dad218e5 microVU: Combine mVU0cacheReserve and mVU1cacheReserve. 2021-09-05 18:06:46 +02:00
refractionpcsx2 ddb300027c VU: Improve sync during interlock and Scratchpad VU mem writes 
Also added some setting of next block cycles to 0 in cases where we don't know ahead of compile time or the VU is ending.
 2021-09-05 16:37:43 +01:00
TellowKrinkle dae8e0d233 Core: Remove unused mmx stuff 2021-09-04 18:28:24 -04:00
TellowKrinkle 5260d63565 Core: Format recompilers 2021-09-04 18:28:24 -04:00
kojin 8fdaaa2eab common: reorganize 2021-09-04 18:28:07 -04:00
refractionpcsx2 bda80fc748 Clang Format VU files 2021-08-31 21:29:31 +01:00
refractionpcsx2 d8dfe0a1e9 VU: optimise entering VU JITs 
Keeps note on how many cycles it needs for the next block to save exiting the EE JIT and entering the microVU JIT for no reason
 2021-08-31 21:29:31 +01:00
Connor McLaughlin d7de81aaaa iR5900: Make const register write clearer 
This was apparently sign extending anyway, but using SD makes it clear
that the 32-bit assignment will sign extend to 64-bit.
 2021-08-17 14:43:24 -04:00
Connor McLaughlin a216f28c9d iR5900: Use a signed multiply for MULT1 const prop 2021-08-17 14:43:24 -04:00