mirror of https://github.com/PCSX2/pcsx2.git
EE: port MMX code to SSE for shift opcode
Code need to be enabled with a define (NO_MMX 1) Code was tested with ps2autotest but it need more tests. I need to check alignement issue too. Globally code is potentially a little slower than SSE. The trick is that we need to shift only the 64 lsb whereas SSE will shift the full 128 bits register. Current implementation flush the lsb and drop the full register. It is unlikely that next intruction will be done in SSE anyway. Note: it would be easier in x64 arch
This commit is contained in:
Gregory Hainaut
parent
119f6deb24
commit
a9a955f8b9
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@ -748,6 +748,7 @@ void _deleteACCtoXMMreg(int vu, int flush)
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// Flush is 0: _freeXMMreg. Flush in memory if MODE_WRITE. Clear inuse
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// Flush is 1: Flush in memory. But register is still valid
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// Flush is 2: like 0 ...
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// Flush is 3: drop register content
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void _deleteGPRtoXMMreg(int reg, int flush)
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{
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int i;
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@ -775,6 +776,10 @@ void _deleteGPRtoXMMreg(int reg, int flush)
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if( flush == 2 )
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xmmregs[i].inuse = 0;
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break;
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case 3:
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xmmregs[i].inuse = 0;
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break;
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}
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return;
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@ -20,6 +20,8 @@
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#include "R5900OpcodeTables.h"
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#include "iR5900.h"
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#define NO_MMX 0
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using namespace x86Emitter;
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namespace R5900 {
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@ -143,6 +145,22 @@ void recDSLLs_(int info, int sa)
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int rtreg, rdreg;
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pxAssert( !(info & PROCESS_EE_XMM) );
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#if NO_MMX
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_addNeededGPRtoXMMreg(_Rt_);
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_addNeededGPRtoXMMreg(_Rd_);
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rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE);
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if( rtreg != rdreg ) xMOVDQA(xRegisterSSE(rdreg), xRegisterSSE(rtreg));
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xPSLL.Q(xRegisterSSE(rdreg), sa);
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// flush lower 64 bits (as upper is wrong)
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// The others possibility could be a read back of the upper 64 bits
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// (better use of register but code will likely be flushed after anyway)
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xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_deleteGPRtoXMMreg(_Rd_, 3);
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#else
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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@ -151,6 +169,7 @@ void recDSLLs_(int info, int sa)
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if( rtreg != rdreg ) xMOVQ(xRegisterMMX(rdreg), xRegisterMMX(rtreg));
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xPSLL.Q(xRegisterMMX(rdreg), sa);
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#endif
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}
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void recDSLL_(int info)
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@ -171,6 +190,22 @@ void recDSRLs_(int info, int sa)
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int rtreg, rdreg;
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pxAssert( !(info & PROCESS_EE_XMM) );
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#if NO_MMX
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_addNeededGPRtoXMMreg(_Rt_);
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_addNeededGPRtoXMMreg(_Rd_);
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rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE);
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if( rtreg != rdreg ) xMOVDQA(xRegisterSSE(rdreg), xRegisterSSE(rtreg));
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xPSRL.Q(xRegisterSSE(rdreg), sa);
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// flush lower 64 bits (as upper is wrong)
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// The others possibility could be a read back of the upper 64 bits
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// (better use of register but code will likely be flushed after anyway)
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xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_deleteGPRtoXMMreg(_Rd_, 3);
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#else
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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@ -179,6 +214,7 @@ void recDSRLs_(int info, int sa)
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if( rtreg != rdreg ) xMOVQ(xRegisterMMX(rdreg), xRegisterMMX(rtreg));
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xPSRL.Q(xRegisterMMX(rdreg), sa);
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#endif
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}
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void recDSRL_(int info)
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@ -199,6 +235,42 @@ void recDSRAs_(int info, int sa)
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int rtreg, rdreg, t0reg;
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pxAssert( !(info & PROCESS_EE_XMM) );
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#if NO_MMX
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_addNeededGPRtoXMMreg(_Rt_);
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_addNeededGPRtoXMMreg(_Rd_);
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rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE);
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if( rtreg != rdreg ) xMOVDQA(xRegisterSSE(rdreg), xRegisterSSE(rtreg));
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if ( sa ) {
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t0reg = _allocTempXMMreg(XMMT_INT, -1);
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xMOVDQA(xRegisterSSE(t0reg), xRegisterSSE(rtreg));
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// it is a signed shift (but 64 bits operands aren't supported on 32 bits even on SSE)
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xPSRA.D(xRegisterSSE(t0reg), sa);
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xPSRL.Q(xRegisterSSE(rdreg), sa);
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// It can be done in one blend instruction in SSE4.1
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// Goal is to move 63:32 of t0reg to 63:32 rdreg
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{
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xPSHUF.D(xRegisterSSE(t0reg), xRegisterSSE(t0reg), 0x55);
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// take lower dword of rdreg and lower dword of t0reg
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xPUNPCK.LDQ(xRegisterSSE(rdreg), xRegisterSSE(t0reg));
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}
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_freeXMMreg(t0reg);
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}
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// flush lower 64 bits (as upper is wrong)
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// The others possibility could be a read back of the upper 64 bits
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// (better use of register but code will likely be flushed after anyway)
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xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_deleteGPRtoXMMreg(_Rd_, 3);
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#else
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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@ -221,6 +293,7 @@ void recDSRAs_(int info, int sa)
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_freeMMXreg(t0reg);
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}
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#endif
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}
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void recDSRA_(int info)
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@ -314,10 +387,25 @@ EERECOMPILE_CODEX(eeRecompileCode2, DSRA32);
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__aligned16 u32 s_sa[4] = {0x1f, 0, 0x3f, 0};
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int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int shift64)
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void recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp)
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{
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pxAssert( !(info & PROCESS_EE_XMM) );
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#if NO_MMX
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_addNeededGPRtoXMMreg(_Rt_);
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_addNeededGPRtoXMMreg(_Rd_);
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*rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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*rdreg = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE);
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*rstemp = _allocTempXMMreg(XMMT_INT, -1);
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xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
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xAND(eax, 0x3f);
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xMOVDZX(xRegisterSSE(*rstemp), eax);
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*rsreg = *rstemp;
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if( *rtreg != *rdreg ) xMOVDQA(xRegisterSSE(*rdreg), xRegisterSSE(*rtreg));
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#else
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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*rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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@ -326,27 +414,41 @@ int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int
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*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
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xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
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xAND(eax, shift64?0x3f:0x1f);
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xAND(eax, 0x3f);
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xMOVDZX(xRegisterMMX(*rstemp), eax);
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*rsreg = *rstemp;
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if( *rtreg != *rdreg ) xMOVQ(xRegisterMMX(*rdreg), xRegisterMMX(*rtreg));
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return 1;
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#endif
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}
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void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp, int shift64)
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void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp)
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{
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#if NO_MMX
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_addNeededGPRtoXMMreg(_Rd_);
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*rdreg = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE);
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*rstemp = _allocTempXMMreg(XMMT_INT, -1);
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xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
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xAND(eax, 0x3f);
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xMOVDZX(xRegisterSSE(*rstemp), eax);
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*rsreg = *rstemp;
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_flushConstReg(_Rt_);
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#else
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_addNeededMMXreg(MMX_GPR+_Rd_);
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*rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
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xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
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xAND(eax, shift64?0x3f:0x1f);
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xAND(eax, 0x3f);
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xMOVDZX(xRegisterMMX(*rstemp), eax);
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*rsreg = *rstemp;
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_flushConstReg(_Rt_);
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#endif
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}
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//// SLLV
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@ -479,20 +581,45 @@ void recDSLLV_consts(int info)
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void recDSLLV_constt(int info)
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{
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int rsreg, rdreg, rstemp = -1;
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recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
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recSetConstShiftV(info, &rsreg, &rdreg, &rstemp);
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#if NO_MMX
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xMOVDQA(xRegisterSSE(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
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xPSLL.Q(xRegisterSSE(rdreg), xRegisterSSE(rsreg));
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if( rstemp != -1 ) _freeXMMreg(rstemp);
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// flush lower 64 bits (as upper is wrong)
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// The others possibility could be a read back of the upper 64 bits
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// (better use of register but code will likely be flushed after anyway)
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xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_deleteGPRtoXMMreg(_Rd_, 3);
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#else
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xMOVQ(xRegisterMMX(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
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xPSLL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
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if( rstemp != -1 ) _freeMMXreg(rstemp);
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#endif
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}
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void recDSLLV_(int info)
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{
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int rsreg, rtreg, rdreg, rstemp = -1;
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recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1);
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recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp);
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#if NO_MMX
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xPSLL.Q(xRegisterSSE(rdreg), xRegisterSSE(rsreg));
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if( rstemp != -1 ) _freeXMMreg(rstemp);
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// flush lower 64 bits (as upper is wrong)
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// The others possibility could be a read back of the upper 64 bits
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// (better use of register but code will likely be flushed after anyway)
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xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_deleteGPRtoXMMreg(_Rd_, 3);
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#else
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xPSLL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
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if( rstemp != -1 ) _freeMMXreg(rstemp);
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#endif
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}
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EERECOMPILE_CODE0(DSLLV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
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@ -513,20 +640,45 @@ void recDSRLV_consts(int info)
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void recDSRLV_constt(int info)
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{
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int rsreg, rdreg, rstemp = -1;
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recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
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recSetConstShiftV(info, &rsreg, &rdreg, &rstemp);
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#if NO_MMX
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xMOVDQA(xRegisterSSE(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
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xPSRL.Q(xRegisterSSE(rdreg), xRegisterSSE(rsreg));
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if( rstemp != -1 ) _freeXMMreg(rstemp);
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// flush lower 64 bits (as upper is wrong)
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// The others possibility could be a read back of the upper 64 bits
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// (better use of register but code will likely be flushed after anyway)
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xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_deleteGPRtoXMMreg(_Rd_, 3);
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#else
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xMOVQ(xRegisterMMX(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
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xPSRL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
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if( rstemp != -1 ) _freeMMXreg(rstemp);
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#endif
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}
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void recDSRLV_(int info)
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{
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int rsreg, rtreg, rdreg, rstemp = -1;
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recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1);
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recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp);
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#if NO_MMX
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xPSRL.Q(xRegisterSSE(rdreg), xRegisterSSE(rsreg));
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if( rstemp != -1 ) _freeXMMreg(rstemp);
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// flush lower 64 bits (as upper is wrong)
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// The others possibility could be a read back of the upper 64 bits
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// (better use of register but code will likely be flushed after anyway)
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xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_deleteGPRtoXMMreg(_Rd_, 3);
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#else
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xPSRL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
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if( rstemp != -1 ) _freeMMXreg(rstemp);
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#endif
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}
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EERECOMPILE_CODE0(DSRLV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
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@ -547,10 +699,45 @@ void recDSRAV_consts(int info)
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void recDSRAV_constt(int info)
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{
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int rsreg, rdreg, rstemp = -1, t0reg, t1reg;
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#if NO_MMX
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t0reg = _allocTempXMMreg(XMMT_INT, -1);
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t1reg = _allocTempXMMreg(XMMT_INT, -1);
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recSetConstShiftV(info, &rsreg, &rdreg, &rstemp);
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xMOVDQA(xRegisterSSE(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
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xPXOR(xRegisterSSE(t0reg), xRegisterSSE(t0reg));
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// calc high bit
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xMOVDQA(xRegisterSSE(t1reg), xRegisterSSE(rdreg));
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xPCMP.GTD(xRegisterSSE(t0reg), xRegisterSSE(rdreg));
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xPSHUF.D(xRegisterSSE(t0reg), xRegisterSSE(t0reg), 0x55);
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// shift highest bit, 64 - eax
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xMOV(eax, 64);
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xMOVDZX(xRegisterSSE(t1reg), eax);
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xPSUB.D(xRegisterSSE(t1reg), xRegisterSSE(rsreg));
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// right logical shift
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xPSRL.Q(xRegisterSSE(rdreg), xRegisterSSE(rsreg));
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xPSLL.Q(xRegisterSSE(t0reg), xRegisterSSE(t1reg)); // highest bits
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xPOR(xRegisterSSE(rdreg), xRegisterSSE(t0reg));
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// flush lower 64 bits (as upper is wrong)
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// The others possibility could be a read back of the upper 64 bits
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// (better use of register but code will likely be flushed after anyway)
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xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
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_deleteGPRtoXMMreg(_Rd_, 3);
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_freeXMMreg(t0reg);
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_freeXMMreg(t1reg);
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if( rstemp != -1 ) _freeXMMreg(rstemp);
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#else
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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t1reg = _allocMMXreg(-1, MMX_TEMP, 0);
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recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
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recSetConstShiftV(info, &rsreg, &rdreg, &rstemp);
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xMOVQ(xRegisterMMX(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
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xPXOR(xRegisterMMX(t0reg), xRegisterMMX(t0reg));
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@ -574,14 +761,49 @@ void recDSRAV_constt(int info)
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_freeMMXreg(t0reg);
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_freeMMXreg(t1reg);
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if( rstemp != -1 ) _freeMMXreg(rstemp);
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#endif
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}
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void recDSRAV_(int info)
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{
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int rsreg, rtreg, rdreg, rstemp = -1, t0reg, t1reg;
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#if NO_MMX
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t0reg = _allocTempXMMreg(XMMT_INT, -1);
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t1reg = _allocTempXMMreg(XMMT_INT, -1);
|
||||
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp);
|
||||
|
||||
xPXOR(xRegisterSSE(t0reg), xRegisterSSE(t0reg));
|
||||
|
||||
// calc high bit
|
||||
xMOVDQA(xRegisterSSE(t1reg), xRegisterSSE(rdreg));
|
||||
xPCMP.GTD(xRegisterSSE(t0reg), xRegisterSSE(rdreg));
|
||||
xPSHUF.D(xRegisterSSE(t0reg), xRegisterSSE(t0reg), 0x55);
|
||||
|
||||
// shift highest bit, 64 - eax
|
||||
xMOV(eax, 64);
|
||||
xMOVDZX(xRegisterSSE(t1reg), eax);
|
||||
xPSUB.D(xRegisterSSE(t1reg), xRegisterSSE(rsreg));
|
||||
|
||||
// right logical shift
|
||||
xPSRL.Q(xRegisterSSE(rdreg), xRegisterSSE(rsreg));
|
||||
xPSLL.Q(xRegisterSSE(t0reg), xRegisterSSE(t1reg)); // highest bits
|
||||
|
||||
xPOR(xRegisterSSE(rdreg), xRegisterSSE(t0reg));
|
||||
|
||||
// flush lower 64 bits (as upper is wrong)
|
||||
// The others possibility could be a read back of the upper 64 bits
|
||||
// (better use of register but code will likely be flushed after anyway)
|
||||
xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
|
||||
_deleteGPRtoXMMreg(_Rt_, 3);
|
||||
_deleteGPRtoXMMreg(_Rd_, 3);
|
||||
|
||||
_freeXMMreg(t0reg);
|
||||
_freeXMMreg(t1reg);
|
||||
if( rstemp != -1 ) _freeXMMreg(rstemp);
|
||||
#else
|
||||
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
||||
t1reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
||||
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1);
|
||||
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp);
|
||||
|
||||
xPXOR(xRegisterMMX(t0reg), xRegisterMMX(t0reg));
|
||||
|
||||
|
|
@ -604,6 +826,7 @@ void recDSRAV_(int info)
|
|||
_freeMMXreg(t0reg);
|
||||
_freeMMXreg(t1reg);
|
||||
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
||||
#endif
|
||||
}
|
||||
|
||||
EERECOMPILE_CODE0(DSRAV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
|
||||
|
|
|
|||
Loading…
Reference in New Issue