mirror of https://github.com/PCSX2/pcsx2.git
EE: replace EE/FPU mov opcode when FPU_RECOMPILE isn't enabled
It will be easier for testing if we change the format of the FPU register
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@ -108,6 +108,15 @@ static const __aligned16 u32 s_pos[4] = { 0x7fffffff, 0xffffffff, 0xffffffff, 0x
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// *FPU Opcodes!*
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//------------------------------------------------------------------
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// Those opcode are marked as special ! But I don't understand why we can't run them in the interpreter
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#ifndef FPU_RECOMPILE
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REC_FPUFUNC(CFC1);
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REC_FPUFUNC(CTC1);
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REC_FPUFUNC(MFC1);
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REC_FPUFUNC(MTC1);
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#else
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//------------------------------------------------------------------
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// CFC1 / CTC1
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@ -260,6 +269,7 @@ void recMTC1()
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}
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}
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}
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#endif
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//------------------------------------------------------------------
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@ -500,6 +500,9 @@ void recSDR()
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void recLWC1()
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{
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#ifndef FPU_RECOMPILE
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recCall(::R5900::Interpreter::OpcodeImpl::LWC1);
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#else
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_deleteFPtoXMMreg(_Rt_, 2);
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if (GPR_IS_CONST1(_Rs_))
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@ -521,12 +524,16 @@ void recLWC1()
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xMOV(ptr32[&fpuRegs.fpr[_Rt_].UL], eax);
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EE::Profiler.EmitOp(eeOpcode::LWC1);
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#endif
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}
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////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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void recSWC1()
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{
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#ifndef FPU_RECOMPILE
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recCall(::R5900::Interpreter::OpcodeImpl::SWC1);
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#else
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_deleteFPtoXMMreg(_Rt_, 1);
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xMOV(edx, ptr32[&fpuRegs.fpr[_Rt_].UL] );
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@ -548,6 +555,7 @@ void recSWC1()
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}
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EE::Profiler.EmitOp(eeOpcode::SWC1);
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#endif
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}
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////////////////////////////////////////////////////
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