mirror of https://github.com/PCSX2/pcsx2.git
EERec: Don't load in skip case of SD[LR]
This commit is contained in:
TellowKrinkle
refractionpcsx2
parent
e9518f78c7
commit
23578e963f
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@ -458,6 +458,43 @@ void recSWR()
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////////////////////////////////////////////////////
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/// Masks rt with (0xffffffffffffffff maskshift maskamt), merges with (value shift amt), leaves result in value
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static void ldlrhelper_const(int maskamt, const xImplSimd_Shift& maskshift, int amt, const xImplSimd_Shift& shift, const xRegisterSSE& value, const xRegisterSSE& rt)
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{
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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xRegisterSSE t0(t0reg);
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xPCMP.EQD(t0, t0);
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maskshift.Q(t0, maskamt);
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xPAND(t0, rt);
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shift.Q(value, amt);
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xPOR(value, t0);
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_freeXMMreg(t0reg);
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}
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/// Masks rt with (0xffffffffffffffff maskshift maskamt), merges with (value shift amt), leaves result in value
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static void ldlrhelper(const xRegister32& maskamt, const xImplSimd_Shift& maskshift, const xRegister32& amt, const xImplSimd_Shift& shift, const xRegisterSSE& value, const xRegisterSSE& rt)
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{
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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int t1reg = _allocTempXMMreg(XMMT_INT, -1);
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xRegisterSSE t0(t0reg);
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xRegisterSSE t1(t1reg);
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xMOVDZX(t1, maskamt);
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xPCMP.EQD(t0, t0);
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maskshift.Q(t0, t1);
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xPAND(t0, rt);
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xMOVDZX(t1, amt);
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shift.Q(value, t1);
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xPOR(value, t0);
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_freeXMMreg(t1reg);
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_freeXMMreg(t0reg);
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}
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void recLDL()
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{
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if (!_Rt_)
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@ -480,6 +517,7 @@ void recLDL()
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if (_Imm_ != 0)
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xADD(arg1regd, _Imm_);
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xMOV(calleeSavedReg1d, arg1regd);
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xAND(arg1regd, ~0x07);
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iFlushCall(FLUSH_FULLVTLB);
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@ -488,46 +526,34 @@ void recLDL()
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}
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int rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ | MODE_WRITE);
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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int t1reg = _allocTempXMMreg(XMMT_INT, -1);
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if (GPR_IS_CONST1(_Rs_))
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{
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u32 shiftval = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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shiftval &= 0x7;
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xMOV(eax, shiftval + 1);
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u32 shift = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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shift = ((shift & 0x7) + 1) * 8;
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if (shift != 64)
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{
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ldlrhelper_const(shift, xPSRL, 64 - shift, xPSLL, xRegisterSSE(t2reg), xRegisterSSE(rtreg));
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}
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}
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else
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{
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_eeMoveGPRtoR(eax, _Rs_);
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if (_Imm_ != 0)
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xADD(eax, _Imm_);
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xAND(eax, 0x7);
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xADD(eax, 1);
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xAND(calleeSavedReg1d, 0x7);
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xCMP(calleeSavedReg1d, 7);
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xForwardJE8 skip;
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// Calculate the shift from top bit to lowest
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xADD(calleeSavedReg1d, 1);
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xMOV(edx, 64);
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xSHL(calleeSavedReg1d, 3);
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xSUB(edx, calleeSavedReg1d);
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ldlrhelper(calleeSavedReg1d, xPSRL, edx, xPSLL, xRegisterSSE(t2reg), xRegisterSSE(rtreg));
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skip.SetTarget();
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}
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xCMP(eax, 8);
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xForwardJE8 skip;
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//Calculate the shift from top bit to lowest
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xMOV(edx, 64);
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xSHL(eax, 3);
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xSUB(edx, eax);
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xMOVDZX(xRegisterSSE(t1reg), eax);
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xPCMP.EQD(xRegisterSSE(t0reg), xRegisterSSE(t0reg));
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xPSRL.Q(xRegisterSSE(t0reg), xRegisterSSE(t1reg));
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xPAND(xRegisterSSE(t0reg), xRegisterSSE(rtreg));
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xMOVDZX(xRegisterSSE(t1reg), edx);
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xPSLL.Q(xRegisterSSE(t2reg), xRegisterSSE(t1reg));
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xPOR(xRegisterSSE(t2reg), xRegisterSSE(t0reg));
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skip.SetTarget();
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xMOVSD(xRegisterSSE(rtreg), xRegisterSSE(t2reg));
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_freeXMMreg(t0reg);
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_freeXMMreg(t1reg);
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_freeXMMreg(t2reg);
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_clearNeededXMMregs();
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#else
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iFlushCall(FLUSH_INTERPRETER);
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@ -562,6 +588,7 @@ void recLDR()
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if (_Imm_ != 0)
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xADD(arg1regd, _Imm_);
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xMOV(calleeSavedReg1d, arg1regd);
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xAND(arg1regd, ~0x07);
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iFlushCall(FLUSH_FULLVTLB);
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@ -570,45 +597,33 @@ void recLDR()
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}
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int rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ | MODE_WRITE);
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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int t1reg = _allocTempXMMreg(XMMT_INT, -1);
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if (GPR_IS_CONST1(_Rs_))
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{
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u32 shiftval = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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shiftval &= 0x7;
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xMOV(eax, shiftval);
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u32 shift = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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shift = (shift & 0x7) * 8;
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if (shift != 0)
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{
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ldlrhelper_const(64 - shift, xPSLL, shift, xPSRL, xRegisterSSE(t2reg), xRegisterSSE(rtreg));
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}
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}
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else
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{
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_eeMoveGPRtoR(eax, _Rs_);
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if (_Imm_ != 0)
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xADD(eax, _Imm_);
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xAND(eax, 0x7);
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xAND(calleeSavedReg1d, 0x7);
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xForwardJE8 skip;
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// Calculate the shift from top bit to lowest
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xMOV(edx, 64);
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xSHL(calleeSavedReg1d, 3);
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xSUB(edx, calleeSavedReg1d);
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ldlrhelper(edx, xPSLL, calleeSavedReg1d, xPSRL, xRegisterSSE(t2reg), xRegisterSSE(rtreg));
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skip.SetTarget();
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}
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xCMP(eax, 0);
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xForwardJE32 skip;
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//Calculate the shift from top bit to lowest
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xMOV(edx, 64);
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xSHL(eax, 3);
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xSUB(edx, eax);
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xMOVDZX(xRegisterSSE(t1reg), edx); //64-shift*8
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xPCMP.EQD(xRegisterSSE(t0reg), xRegisterSSE(t0reg));
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xPSLL.Q(xRegisterSSE(t0reg), xRegisterSSE(t1reg));
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xPAND(xRegisterSSE(t0reg), xRegisterSSE(rtreg));
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xMOVDZX(xRegisterSSE(t1reg), eax); //shift*8
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xPSRL.Q(xRegisterSSE(t2reg), xRegisterSSE(t1reg));
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xPOR(xRegisterSSE(t2reg), xRegisterSSE(t0reg));
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skip.SetTarget();
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xMOVSD(xRegisterSSE(rtreg), xRegisterSSE(t2reg));
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_freeXMMreg(t0reg);
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_freeXMMreg(t1reg);
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_freeXMMreg(t2reg);
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_clearNeededXMMregs();
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#else
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iFlushCall(FLUSH_INTERPRETER);
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@ -622,16 +637,73 @@ void recLDR()
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////////////////////////////////////////////////////
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/// Masks value with (0xffffffffffffffff maskshift maskamt), merges with (rt shift amt), saves to dummyValue
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static void sdlrhelper_const(int maskamt, const xImplSimd_Shift& maskshift, int amt, const xImplSimd_Shift& shift, const xRegisterSSE& value, const xRegisterSSE& rt)
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{
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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xRegisterSSE t0(t0reg);
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xPCMP.EQD(t0, t0);
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maskshift.Q(t0, maskamt);
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xPAND(t0, value);
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shift.Q(rt, amt);
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xPOR(rt, t0);
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xLEA(arg2reg, ptr[&dummyValue[0]]);
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xMOVQ(ptr64[arg2reg], rt);
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_freeXMMreg(t0reg);
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}
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/// Masks value with (0xffffffffffffffff maskshift maskamt), merges with (rt shift amt), saves to dummyValue
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static void sdlrhelper(const xRegister32& maskamt, const xImplSimd_Shift& maskshift, const xRegister32& amt, const xImplSimd_Shift& shift, const xRegisterSSE& value, const xRegisterSSE& rt)
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{
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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int t1reg = _allocTempXMMreg(XMMT_INT, -1);
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xRegisterSSE t0(t0reg);
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xRegisterSSE t1(t1reg);
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// Generate mask 128-(shiftx8)
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xMOVDZX(t1, maskamt);
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xPCMP.EQD(t0, t0);
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maskshift.Q(t0, t1);
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xPAND(t0, value);
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// Shift over reg value
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xMOVDZX(t1, amt);
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shift.Q(rt, t1);
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xPOR(rt, t0);
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xLEA(arg2reg, ptr[&dummyValue[0]]);
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xMOVQ(ptr64[arg2reg], rt);
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_freeXMMreg(t1reg);
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_freeXMMreg(t0reg);
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}
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void recSDL()
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{
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#ifdef LOADSTORE_RECOMPILE
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int t2reg;
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_flushEEreg(_Rt_); // flush register to mem
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if (GPR_IS_CONST1(_Rs_))
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{
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u32 srcadr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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srcadr &= ~0x07;
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t2reg = vtlb_DynGenRead64_Const(64, srcadr, -1);
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u32 adr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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u32 aligned = adr & ~0x07;
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u32 shift = ((adr & 0x7) + 1) * 8;
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if (shift == 64)
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{
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xLEA(arg2reg, ptr[&cpuRegs.GPR.r[_Rt_].UL[0]]);
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}
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else
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{
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int t2reg = vtlb_DynGenRead64_Const(64, aligned, -1);
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int rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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sdlrhelper_const(shift, xPSLL, 64 - shift, xPSRL, xRegisterSSE(t2reg), xRegisterSSE(rtreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_freeXMMreg(t2reg);
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}
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vtlb_DynGenWrite_Const(64, aligned);
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}
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else
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{
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@ -640,74 +712,34 @@ void recSDL()
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if (_Imm_ != 0)
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xADD(arg1regd, _Imm_);
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xAND(arg1regd, ~0x07);
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iFlushCall(FLUSH_FULLVTLB);
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xMOV(calleeSavedReg1d, arg1regd);
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xAND(arg1regd, ~0x07);
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xAND(calleeSavedReg1d, 0x7);
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xCMP(calleeSavedReg1d, 7);
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xForwardJE32 skip;
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xADD(calleeSavedReg1d, 1);
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int t2reg = vtlb_DynGenRead64(64, -1);
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int rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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t2reg = vtlb_DynGenRead64(64, -1);
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}
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_flushEEreg(_Rt_); // flush register to mem
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//Calculate the shift from top bit to lowest
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xMOV(edx, 64);
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xSHL(calleeSavedReg1d, 3);
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xSUB(edx, calleeSavedReg1d);
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int rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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int t1reg = _allocTempXMMreg(XMMT_INT, -1);
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sdlrhelper(calleeSavedReg1d, xPSLL, edx, xPSRL, xRegisterSSE(t2reg), xRegisterSSE(rtreg));
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if (GPR_IS_CONST1(_Rs_))
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{
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u32 shiftval = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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shiftval &= 0x7;
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xMOV(eax, shiftval + 1);
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}
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else
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{
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_eeMoveGPRtoR(eax, _Rs_);
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if (_Imm_ != 0)
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xADD(eax, _Imm_);
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xAND(eax, 0x7);
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xADD(eax, 1);
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}
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_deleteGPRtoXMMreg(_Rt_, 3);
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_freeXMMreg(t2reg);
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xCMP(eax, 8);
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xForwardJE8 skip;
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//Calculate the shift from top bit to lowest
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xMOV(edx, 64);
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xSHL(eax, 3);
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xSUB(edx, eax);
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// Generate mask 128-(shiftx8) xPSRA.W does bit for bit
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xMOVDZX(xRegisterSSE(t1reg), eax);
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xPCMP.EQD(xRegisterSSE(t0reg), xRegisterSSE(t0reg));
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xPSLL.Q(xRegisterSSE(t0reg), xRegisterSSE(t1reg));
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xPAND(xRegisterSSE(t0reg), xRegisterSSE(t2reg));
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// Shift over reg value (shift, PSLL.Q multiplies by 8)
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xMOVDZX(xRegisterSSE(t1reg), edx);
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xPSRL.Q(xRegisterSSE(rtreg), xRegisterSSE(t1reg));
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xPOR(xRegisterSSE(rtreg), xRegisterSSE(t0reg));
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skip.SetTarget();
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xMOVQ(ptr64[&dummyValue[0]], xRegisterSSE(rtreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_freeXMMreg(t0reg);
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_freeXMMreg(t1reg);
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_freeXMMreg(t2reg);
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xLEA(arg2reg, ptr128[&dummyValue[0]]);
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if (GPR_IS_CONST1(_Rs_))
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{
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u32 dstadr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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dstadr &= ~0x07;
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vtlb_DynGenWrite_Const(64, dstadr);
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}
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else
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{
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_eeMoveGPRtoR(arg1regd, _Rs_);
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if (_Imm_ != 0)
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xADD(arg1regd, _Imm_);
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xAND(arg1regd, ~0x7);
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_eeMoveGPRtoR(arg1regd, _Rs_);
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if (_Imm_ != 0)
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xADD(arg1regd, _Imm_);
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xAND(arg1regd, ~0x7);
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xForwardJump8 end;
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skip.SetTarget();
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xLEA(arg2reg, ptr[&cpuRegs.GPR.r[_Rt_].UL[0]]);
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end.SetTarget();
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iFlushCall(FLUSH_FULLVTLB);
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@ -726,13 +758,26 @@ void recSDL()
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void recSDR()
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{
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#ifdef LOADSTORE_RECOMPILE
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int t2reg;
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_flushEEreg(_Rt_); // flush register to mem
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if (GPR_IS_CONST1(_Rs_))
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{
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u32 srcadr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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srcadr &= ~0x07;
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u32 adr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
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u32 aligned = adr & ~0x07;
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u32 shift = (adr & 0x7) * 8;
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if (shift == 0)
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{
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xLEA(arg2reg, ptr[&cpuRegs.GPR.r[_Rt_].UL[0]]);
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}
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else
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{
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int t2reg = vtlb_DynGenRead64_Const(64, aligned, -1);
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int rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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sdlrhelper_const(64 - shift, xPSRL, shift, xPSLL, xRegisterSSE(t2reg), xRegisterSSE(rtreg));
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_deleteGPRtoXMMreg(_Rt_, 3);
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_freeXMMreg(t2reg);
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}
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t2reg = vtlb_DynGenRead64_Const(64, srcadr, -1);
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vtlb_DynGenWrite_Const(64, aligned);
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}
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else
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{
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@ -741,73 +786,31 @@ void recSDR()
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if (_Imm_ != 0)
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xADD(arg1regd, _Imm_);
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xAND(arg1regd, ~0x07);
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iFlushCall(FLUSH_FULLVTLB);
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xMOV(calleeSavedReg1d, arg1regd);
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xAND(arg1regd, ~0x07);
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xAND(calleeSavedReg1d, 0x7);
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xForwardJE32 skip;
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int t2reg = vtlb_DynGenRead64(64, -1);
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int rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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t2reg = vtlb_DynGenRead64(64, -1);
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}
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_flushEEreg(_Rt_); // flush register to mem
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xMOV(edx, 64);
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xSHL(calleeSavedReg1d, 3);
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xSUB(edx, calleeSavedReg1d);
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int rtreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ);
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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int t1reg = _allocTempXMMreg(XMMT_INT, -1);
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||||
sdlrhelper(edx, xPSRL, calleeSavedReg1d, xPSLL, xRegisterSSE(t2reg), xRegisterSSE(rtreg));
|
||||
|
||||
if (GPR_IS_CONST1(_Rs_))
|
||||
{
|
||||
u32 shiftval = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
|
||||
shiftval &= 0x7;
|
||||
xMOV(eax, shiftval);
|
||||
}
|
||||
else
|
||||
{
|
||||
_eeMoveGPRtoR(eax, _Rs_);
|
||||
if (_Imm_ != 0)
|
||||
xADD(eax, _Imm_);
|
||||
xAND(eax, 0x7);
|
||||
}
|
||||
_deleteGPRtoXMMreg(_Rt_, 3);
|
||||
_freeXMMreg(t2reg);
|
||||
|
||||
xCMP(eax, 0);
|
||||
xForwardJE8 skip;
|
||||
//Calculate the shift from top bit to lowest
|
||||
xMOV(edx, 64);
|
||||
xSHL(eax, 3);
|
||||
xSUB(edx, eax);
|
||||
// Generate mask 128-(shiftx8) xPSRA.W does bit for bit
|
||||
xMOVDZX(xRegisterSSE(t1reg), edx);
|
||||
xPCMP.EQD(xRegisterSSE(t0reg), xRegisterSSE(t0reg));
|
||||
xPSRL.Q(xRegisterSSE(t0reg), xRegisterSSE(t1reg));
|
||||
xPAND(xRegisterSSE(t0reg), xRegisterSSE(t2reg));
|
||||
|
||||
// Shift over reg value (shift, PSLL.Q multiplies by 8)
|
||||
xMOVDZX(xRegisterSSE(t1reg), eax);
|
||||
xPSLL.Q(xRegisterSSE(rtreg), xRegisterSSE(t1reg));
|
||||
xPOR(xRegisterSSE(rtreg), xRegisterSSE(t0reg));
|
||||
skip.SetTarget();
|
||||
|
||||
xMOVQ(ptr64[&dummyValue[0]], xRegisterSSE(rtreg));
|
||||
|
||||
_deleteGPRtoXMMreg(_Rt_, 3);
|
||||
_freeXMMreg(t0reg);
|
||||
_freeXMMreg(t1reg);
|
||||
_freeXMMreg(t2reg);
|
||||
|
||||
xLEA(arg2reg, ptr128[&dummyValue[0]]);
|
||||
|
||||
if (GPR_IS_CONST1(_Rs_))
|
||||
{
|
||||
u32 dstadr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
|
||||
dstadr &= ~0x07;
|
||||
|
||||
vtlb_DynGenWrite_Const(64, dstadr);
|
||||
}
|
||||
else
|
||||
{
|
||||
_eeMoveGPRtoR(arg1regd, _Rs_);
|
||||
if (_Imm_ != 0)
|
||||
xADD(arg1regd, _Imm_);
|
||||
|
||||
xAND(arg1regd, ~0x7);
|
||||
_eeMoveGPRtoR(arg1regd, _Rs_);
|
||||
if (_Imm_ != 0)
|
||||
xADD(arg1regd, _Imm_);
|
||||
xAND(arg1regd, ~0x7);
|
||||
xForwardJump8 end;
|
||||
skip.SetTarget();
|
||||
xLEA(arg2reg, ptr[&cpuRegs.GPR.r[_Rt_].UL[0]]);
|
||||
end.SetTarget();
|
||||
|
||||
iFlushCall(FLUSH_FULLVTLB);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue