Commit Graph

1514 Commits

Author SHA1 Message Date
zilmar de1288bdca Core: remove try/catch around Interpreter cpu 2023-11-30 21:15:14 +10:30
zilmar df56964c96 Android: Remove unneeded log call 2023-11-30 21:13:27 +10:30
zilmar 5671f2b759 Android: Update how Addu cause android studio was not sign extending result 2023-11-30 21:12:53 +10:30
zilmar 01673dac8d Core: Change TriggerAddressException to SetVPN an R of entry hi in one call 2023-11-23 14:20:48 +10:30
zilmar d47b49d4b5 Core: Fix clang issue 2023-11-16 18:24:47 +10:30
zilmar 542afc4514 Core: remove some accidental added debug code 2023-11-16 18:16:35 +10:30
zilmar ee714e2462 Core: On unmap base addresses reset to the correct address 2023-11-16 18:14:15 +10:30
zilmar 8f4f434820 Core: Get Fast tlb to just be 32bit 2023-11-16 17:11:05 +10:30
zilmar dcb6969067 Core: Have entryHI use functions to set/get parts 2023-11-16 09:19:24 +10:30
zilmar a0130ff896 Core: Convert %I64U to %llx 2023-11-16 09:03:32 +10:30
zilmar 296b7cf1cf Android: Force RSP to be interpret 2023-11-09 12:45:36 +10:30
zilmar e6edbc6c82 Fix clang formatting 2023-10-27 10:14:21 +10:30
zilmar 4770d29ec0 Core: Get system events to be internal not global 2023-10-26 19:59:11 +10:30
zilmar 8f062975c3 Core: improve DisplayControlRegHandler::Write32 2023-10-19 19:28:38 +10:30
zilmar d6a2ae80c1 Core: Remove SystemRegisters 2023-10-19 14:56:53 +10:30
zilmar d58168bcb9 Core: R4300iOp access the registers directly, not through CSystemRegisters 2023-10-19 12:52:33 +10:30
zilmar 4d78f56aa2 Core: In R4300iOp have a member variable for system, reg, mmu 2023-10-19 12:31:26 +10:30
zilmar ae0097550f Core: Make R4300iOp opcodes not static 2023-10-19 11:43:32 +10:30
zilmar 7f42f70283 Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static 2023-10-19 10:28:25 +10:30
zilmar d3edbf6dda Core: move CInterpreterCPU into R4300iOp 2023-10-19 09:32:42 +10:30
zilmar d4dbc5a3f4 Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio 2023-10-14 11:53:35 +10:30
zilmar 00c5057b17 Core: Make sure precision is correct for COP1_D_SQRT 2023-10-13 00:16:14 +10:30
zilmar 3a68d3d92a Core: LL/LLD store address 2023-10-12 19:55:29 +10:30
zilmar a6405cfa2d Core: Add masking around DPC_START_REG/DPC_END_REG 2023-10-12 17:50:58 +10:30
zilmar 4e71221147 Core: Fix up FPU mode register location 2023-10-12 14:53:44 +10:30
zilmar befa57924d Core: Fix clang compile issues 2023-10-05 15:01:09 +10:30
zilmar f73c3708a5 Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty 2023-10-05 14:45:17 +10:30
zilmar e74e8f6a23 Core: Have load/store ops be able to use 64bit addresses 2023-10-05 14:28:32 +10:30
zilmar 9f07fe2aac Core: Get tlb addresses to be 64bit 2023-10-05 13:42:31 +10:30
zilmar 4b844495b7 Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
2023-10-05 13:10:45 +10:30
zilmar 35105e814e Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss 2023-10-05 09:54:41 +10:30
zilmar b7311cc611 Core: Change Non memory load/store to not use tlb 2023-10-05 09:32:45 +10:30
zilmar 46e6e54f24 RSP: improve running RSP multithreaded 2023-09-28 14:46:36 +09:30
zilmar ac3e0f83d1 Rsp: Use RSP Register Handler 2023-09-28 11:52:06 +09:30
zilmar bd1ec4ff0f Core: Create a setting for RDRAM Size that plugins can read 2023-09-28 07:29:11 +09:30
zilmar 99417fc5d9 Core: reset run event in CRSP_Plugin after rom close 2023-09-28 07:19:20 +09:30
zilmar f817becf9c Core: Create a handler for RSP registers that is accessible to the core and the RSP 2023-09-28 07:03:01 +09:30
zilmar 03e13455f9 Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot 2023-09-28 06:39:39 +09:30
zilmar 2caa457d02 Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
2023-09-22 11:01:46 +09:30
zilmar 10d2b77d7c Core: Try to fix android build 2023-09-21 20:13:41 +09:30
zilmar aadcca7528 Core: Fix clang issue 2023-09-21 18:40:27 +09:30
zilmar 6307888be4 Core: fix up exception generator functions 2023-09-21 18:07:56 +09:30
zilmar 42a944c660 RSP: Setup option to run in a thread 2023-09-21 14:25:07 +09:30
zilmar f3d6d3fc7c Core: for tlb miss only use special address when address is not defined 2023-09-14 18:39:15 +09:30
zilmar e0c125e837 Core: Fix clang issue 2023-09-14 16:33:20 +09:30
zilmar c02858c7a0 Core: Add LLD opcode 2023-09-14 16:31:37 +09:30
zilmar f559aed2ad Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function 2023-09-14 16:23:26 +09:30
zilmar ae4af8746b Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss 2023-09-14 13:09:11 +09:30
zilmar 8b14b6d7d1 Core: Move InitRegisters to register class 2023-09-14 12:01:16 +09:30
zilmar a5a4873e84 Core: Have CRegisters::DoAddressError to not directly modify program counter 2023-09-14 11:37:21 +09:30
zilmar 2d09178449 Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions 2023-09-14 11:15:42 +09:30
zilmar 5da5dab3c5 Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC 2023-09-14 11:09:28 +09:30
zilmar fcd7257adc Core: Change COP0 Status register to a struct breaking up the bits 2023-09-14 10:23:36 +09:30
zilmar 9ffd87168a Core: DisplayControlRegHandler::Read32 read more of the registers 2023-09-14 09:40:11 +09:30
zilmar ab03916a70 Core: let the stack pointer equal end of rdram 2023-09-07 11:13:54 +09:30
zilmar 7199096748 Core: Merge CheckFPUException into CheckFPUResult64 2023-08-31 18:52:34 +09:30
zilmar 91d1c6e237 Core: Add fpu exceptions to COP1_S_MUL 2023-08-31 11:09:48 +09:30
zilmar 2f7a35613f Core: Add exception to COP1_S_SUB 2023-08-31 10:54:41 +09:30
zilmar c28c6bb4a1 Core: Add fpu exceptions to COP1_S_ADD 2023-08-31 10:08:49 +09:30
zilmar 416c85ecda Core: some code clean up of Load_FPR_ToTop 2023-08-31 09:30:05 +09:30
zilmar 2dcfcf250d Core: Do not force unmapping of fpr registers before CX86RegInfo::BeforeCallDirect(void) 2023-08-31 09:28:23 +09:30
zilmar e49438cdab Core: Add exit reason exception 2023-08-30 12:16:07 +09:30
zilmar 41fa1fd5dd Core: use m_TLB_WriteMap not m_TLB_ReadMap for NonMemory 2023-08-30 11:35:53 +09:30
zilmar d300dc002a Core: remove exception catch around RSP 2023-08-17 15:27:18 +09:30
zilmar 6884c8d2c9 Core: fix up how recompiler handles rounding 2023-08-17 15:24:57 +09:30
zilmar b5db44c12d Core: Get CheckFPUInput64Conv to return true on exception 2023-08-03 17:25:03 +09:30
zilmar 5ff45c43c4 Core: Get R4300iOp::CheckFPUInput64 to return true on exception 2023-08-03 17:11:56 +09:30
zilmar bc1b027c94 Core: get CheckFPUInput32Conv to return true on exception 2023-08-03 16:24:54 +09:30
zilmar 930e463bbc Core: Move TriggerException(EXC_FPE) into R4300iOp::CheckFPUInput32 2023-08-03 15:38:07 +09:30
zilmar 07cf94bde3 RSP: only look at SP_STATUS_HALT when seeing if the RSP should run 2023-07-06 20:49:14 +09:30
zilmar 187bd64915 Core: Update how exceptions are handled with the recompiler 2023-06-08 16:25:05 +09:30
zilmar 1522f17b9c RSP: Convert base code to be compiled as c++ instead of C 2023-06-01 17:11:26 +09:30
zilmar a39ebe7d37 Core: Create InitFpuOperation 2023-05-27 10:01:19 +09:30
zilmar e2eebe566d Core: fix up for clang 2023-05-18 18:05:54 +09:30
zilmar b438fddf2e Core: Add CP2 handling 2023-05-18 18:04:41 +09:30
zilmar 3b8dfce64a Core: Convert DoBreakException to TriggerException 2023-05-18 11:47:00 +09:30
zilmar b2c2a03a2e Core: convert DoFloatingPointException to TriggerException 2023-05-18 11:41:20 +09:30
zilmar 0dfab78c88 Core: Convert DoCopUnusableException to TriggerException 2023-05-18 11:26:36 +09:30
zilmar 456f25eb6b Core: Get DoIntrException to use TriggerException 2023-05-18 11:19:26 +09:30
zilmar 252f629e14 Core: Convert DoIllegalInstructionException to TriggerException 2023-05-18 11:13:22 +09:30
zilmar 59a1277bed Core: Convert GenerateOverflowException to TriggerException 2023-05-18 11:05:27 +09:30
zilmar 69fd74ba56 Core: Convert DoSysCallException to TriggerException 2023-05-18 10:56:06 +09:30
zilmar 17df17805d Core: convert DoTrapException to TriggerException 2023-05-18 10:49:58 +09:30
zilmar 74912ca8c2 Core: handle jump to unaligned addresses 2023-05-18 10:33:57 +09:30
zilmar 6e58edb076 Core: Merge CheckFPUException into CheckFPUResult32 2023-05-15 23:16:54 +09:30
zilmar 62b29622ca Core: remove usage of fpclassify in CheckFPUInput32 and CheckFPUResult32 2023-05-15 22:57:13 +09:30
zilmar 0ddeb6b981 Core: remove exception out of R4300iOp::CheckFPUInput32 2023-05-15 20:56:56 +09:30
zilmar fdc637516f Core: remove Double_RoundToInteger64 2023-05-09 13:05:58 +09:30
zilmar 5a23f48629 Core: remove Double_RoundToInteger32 2023-05-09 12:57:08 +09:30
zilmar e5b1a9469a Core: remove Float_RoundToInteger64 2023-05-09 12:50:23 +09:30
zilmar 2c19c2c362 Core: Handle CPO1 unimplemented op 2023-05-09 11:28:59 +09:30
zilmar 85f4f147a1 Core: Remove Float_RoundToInteger32 2023-05-09 09:40:10 +09:30
zilmar 49a385e743 Core: Split CheckFPUException into CheckFPUException and CheckFPUInvalidException 2023-05-09 08:06:15 +09:30
zilmar fa25b6d2af Core: clear FPU StatusReg cause in CX86RecompilerOps::COP1_S_ADD 2023-05-02 11:12:13 +09:30
zilmar 02a48566c0 Core: Remove helper functions from x86 Recompiler Ops 2023-05-02 10:50:49 +09:30
zilmar 5cfb80fcfc Core: Improve R4300iOp::COP1_S_CVT_W 2023-04-24 19:02:00 +09:30
zilmar 71ef28fd55 Core: Add R4300iOp::COP1_W_CVT_W 2023-04-24 18:55:06 +09:30
zilmar ab8b004b71 Core: Add a setting for fpu reg caching 2023-04-17 18:47:33 +09:30
zilmar cba01b2063 Core: Improve R4300iOp::COP1_L_CVT_D 2023-04-17 18:08:51 +09:30
zilmar d9e69fee65 Core: Improve R4300iOp::COP1_D_CMP 2023-04-17 18:07:58 +09:30
zilmar 0cc6d21ad1 Core: Improve R4300iOp::COP1_S_CMP 2023-04-17 18:06:42 +09:30
zilmar 9297b1c4b8 Core: Improve COP1_S_CVT_D, COP1_W_CVT_D, COP1_D_CVT_S, COP1_W_CVT_S, COP1_L_CVT_S, 2023-04-11 16:20:24 +09:30
zilmar 9a04293a67 Update arm/arm64 to use asmjit 2023-04-05 10:16:21 +09:30
zilmar 2c40d47a34 Start to look at x64 recompiler 2023-04-04 17:44:42 +09:30
zilmar fe35d950f3 x64: Change MemoryStackPos to be a pointer 2023-04-03 09:08:43 +09:30
zilmar 422a42cae3 Core: More work improve the accuracy of cop1 2023-03-28 13:12:59 +10:30
zilmar ce69324dbe Core: Update R4300iOp::COP1_S_MUL to handle exceptions 2023-03-21 10:49:49 +10:30
zilmar cbf67cede4 Core: Update sub.d to handle exceptions 2023-03-20 17:17:31 +10:30
zilmar 96787690c7 Core: Fix CoprocessorUnitNumber on exception 2023-03-20 12:09:06 +10:30
zilmar 7f7aee7232 Core: remove FAKE_CAUSE_REGISTER 2023-03-14 12:14:10 +10:30
zilmar 9093b42d47 Core: improve the accuracy of COP1_S_SUB 2023-03-06 20:58:47 +10:30
zilmar 306f21b5fa Core: Improve accuracy of add.d 2023-03-06 18:28:32 +10:30
zilmar ea70218d1c Clean up warnings 2023-02-28 10:09:08 +10:30
zilmar 1864adcb35 Core: improve the accuracy of COP1_S_ADD 2023-02-21 14:54:22 +10:30
zilmar 3acd56ae61 Core Fix up clang formatting 2023-02-14 08:05:40 +10:30
zilmar 2db5c81af5 Core: Change Project64.rdb so it use 1's and 0's instead of "Yes" or "No" 2023-02-13 21:05:57 +10:30
zilmar e14e10f4b0 Core: Fix handling of R4300iOp::COP1_S_CMP and R4300iOp::COP1_D_CMP 2023-02-13 16:22:50 +10:30
zilmar baa5dbe257 Core: Add some error message when failing to load rom 2023-02-13 12:04:31 +10:30
zilmar a8a553b316 Core: fix code to make clang happy 2023-01-31 07:54:47 +10:30
zilmar 83a7d9e3f2 Core: Start to improve the accuracy of R4300iOp::COP1_S_ADD 2023-01-30 20:36:58 +10:30
zilmar 7affd514c0 Core: Convert TEST_COP1_USABLE_EXCEPTION from a macro to a function 2023-01-30 11:40:03 +10:30
zilmar f802b18cdc Core: Change to using fenv.h instead of including the code directly 2023-01-30 10:07:51 +10:30
zilmar fb6bda321c Core: SW_Register needs to protect the register 2023-01-23 15:30:39 +10:30
zilmar 0e52bfb185 Core: Fix the allocation of rdram size if set in the rdb 2023-01-23 08:30:13 +10:30
zilmar 210ebd42de Core: have an option for rdram to be different between known and unknown roms 2023-01-16 20:53:48 +10:30
zilmar dbd360f676 Core: Handle exception of mov word ptr ds:[E01F4F52h],ax 2023-01-09 17:53:16 +10:30
zilmar 531a7df959 Core: Improve StoreInstruc 2023-01-09 14:26:35 +10:30
zilmar ccae22afc5 Core: Revert SPECIAL_SRA and SPECIAL_SRAV to old version when running as 32bit 2023-01-09 13:47:41 +10:30
zilmar b6629ac1d3 Android: Fix build warning with CX86Ops::CallThis 2023-01-03 14:49:35 +10:30
zilmar e0373025ef Core: Have user rom settings in Project64.rdb.user 2023-01-03 13:08:00 +10:30
zilmar 80aecdc5e3 Core: Improve R4300iOp::COP1_CT 2023-01-02 19:49:19 +10:30
zilmar 3c73c06b01 Update Project files to remove some headers that no longer exist 2023-01-02 17:56:12 +10:30
zilmar 811aaf9d36 Core: Fix up SPECIAL_SRAV for 64bit copy 2022-12-26 18:34:53 +10:30
zilmar c619b71b26 Core: get sra to handle 64bit shift 2022-12-26 18:13:45 +10:30
zilmar b217428fee Core: fix up masking in CX86RecompilerOps::COP1_CT 2022-12-26 17:35:58 +10:30
zilmar 0cc7ede816 Core: Fix up BGEZALL in recompiler 2022-12-26 17:19:32 +10:30
zilmar 2c6d3429b7 Core: Fix handling of BGEZAL ra in recompiler 2022-12-26 16:14:05 +10:30
zilmar f6e4443dda Core: Revert Unaligned DMA to fix some hacks 2022-12-26 15:15:28 +10:30
zilmar f380d326fe Core: Start to handle jump in delay slot 2022-12-26 12:54:04 +10:30
zilmar 620aabcf9e Core: Add clang script and check on building release 2022-12-19 15:51:02 +10:30
zilmar bd1b1b4dbb Core: Missed file for code clean up 2022-12-19 15:36:08 +10:30
zilmar c0341bb759 Core: Code clean up for clang 2022-12-19 15:35:17 +10:30
zilmar ae62981aef Core: Remove unaligned dma 2022-12-19 10:15:31 +10:30
zilmar cbacddb65e Core: Make 32bit CPU recompiler only setting 2022-12-19 09:07:26 +10:30
zilmar 6c154f6547 Core: Add Cop2/Cop3 handling exception 2022-12-12 21:29:16 +10:30
zilmar c8bb04b6b0 Core: Mask COP1_CT reg 31 2022-12-12 19:04:03 +10:30
zilmar d3afe97d38 Core: Initialize FPR_Ctrl[Revision] to 0xA00 2022-12-12 15:27:07 +10:30
zilmar ff56992542 Android: Some more core changes for asmjit 2022-12-07 09:04:55 +10:30
zilmar 6b04b908bf Core: Handle bgezal ra in the recompiler 2022-12-05 14:09:03 +10:30
zilmar d35d2e6abe Core: Move ReadsGPR, WritesGPR, ReadsHI(), ReadsLO(), WritesHI(), WritesLO() out of OpInfo and into R4300iInstruction 2022-12-05 12:23:09 +10:30
zilmar 138868d9ac Core: Get x64 compiling 2022-11-30 17:19:15 +10:30
zilmar ed357e5d97 Core: Get recompiler to call PifRamHandler when in pif address space 2022-11-27 11:07:28 +10:30
zilmar 1e3fff2b41 Core: ignore memory stack pointer when stack pointer is reset 2022-11-25 09:34:54 +10:30
zilmar 1f2fe96d76 Merge branch 'develop' of https://github.com/project64/project64 into develop 2022-11-24 09:10:50 +10:30
zilmar 79d749e33d Core: fix bug in CX86Ops::CallFunc when not logging opcodes 2022-11-24 09:10:15 +10:30
Squall Leonhart 8eecb0c823
Extend mempak Index Table to the intended 256 bytes, so that the default checksum is actually correct, and include the backup of that data. (#2304)
* just a test to see what happens

* duplicate the full 256 bytes.

* Didn't need to duplicate it after all.

The index table wasn't actually 256 bytes as intended, so the checksum was invalid.

Cruis'n'USA 1.0 didn't like this one bit.

* fully duplicate it after all just in case of a rare case

where a game breaks without the backup of the checksum and table.

* this looks properly duplicated now.

perhaps
2022-11-24 07:49:48 +10:30
zilmar e3aa2514c1 Core: Fix bug in CX86RecompilerOps::SPECIAL_DIV 2022-11-23 20:16:38 +10:30
zilmar 8e94b3086b Core: Change recompiler to use asmjit 2022-11-23 14:46:55 +10:30
zilmar 2a6d3cd519 Core: remove #ifdef toremove block in CX86RecompilerOps::SPECIAL_DMULTU() 2022-11-21 08:55:51 +10:30
zilmar 9743f12b1d Core: Remvoe #ifdef LinkBlocks code block 2022-11-21 08:52:19 +10:30
zilmar 989827cb77 Core: Do not set m_MemoryReadMap/m_MemoryWriteMap if tlb mapping is outside rdram 2022-11-14 21:20:28 +10:30
zilmar 97e3f50007 Core: Update mask of registers in CRegisters::Cop0_MT 2022-11-14 20:56:21 +10:30
zilmar cabcd2cc95 Core: Handle masking of random in CSystemTimer::UpdateTimers 2022-11-14 11:19:02 +10:30
zilmar 48da86bea1 Core: if Rom is larger than ISViewerHandler, then use rom handler 2022-11-08 10:54:01 +10:30
zilmar 529812fdca Core: Switch to use asmjit registers in recompiler 2022-11-07 21:03:32 +10:30
zilmar a4c49a3567 Core: rearrange XorVariableToX86reg parameters 2022-11-07 16:30:09 +10:30
zilmar 2fcce6cdd5 Cote: TestVariable rearrange parameters 2022-11-07 16:25:54 +10:30
zilmar fe1f99ae1c Core: rearrange TestConstToX86Reg parameters 2022-11-07 16:22:51 +10:30
zilmar ce939100c5 Core: rearrange OrVariableToX86Reg parameters 2022-11-07 16:18:54 +10:30
zilmar 697397f1dd Core: Rearrange OrConstToX86Reg parameters 2022-11-07 16:03:45 +10:30
zilmar 40259d01ca Core: rearrange OrConstToVariable parameters 2022-11-07 15:55:19 +10:30
zilmar c95aae8e38 Core: rearrange MoveZxVariableToX86regHalf parameters 2022-11-07 15:48:39 +10:30
zilmar 96eed54a1d Core: rearrange MoveZxVariableToX86regByte parameters 2022-11-07 15:44:10 +10:30
zilmar 4570d9eab5 Core: rearrange MoveZxHalfX86regPointerToX86reg variables 2022-11-07 15:40:01 +10:30
zilmar 8a2197707b Core: rearrange MoveZxByteX86regPointerToX86reg parameters 2022-11-07 15:38:36 +10:30
zilmar 59892a266b Core: rearrange MoveX86regToVariable parameters 2022-11-07 15:30:25 +10:30
zilmar 91a192cead Core: rearrange MoveX86regToMemory parameters 2022-11-07 14:40:28 +10:30
zilmar 891d487fdd Core: rearrange MoveX86regPointerToX86regDisp8 parameters 2022-11-07 14:38:34 +10:30
zilmar d74694d16f Core: rearrange MoveX86regPointerToX86reg parameters 2022-11-07 14:36:11 +10:30
zilmar ebca0854d7 Core: rearrange MoveX86regHalfToX86regPointer parameters 2022-11-07 14:29:33 +10:30
zilmar efac334136 Rearrange MoveX86regHalfToVariable parameters 2022-11-07 14:26:06 +10:30
zilmar 1966b842f3 Core: rearrange MoveX86regByteToX86regPointer parameters 2022-11-07 14:24:22 +10:30
zilmar bb51c3d11d Core: rearrange MoveX86regByteToVariable parameters 2022-11-07 14:23:09 +10:30
zilmar d19fc10f0c Core: remove MoveVariableToX86regByte, MoveVariableToX86regHalf, MoveX86regByteToN64Mem 2022-11-07 14:21:26 +10:30
zilmar 8702e6b67c core: Rearrange MoveVariableDispToX86Reg parmeters 2022-11-07 14:18:15 +10:30
zilmar 10dd2c662a Core: rearrange MoveSxVariableToX86regHalf parameters 2022-11-07 14:08:23 +10:30
zilmar eb5d0ce363 Core: rearrange MoveSxVariableToX86regByte parameters 2022-11-07 14:05:08 +10:30
zilmar 1584d25cd9 Core: Rearrange MoveSxHalfX86regPointerToX86reg parameters 2022-11-07 13:41:49 +10:30
zilmar fe7b8afa92 Core: Rearrange MoveSxByteX86regPointerToX86reg parameters 2022-11-07 13:37:29 +10:30
zilmar 288fe4d222 Core: reorder MoveConstToX86regPointer parameters 2022-11-07 11:35:11 +10:30
zilmar b68caed6c4 Core: reorder MoveConstByteToX86regPointer parameters 2022-11-07 11:32:46 +10:30
zilmar eb0aa05a48 Core: remove x86 functions referencing n64mem 2022-11-07 11:30:51 +10:30
zilmar 40456f12db Core: Change order of MoveConstToVariable 2022-11-07 11:26:17 +10:30
zilmar 5c7390324a Core: reorder MoveConstToMemoryDisp parameters 2022-11-07 10:45:28 +10:30
zilmar 8272d18aa6 Reorder MoveConstHalfToX86regPointer parameters 2022-11-07 10:43:27 +10:30
zilmar 0123100233 Core: reorder MoveConstHalfToVariable parameters 2022-11-07 10:37:29 +10:30
zilmar bdb2d040f9 Core: reorder MoveConstByteToVariable parameters 2022-11-07 10:34:25 +10:30
zilmar eb8b36603b Core: remove MoveConstByteToN64Mem, MoveConstHalfToN64Mem, MoveConstToN64Mem, MoveConstToN64MemDisp 2022-11-07 10:27:22 +10:30
zilmar 9dd2df36d4 Core: remove CX86Ops::CompVariableToX86reg 2022-11-07 10:18:55 +10:30
zilmar 09fb90117e Core: reorder CompConstToVariable parameters 2022-11-07 10:11:55 +10:30