Core: LL/LLD store address
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@ -1192,6 +1192,10 @@ void R4300iOp::LL()
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{
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_GPR[m_Opcode.rt].DW = (int32_t)MemoryValue;
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(*_LLBit) = 1;
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uint32_t PhysicalAddr;
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bool MemoryUsed;
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g_TLB->VAddrToPAddr(Address, PhysicalAddr, MemoryUsed);
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_CP0[17] = PhysicalAddr >> 4;
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}
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}
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@ -1234,6 +1238,10 @@ void R4300iOp::LLD()
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if (g_MMU->LD_Memory(Address, _GPR[m_Opcode.rt].UDW))
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{
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(*_LLBit) = 1;
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uint32_t PhysicalAddr;
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bool MemoryUsed;
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g_TLB->VAddrToPAddr(Address, PhysicalAddr, MemoryUsed);
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_CP0[17] = PhysicalAddr >> 4;
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}
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}
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@ -2151,7 +2159,7 @@ void R4300iOp::COP1_S_MOV()
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{
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return;
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}
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*_FPR_UDW[m_Opcode.fd] = (*(uint64_t *)_FPR_D[m_Opcode.fs] & 0xFFFFFFFF00000000ll) | *(uint32_t *)_FPR_S_L[m_Opcode.fs];
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*_FPR_UDW[m_Opcode.fd] = (*(uint64_t *)_FPR_D[m_Opcode.fs] & 0xFFFFFFFF00000000ll) | *(uint32_t *)_FPR_S_L[m_Opcode.fs];
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}
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void R4300iOp::COP1_S_NEG()
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@ -93,7 +93,7 @@ bool DisplayControlRegHandler::Write32(uint32_t Address, uint32_t Value, uint32_
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break;
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case 0x04100004:
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DPC_END_REG = MaskedValue & 0xFFFFF8;
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if (DPC_STATUS_REG & DPC_STATUS_START_VALID)
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if (DPC_STATUS_REG & DPC_STATUS_START_VALID)
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{
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DPC_CURRENT_REG = DPC_START_REG;
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DPC_STATUS_REG &= ~DPC_STATUS_START_VALID;
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@ -768,7 +768,7 @@ void CRegisters::FixFpuLocations()
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m_FPR_S[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].F[i & 1] : &m_FPR[i].F[0];
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m_FPR_S_L[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].F[0] : &m_FPR[i].F[0];
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m_FPR_D[i] = STATUS_REGISTER.FR == 0 ? &m_FPR[i & ~1].D : &m_FPR[i].D;
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}
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}
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}
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bool CRegisters::DoIntrException()
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@ -323,7 +323,7 @@ bool CTLB::VAddrToPAddr(uint64_t VAddr, uint32_t & PAddr, bool & MemoryUnused)
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}
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if (Segment == MemorySegment_Direct32 || Segment == MemorySegment_Cached32)
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{
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PAddr = VAddr & 0x1FFFFFFF;
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PAddr = VAddr & 0x7FFFFFFF;
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return true;
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}
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return false;
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