zilmar
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d357d20aad
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Merge branch 'develop' of https://github.com/project64/project64 into develop
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2025-05-29 20:19:25 +09:30 |
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zilmar
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ef879f6370
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Gfx Spec: Add draw status
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2025-05-29 20:18:51 +09:30 |
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Denis Kopyrin
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7d5c867bfd
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Core: Fixed recompiler memory overrun for m_TestTimer (#2480)
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2025-05-29 15:43:40 +09:30 |
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zilmar
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85de557b80
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Core: remove graphics plugin debug code that is not currently being used
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2025-05-29 12:04:20 +09:30 |
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zilmar
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95037a4801
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fix clang issue
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2025-05-23 14:44:06 +09:30 |
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zilmar
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51026ac8c3
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Core: Added RSP registers for gfx plugin
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2025-05-22 22:48:30 +09:30 |
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zilmar
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4e18341f5f
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Input: Use settings to handle emulation pause
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2025-05-22 12:25:37 +09:30 |
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zilmar
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0cf8b1ddf6
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core: Get CSettingTypeSelectedDirectory to normalise directories passed to it
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2025-05-15 12:05:56 +09:30 |
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zilmar
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1edb5debdf
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Core: have CRecompiler::RecompilerMain_VirtualTable handle PC as 32bit and clean up recompiler memory reset
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2025-02-27 20:47:37 +10:30 |
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Fanatic-64
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70c44965b0
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CIC improvements (#2455)
* Add CIC CRCs for iQue Player games
* Give proper name to 64DD IPL US CIC
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2025-02-21 12:13:52 +10:30 |
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zilmar
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daa8dbc833
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core: reset m_InstructionRegion on R4300iOp::ExecuteOps
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2025-02-21 12:00:41 +10:30 |
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zilmar
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7eaf1c4ba3
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Core: do not write back rt in CX86RecompilerOps::CompileLoadMemoryValue on exception
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2025-02-21 11:13:54 +10:30 |
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zilmar
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5d21bf80b9
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core: fix up missing exception check in CX86RecompilerOps::SPECIAL_DIV
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2025-02-21 06:15:07 +10:30 |
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zilmar
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fa57ce7fb8
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core: make CX86RecompilerOps::SPECIAL_JALR handle 64bit PC
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2025-02-20 13:25:44 +10:30 |
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zilmar
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5e029ecf6a
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Core: CX86RecompilerOps::CompileLoadMemoryValue some work on it generating an exception from invalid load address
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2025-02-13 22:20:00 +10:30 |
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zilmar
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bd38e7f2d6
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Core: In CX86RecompilerOps::SPECIAL_JR store PC as 64bit
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2025-02-13 22:15:20 +10:30 |
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zilmar
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9d28d9cf28
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core: More work in making sure the Compiler sets 64bit PC
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2025-02-13 16:29:25 +10:30 |
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zilmar
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1debcd1ca5
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Core: In CX86RecompilerOps::CompileExit, make sure writing 64bit PC
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2025-02-13 16:08:11 +10:30 |
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zilmar
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a82c11b8bb
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Core: When syncing CPU make sure PC matches on 64bit address
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2025-02-13 15:57:53 +10:30 |
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zilmar
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20f3e5e123
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Core: In CX86RecompilerOps::COP1_S_CVT, CX86RecompilerOps::CompileCheckFPUResult32 set softfloat_exceptionFlags to the FPU exception value
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2025-02-13 15:55:16 +10:30 |
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zilmar
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a07f6eaf90
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Core: In CX86RecompilerOps::COP0_MT update the count register when writing to Count
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2025-02-13 12:24:20 +10:30 |
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zilmar
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a5a2c8cf6d
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Core: in CRecompiler::RecompilerMain_Lookup when TriggerAddressException has occured, update the PC before checking if valid
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2025-02-13 12:22:52 +10:30 |
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zilmar
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8ae9d7b9ff
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Core: In R4300iOp::ExecuteOps only update UpdateInstructionMemory at the start of the loop
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2025-02-13 12:19:22 +10:30 |
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zilmar
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b8a514a483
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core: Create instruction region to update after a block
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2025-02-06 16:09:31 +10:30 |
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zilmar
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4a68941c08
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Core: Speed up some debugger usage in interepter if not being used
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2025-02-06 12:24:39 +10:30 |
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zilmar
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3a0c4f5da6
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core: Fix CPU % numbers
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2025-02-06 07:55:12 +10:30 |
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zilmar
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fd062a288a
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Core: Convert interpter FPU ops to use softfloat
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2025-02-04 07:15:24 +10:30 |
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zilmar
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00a978ca1b
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Core: add edge condition test to DDIV in interpter
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2025-01-31 06:18:36 +10:30 |
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Fanatic-64
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ec6d9336a6
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Fix wrong initial texture and log directories (#2454)
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2025-01-16 22:31:27 +10:30 |
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Fanatic-64
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5cd2f0253b
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Fix wrong setting names in Project64.cfg for LogRomHeader and LogUnknown (#2452)
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2025-01-08 23:03:29 +10:30 |
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zilmar
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c7d8a70a4d
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Core: fix jump in CX86RecompilerOps::CompileSystemCheck
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2024-12-27 09:02:37 +10:30 |
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zilmar
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bfa3788562
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Core: CX86RecompilerOps::COP1_D_Opcode fix return type of floating point register
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2024-12-26 14:29:52 +10:30 |
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zilmar
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3c7e71adca
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Core: Fix up CX86RecompilerOps::COP1_D_Opcode for the registers it is using
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2024-12-26 14:16:26 +10:30 |
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zilmar
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fc79cb0344
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Core: Add DwordLower for cvt.w
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2024-12-26 09:35:07 +10:30 |
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zilmar
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7e74b98d5b
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Core: Fix up labels in CX86RecompilerOps::COP1_S_CVT
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2024-12-19 21:59:42 +10:30 |
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zilmar
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57f278416e
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core: better handling of fpu registers with COP1_S_Opcode
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2024-12-19 19:09:31 +10:30 |
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zilmar
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13a974e687
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Core: in CX86RecompilerOps::COP1_CT ignore write to other registers
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2024-12-19 09:58:30 +10:30 |
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zilmar
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fba1c4bc3b
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Core: Fix up bug in CX86RecompilerOps::SPECIAL_AND
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2024-12-19 09:57:25 +10:30 |
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zilmar
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473aeba2cf
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Core: Fix order of value in call to CMipsMemoryVM::SD_VAddr32 in recompiler
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2024-12-12 21:22:32 +10:30 |
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zilmar
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5d64b3d920
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Core: Better handling of Storing non 32bit values to non memory
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2024-12-12 16:50:36 +10:30 |
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zilmar
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3164caf2d0
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Core: allow Store/load ops be forced to 32bit version
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2024-12-08 11:15:39 +10:30 |
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zilmar
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8392ea5c0f
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Core fix up load states
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2024-12-06 21:50:31 +10:30 |
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zilmar
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c6b41da926
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Add Overclock modifier to Defaults panel
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2024-12-05 17:30:59 +10:30 |
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zilmar
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77cd679756
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Core: Fix a bug in CX86RecompilerOps::SPECIAL_DIV
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2024-12-05 17:05:52 +10:30 |
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zilmar
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fc1210aac5
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Core: Do not allow CX86RecompilerOps::SPECIAL_DSRL32 and CX86RecompilerOps::SPECIAL_DSRA32 to write to R0
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2024-12-05 11:25:20 +10:30 |
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zilmar
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1e4ab04121
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Core: Fix up CX86RecompilerOps::SPECIAL_DSUB when rd == rt
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2024-12-05 11:06:42 +10:30 |
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zilmar
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04c1c3d024
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Core: Fix up CX86RecompilerOps::SPECIAL_DADD
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2024-12-05 10:03:45 +10:30 |
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zilmar
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1f3ef6d505
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Core: CX86RecompilerOps::SPECIAL_NOR Ignore write to r0
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2024-11-28 15:54:36 +10:30 |
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zilmar
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95015302d6
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Core: Have CX86RecompilerOps::SPECIAL_XOR treat R0 as 64bit constant
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2024-11-28 15:38:54 +10:30 |
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zilmar
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a3c777ed84
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Core: Have CX86RecompilerOps::SPECIAL_AND unmap the register on const write
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2024-11-28 15:14:26 +10:30 |