zilmar
|
7e74b98d5b
|
Core: Fix up labels in CX86RecompilerOps::COP1_S_CVT
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2024-12-19 21:59:42 +10:30 |
|
zilmar
|
57f278416e
|
core: better handling of fpu registers with COP1_S_Opcode
|
2024-12-19 19:09:31 +10:30 |
|
zilmar
|
13a974e687
|
Core: in CX86RecompilerOps::COP1_CT ignore write to other registers
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2024-12-19 09:58:30 +10:30 |
|
zilmar
|
fba1c4bc3b
|
Core: Fix up bug in CX86RecompilerOps::SPECIAL_AND
|
2024-12-19 09:57:25 +10:30 |
|
zilmar
|
473aeba2cf
|
Core: Fix order of value in call to CMipsMemoryVM::SD_VAddr32 in recompiler
|
2024-12-12 21:22:32 +10:30 |
|
zilmar
|
5d64b3d920
|
Core: Better handling of Storing non 32bit values to non memory
|
2024-12-12 16:50:36 +10:30 |
|
zilmar
|
3164caf2d0
|
Core: allow Store/load ops be forced to 32bit version
|
2024-12-08 11:15:39 +10:30 |
|
zilmar
|
8392ea5c0f
|
Core fix up load states
|
2024-12-06 21:50:31 +10:30 |
|
zilmar
|
c6b41da926
|
Add Overclock modifier to Defaults panel
|
2024-12-05 17:30:59 +10:30 |
|
zilmar
|
77cd679756
|
Core: Fix a bug in CX86RecompilerOps::SPECIAL_DIV
|
2024-12-05 17:05:52 +10:30 |
|
zilmar
|
fc1210aac5
|
Core: Do not allow CX86RecompilerOps::SPECIAL_DSRL32 and CX86RecompilerOps::SPECIAL_DSRA32 to write to R0
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2024-12-05 11:25:20 +10:30 |
|
zilmar
|
1e4ab04121
|
Core: Fix up CX86RecompilerOps::SPECIAL_DSUB when rd == rt
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2024-12-05 11:06:42 +10:30 |
|
zilmar
|
04c1c3d024
|
Core: Fix up CX86RecompilerOps::SPECIAL_DADD
|
2024-12-05 10:03:45 +10:30 |
|
zilmar
|
1f3ef6d505
|
Core: CX86RecompilerOps::SPECIAL_NOR Ignore write to r0
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2024-11-28 15:54:36 +10:30 |
|
zilmar
|
95015302d6
|
Core: Have CX86RecompilerOps::SPECIAL_XOR treat R0 as 64bit constant
|
2024-11-28 15:38:54 +10:30 |
|
zilmar
|
a3c777ed84
|
Core: Have CX86RecompilerOps::SPECIAL_AND unmap the register on const write
|
2024-11-28 15:14:26 +10:30 |
|
zilmar
|
0de0bea07a
|
Core: Ignore write in CX86RecompilerOps::SPECIAL_OR
|
2024-11-28 12:37:42 +10:30 |
|
zilmar
|
8d69671e93
|
Core: CX86RecompilerOps::ADDIU should not ignore when not 32bit mapped
|
2024-11-28 12:29:35 +10:30 |
|
zilmar
|
52d904702f
|
Core: With CONST64 CX86RegInfo::WriteBackRegisters might not write the high 32bit correct
|
2024-11-28 11:39:41 +10:30 |
|
zilmar
|
d5367d9291
|
Core: Better handling of SW with address not sign extended
|
2024-11-28 11:02:38 +10:30 |
|
zilmar
|
fd05d9f42f
|
core: if lwl or lwr, in CX86RecompilerOps::CompileLoadMemoryValue, make sure that we are loading rt
|
2024-11-21 21:33:42 +10:30 |
|
zilmar
|
315d5b9e66
|
Core: When running as recompiler in 32bit mode, if LW/SW are in delay slots on block boundaries use 32bit interpter functions
|
2024-11-21 19:13:56 +10:30 |
|
zilmar
|
5e1a40fffb
|
Core: fix CX86RecompilerOps::CompileLoadMemoryValue Map_GPR_32bit when called from LWC1
|
2024-11-21 11:10:01 +10:30 |
|
zilmar
|
48b3e5a9a2
|
Core: Zip load in CN64System::LoadState uses utf16 path
|
2024-11-21 10:48:16 +10:30 |
|
zilmar
|
58a13b8e28
|
Core: Get Zip files to use utf16 paths
|
2024-11-21 10:43:56 +10:30 |
|
zilmar
|
2ec9ed08a4
|
Core: Improve LW with address not sign extended test in recompiler
|
2024-11-14 17:02:18 +10:30 |
|
zilmar
|
944dd0917a
|
Core: Fix up logging id for label symbols
|
2024-11-14 09:31:45 +10:30 |
|
zilmar
|
61aa53f1a5
|
Core: In jump ops, Only add label symbol if logging
|
2024-11-14 07:30:39 +10:30 |
|
zilmar
|
97b2579b4b
|
Core: Have the recompiler just deal with the Program Counter as 32bit
|
2024-11-07 17:05:16 +10:30 |
|
zilmar
|
f63244cfa4
|
Core: Handle duplicate symbols in AddLabelSymbol
|
2024-11-07 13:37:10 +10:30 |
|
zilmar
|
72e6ee1a2b
|
Core: Normalize RomDatabase, VideoRDB, AudioRdb file paths
|
2024-11-07 13:24:45 +10:30 |
|
zilmar
|
e419508c2b
|
Core: On ExitReason_CheckPCAlignment make sure CompileSystemCheck is called
|
2024-11-07 12:13:28 +10:30 |
|
zilmar
|
a46ac9f38d
|
Core: in CX86Ops::_log better handle label symbols
|
2024-11-07 12:12:44 +10:30 |
|
zilmar
|
d06212e766
|
Core: CX86RecompilerOps::JAL stop double call to UpdateCounters
|
2024-11-07 11:05:55 +10:30 |
|
zilmar
|
bfd181f33e
|
Core: Fix up recompiler log including 0x in number symbols
|
2024-11-07 09:22:56 +10:30 |
|
zilmar
|
24d5a6bd65
|
Core: fix up clang formatting
|
2024-10-31 07:01:32 +10:30 |
|
zilmar
|
905254615d
|
Core: Change the handling of symbols inside asmjit usage
|
2024-10-31 06:50:17 +10:30 |
|
zilmar
|
17c501fa08
|
Core: clean up some code related to CompileStoreMemoryValue, like the exit method being an exception
|
2024-10-24 13:32:02 +10:30 |
|
zilmar
|
a8c8e751fc
|
Core: log the block code to the asm log file
|
2024-10-24 12:11:15 +10:30 |
|
zilmar
|
885d31f275
|
Core: Update Map_MemoryStack to pass gp by reference
|
2024-10-24 12:01:14 +10:30 |
|
zilmar
|
440894992a
|
Core: remove the BreakPoint in handling ExitReason_CheckPCAlignment
|
2024-10-24 11:58:53 +10:30 |
|
zilmar
|
65ede5e3e8
|
Core: If jumping to an unaligned address then generate an exception
|
2024-10-24 10:31:48 +10:30 |
|
zilmar
|
4a42466559
|
Core: In compiling a block be able to trace the time to compile
|
2024-10-24 10:04:45 +10:30 |
|
zilmar
|
5750d3df80
|
Core: Have only one function to do what R4300iOp::ExecuteOps and R4300iOp::ExecuteCPU was doing
|
2024-10-24 09:59:41 +10:30 |
|
zilmar
|
c39582b9ed
|
Core: Make sure CX86RecompilerOps::SPECIAL_AND can not write to R0
|
2024-10-17 18:42:45 +10:30 |
|
zilmar
|
a38467cc19
|
Core: Reset Memory Stack Pos In recompiler after running interpter code at non rdram location
|
2024-10-17 18:40:37 +10:30 |
|
zilmar
|
f708e5c0b2
|
Core: Check recompiler memory based on the function size
|
2024-10-17 15:05:48 +10:30 |
|
zilmar
|
45e52e1d2a
|
Core: in SPECIAL_SYSCALL, SPECIAL_BREAK only exit the block is the stage is PIPELINE_STAGE_NORMAL
|
2024-10-17 14:12:46 +10:30 |
|
zilmar
|
a2e479a705
|
Core: Handle paths with non-ASCII characters
|
2024-10-10 18:01:10 +10:30 |
|
zilmar
|
c176f61aac
|
Core: Normalize Plugin dir
|
2024-10-10 10:12:53 +10:30 |