Core: Get Fast tlb to just be 32bit
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parent
dcb6969067
commit
8f4f434820
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@ -94,7 +94,7 @@ void R4300iOp::ExecuteCPU()
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{
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if (!m_MMU.MemoryValue32(m_PROGRAM_COUNTER, m_Opcode.Value))
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{
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m_Reg.TriggerAddressException(m_PROGRAM_COUNTER, EXC_RMISS);
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m_Reg.TriggerAddressException((int32_t)m_PROGRAM_COUNTER, EXC_RMISS);
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m_PROGRAM_COUNTER = JumpToLocation;
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PipelineStage = PIPELINE_STAGE_NORMAL;
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continue;
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@ -305,7 +305,7 @@ void R4300iOp::ExecuteOps(int32_t Cycles)
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}
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else
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{
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m_Reg.TriggerAddressException(m_PROGRAM_COUNTER, EXC_RMISS);
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m_Reg.TriggerAddressException((int32_t)m_PROGRAM_COUNTER, EXC_RMISS);
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m_PROGRAM_COUNTER = JumpToLocation;
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PipelineStage = PIPELINE_STAGE_NORMAL;
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}
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@ -647,7 +647,7 @@ bool CMipsMemoryVM::LB_VAddr32(uint32_t VAddr, uint8_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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m_Reg.TriggerAddressException(VAddr, EXC_RMISS);
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m_Reg.TriggerAddressException((int32_t)VAddr, EXC_RMISS);
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return false;
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}
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return LB_PhysicalAddress(BaseAddress + VAddr, Value);
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@ -658,7 +658,7 @@ bool CMipsMemoryVM::LH_VAddr32(uint32_t VAddr, uint16_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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m_Reg.TriggerAddressException(VAddr, EXC_RMISS);
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m_Reg.TriggerAddressException((int32_t)VAddr, EXC_RMISS);
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return false;
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}
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return LH_PhysicalAddress(BaseAddress + VAddr, Value);
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@ -669,7 +669,7 @@ bool CMipsMemoryVM::LW_VAddr32(uint32_t VAddr, uint32_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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m_Reg.TriggerAddressException(VAddr, EXC_RMISS);
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m_Reg.TriggerAddressException((int32_t)VAddr, EXC_RMISS);
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return false;
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}
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return LW_PhysicalAddress(BaseAddress + VAddr, Value);
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@ -680,7 +680,7 @@ bool CMipsMemoryVM::LD_VAddr32(uint32_t VAddr, uint64_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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m_Reg.TriggerAddressException(VAddr, EXC_RMISS);
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m_Reg.TriggerAddressException((int32_t)VAddr, EXC_RMISS);
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return false;
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}
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return LD_PhysicalAddress(BaseAddress + VAddr, Value);
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@ -821,7 +821,7 @@ bool CMipsMemoryVM::SB_VAddr32(uint32_t VAddr, uint32_t Value)
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uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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m_Reg.TriggerAddressException(VAddr, EXC_WMISS);
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m_Reg.TriggerAddressException((int32_t)VAddr, EXC_WMISS);
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return false;
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}
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return SB_PhysicalAddress(BaseAddress + VAddr, Value);
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@ -832,7 +832,7 @@ bool CMipsMemoryVM::SH_VAddr32(uint32_t VAddr, uint32_t Value)
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uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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m_Reg.TriggerAddressException(VAddr, EXC_WMISS);
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m_Reg.TriggerAddressException((int32_t)VAddr, EXC_WMISS);
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return false;
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}
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return SH_PhysicalAddress(BaseAddress + VAddr, Value);
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@ -843,7 +843,7 @@ bool CMipsMemoryVM::SW_VAddr32(uint32_t VAddr, uint32_t Value)
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uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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m_Reg.TriggerAddressException(VAddr, EXC_WMISS);
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m_Reg.TriggerAddressException((int32_t)VAddr, EXC_WMISS);
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return false;
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}
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return SW_PhysicalAddress(BaseAddress + VAddr, Value);
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@ -854,7 +854,7 @@ bool CMipsMemoryVM::SD_VAddr32(uint32_t VAddr, uint64_t Value)
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uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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m_Reg.TriggerAddressException(VAddr, EXC_WMISS);
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m_Reg.TriggerAddressException((int32_t)VAddr, EXC_WMISS);
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return false;
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}
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return SD_PhysicalAddress(BaseAddress + VAddr, Value);
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@ -1109,16 +1109,11 @@ const char * CMipsMemoryVM::LabelName(uint32_t Address) const
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return m_strLabelName;
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}
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void CMipsMemoryVM::TLB_Mapped(uint64_t VAddr, uint32_t Len, uint32_t PAddr, bool bReadOnly)
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void CMipsMemoryVM::TLB_Mapped(uint32_t VAddr, uint32_t Len, uint32_t PAddr, bool bReadOnly)
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{
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uint64_t VEnd = VAddr + Len;
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for (uint64_t Address = VAddr; Address < VEnd; Address += 0x1000)
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{
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if ((uint64_t)((int32_t)Address) != Address)
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{
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break;
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}
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size_t Index = (size_t)(Address >> 12);
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if ((Address - VAddr + PAddr) < m_AllocatedRdramSize)
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{
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@ -1136,15 +1131,11 @@ void CMipsMemoryVM::TLB_Mapped(uint64_t VAddr, uint32_t Len, uint32_t PAddr, boo
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}
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}
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void CMipsMemoryVM::TLB_Unmaped(uint64_t Vaddr, uint32_t Len)
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void CMipsMemoryVM::TLB_Unmaped(uint32_t Vaddr, uint32_t Len)
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{
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uint64_t End = Vaddr + Len;
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for (uint64_t Address = Vaddr; Address < End && Address >= Vaddr; Address += 0x1000)
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{
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if ((uint64_t)((int32_t)Address) != Address)
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{
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continue;
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}
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size_t Index = (size_t)(Address >> 12);
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m_MemoryReadMap[Index] = (size_t)-1;
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m_MemoryWriteMap[Index] = (size_t)-1;
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@ -122,8 +122,8 @@ public:
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void UnProtectMemory(uint32_t StartVaddr, uint32_t EndVaddr);
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// Functions for TLB notification
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void TLB_Mapped(uint64_t VAddr, uint32_t Len, uint32_t PAddr, bool bReadOnly);
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void TLB_Unmaped(uint64_t Vaddr, uint32_t Len);
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void TLB_Mapped(uint32_t VAddr, uint32_t Len, uint32_t PAddr, bool bReadOnly);
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void TLB_Unmaped(uint32_t Vaddr, uint32_t Len);
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bool ValidVaddr(uint32_t VAddr) const;
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bool VAddrToPAddr(uint32_t VAddr, uint32_t & PAddr) const;
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@ -226,12 +226,13 @@ void CTLB::SetupTLB_Entry(uint32_t Index, bool Random)
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TLB_Unmaped(m_FastTlb[FastIndx].VSTART, m_FastTlb[FastIndx].Length);
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}
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m_FastTlb[FastIndx].Length = (uint32_t)((m_tlb[Index].PageMask.Mask << 12) + 0xFFF);
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m_FastTlb[FastIndx].VSTART = ((uint64_t)m_tlb[Index].EntryHi.R() << 62) | ((uint64_t)m_tlb[Index].EntryHi.VPN2() << 13);
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m_FastTlb[FastIndx].Region = (uint8_t)m_tlb[Index].EntryHi.R();
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m_FastTlb[FastIndx].VSTART = (uint32_t)(m_tlb[Index].EntryHi.VPN2() << 13);
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m_FastTlb[FastIndx].VEND = m_FastTlb[FastIndx].VSTART + m_FastTlb[FastIndx].Length;
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m_FastTlb[FastIndx].PHYSSTART = (uint32_t)(m_tlb[Index].EntryLo0.PFN << 12);
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m_FastTlb[FastIndx].PHYSEND = m_FastTlb[FastIndx].PHYSSTART + m_FastTlb[FastIndx].Length;
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m_FastTlb[FastIndx].VALID = m_tlb[Index].EntryLo0.V;
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m_FastTlb[FastIndx].DIRTY = m_tlb[Index].EntryLo0.D;
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m_FastTlb[FastIndx].VALID = m_tlb[Index].EntryLo0.V != 0;
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m_FastTlb[FastIndx].DIRTY = m_tlb[Index].EntryLo0.D != 0;
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m_FastTlb[FastIndx].GLOBAL = m_tlb[Index].EntryLo0.GLOBAL & m_tlb[Index].EntryLo1.GLOBAL;
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m_FastTlb[FastIndx].ValidEntry = false;
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m_FastTlb[FastIndx].Random = Random;
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@ -243,12 +244,13 @@ void CTLB::SetupTLB_Entry(uint32_t Index, bool Random)
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TLB_Unmaped(m_FastTlb[FastIndx].VSTART, m_FastTlb[FastIndx].Length);
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}
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m_FastTlb[FastIndx].Length = (uint32_t)((m_tlb[Index].PageMask.Mask << 12) + 0xFFF);
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m_FastTlb[FastIndx].VSTART = ((uint64_t)m_tlb[Index].EntryHi.R() << 62 | ((uint64_t)m_tlb[Index].EntryHi.VPN2() << 13)) + (m_FastTlb[FastIndx].Length + 1);
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m_FastTlb[FastIndx].Region = (uint8_t)m_tlb[Index].EntryHi.R();
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m_FastTlb[FastIndx].VSTART = (uint32_t)(m_tlb[Index].EntryHi.VPN2() << 13) + (m_FastTlb[FastIndx].Length + 1);
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m_FastTlb[FastIndx].VEND = m_FastTlb[FastIndx].VSTART + m_FastTlb[FastIndx].Length;
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m_FastTlb[FastIndx].PHYSSTART = (uint32_t)m_tlb[Index].EntryLo1.PFN << 12;
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m_FastTlb[FastIndx].PHYSEND = m_FastTlb[FastIndx].PHYSSTART + m_FastTlb[FastIndx].Length;
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m_FastTlb[FastIndx].VALID = m_tlb[Index].EntryLo1.V;
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m_FastTlb[FastIndx].DIRTY = m_tlb[Index].EntryLo1.D;
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m_FastTlb[FastIndx].VALID = m_tlb[Index].EntryLo1.V != 0;
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m_FastTlb[FastIndx].DIRTY = m_tlb[Index].EntryLo1.D != 0;
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m_FastTlb[FastIndx].GLOBAL = m_tlb[Index].EntryLo0.GLOBAL & m_tlb[Index].EntryLo1.GLOBAL;
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m_FastTlb[FastIndx].ValidEntry = false;
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m_FastTlb[FastIndx].Random = Random;
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@ -263,6 +265,16 @@ void CTLB::SetupTLB_Entry(uint32_t Index, bool Random)
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continue;
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}
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if ((m_FastTlb[FastIndx].VSTART & 0x80000000) == 0 && m_FastTlb[FastIndx].Region != 0)
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{
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continue;
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}
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if ((m_FastTlb[FastIndx].VSTART & 0x80000000) != 0 && m_FastTlb[FastIndx].Region != 3)
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{
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continue;
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}
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if (m_FastTlb[FastIndx].VEND <= m_FastTlb[FastIndx].VSTART)
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{
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continue;
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@ -282,10 +294,10 @@ void CTLB::SetupTLB_Entry(uint32_t Index, bool Random)
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}
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}
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void CTLB::TLB_Unmaped(uint64_t VAddr, uint32_t Len)
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void CTLB::TLB_Unmaped(uint32_t VAddr, uint32_t Len)
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{
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m_MMU.TLB_Unmaped(VAddr, Len);
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if (m_Recomp && bSMM_TLB() && (uint64_t)((int32_t)VAddr) == VAddr)
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if (m_Recomp && bSMM_TLB())
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{
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m_Recomp->ClearRecompCode_Virt((uint32_t)VAddr, Len, CRecompiler::Remove_TLB);
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}
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@ -302,17 +314,27 @@ bool CTLB::VAddrToPAddr(uint64_t VAddr, uint32_t & PAddr, bool & MemoryUnused)
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MemorySegment Segment = VAddrMemorySegment(VAddr);
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if (Segment == MemorySegment_Mapped)
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{
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for (int i = 0; i < 64; i++)
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for (uint32_t i = 0; i < 32; i++)
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{
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if (m_FastTlb[i].ValidEntry == false)
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if (m_tlb[i].EntryLo0.GLOBAL == 0)
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{
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continue;
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}
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if (VAddr >= m_FastTlb[i].VSTART && VAddr < m_FastTlb[i].VEND)
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if ((VAddr & 0xE000000000000000) != ((uint64_t)m_tlb[i].EntryHi.R() << 62))
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{
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PAddr = (uint32_t)(m_FastTlb[i].PHYSSTART + (VAddr - m_FastTlb[i].VSTART));
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return true;
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continue;
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}
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uint64_t PageMask = (m_tlb[i].PageMask.Mask << 12);
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uint64_t AddressMaskHi = ~(PageMask | 0x1fff) & 0xFFFFFFFFFF;
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uint64_t AddressRegion = ((uint64_t)m_tlb[i].EntryHi.VPN2() << 13);
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if ((VAddr & AddressMaskHi) != AddressRegion)
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{
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continue;
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}
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uint64_t AddressSelect = ((m_tlb[i].PageMask.Mask << 12) | 0xfff) + 1;
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COP0EntryLo EntryLo = (VAddr & AddressSelect) != 0 ? m_tlb[i].EntryLo1 : m_tlb[i].EntryLo0;
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PAddr = (uint32_t)((EntryLo.PFN << 12) + (VAddr & (PageMask | 0x1fff)));
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return true;
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}
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return false;
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}
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@ -35,11 +35,12 @@ class CTLB :
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struct FASTTLB
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{
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uint64_t VSTART;
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uint64_t VEND;
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uint32_t VSTART;
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uint32_t VEND;
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uint32_t PHYSSTART;
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uint32_t PHYSEND;
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uint32_t Length;
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uint8_t Region;
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bool VALID;
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bool DIRTY;
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bool GLOBAL;
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@ -73,7 +74,7 @@ private:
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CTLB & operator=(const CTLB &);
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void SetupTLB_Entry(uint32_t Index, bool Random);
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void TLB_Unmaped(uint64_t VAddr, uint32_t Len);
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void TLB_Unmaped(uint32_t VAddr, uint32_t Len);
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MemorySegment VAddrMemorySegment(uint64_t VAddr);
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PRIVILEGE_MODE m_PrivilegeMode;
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@ -265,7 +265,7 @@ void CDebugTlb::RefreshTLBWindow(void)
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if (FastTlb[count].ValidEntry && FastTlb[count].VALID)
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{
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swprintf(Output, sizeof(Output), L"%llX:%llX -> %08X:%08X", FastTlb[count].VSTART, FastTlb[count].VEND,
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swprintf(Output, sizeof(Output), L"%08X:%08X -> %08X:%08X", FastTlb[count].VSTART, FastTlb[count].VEND,
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FastTlb[count].PHYSSTART, FastTlb[count].PHYSEND);
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}
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else
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