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Core: Change Non memory load/store to not use tlb

This commit is contained in:
zilmar 2023-10-05 09:32:45 +10:30
parent a975af0e3c
commit b7311cc611
5 changed files with 167 additions and 141 deletions
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70
Source/Project64-core/MemoryExceptionFilter.cpp
View File

@ -171,7 +171,7 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
case 0xB6:
{
uint8_t Value = 0;
g_MMU->LB_NonMemory((MemAddress | 0x80000000) ^ 3, Value);
g_MMU->LB_PhysicalAddress(MemAddress ^ 3, Value);
*(uint32_t *)Reg = Value;
*context.Eip = (uint32_t)ReadPos;
return true;
@ -179,7 +179,7 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
case 0xB7:
{
uint16_t Value = 0;
g_MMU->LH_NonMemory((MemAddress | 0x80000000) ^ 2, Value);
g_MMU->LH_PhysicalAddress(MemAddress ^ 2, Value);
*(uint32_t *)Reg = Value;
*context.Eip = (uint32_t)ReadPos;
return true;
@ -187,7 +187,7 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
case 0xBE:
{
uint8_t Value = 0;
g_MMU->LB_NonMemory((MemAddress | 0x80000000) ^ 3, Value);
g_MMU->LB_PhysicalAddress(MemAddress ^ 3, Value);
*(int32_t *)Reg = (int8_t)Value;
*context.Eip = (uint32_t)ReadPos;
return true;
@ -195,7 +195,7 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
case 0xBF:
{
uint16_t Value = 0;
g_MMU->LH_NonMemory((MemAddress | 0x80000000) ^ 2, Value);
g_MMU->LH_PhysicalAddress(MemAddress ^ 2, Value);
*(int32_t *)Reg = (int16_t)Value;
*context.Eip = (uint32_t)ReadPos;
return true;
@ -214,17 +214,17 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
case 0x8B:
{
uint16_t Value = 0;
g_MMU->LH_NonMemory((MemAddress | 0x80000000) ^ 2, Value);
g_MMU->LH_PhysicalAddress(MemAddress ^ 2, Value);
*(uint32_t *)Reg = Value;
*context.Eip = (uint32_t)ReadPos;
return true;
}
case 0x89:
g_MMU->SH_NonMemory((MemAddress | 0x80000000) ^ 2, *(uint16_t *)Reg);
g_MMU->SH_PhysicalAddress(MemAddress ^ 2, *(uint16_t *)Reg);
*context.Eip = (uint32_t)ReadPos;
return true;
case 0xA3:
g_MMU->SH_NonMemory((MemAddress | 0x80000000) ^ 2, *(uint16_t *)context.Eax);
g_MMU->SH_PhysicalAddress(MemAddress ^ 2, *(uint16_t *)context.Eax);
*context.Eip += 6;
return true;
case 0xC7:
@ -236,7 +236,7 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
}
return false;
}
g_MMU->SH_NonMemory((MemAddress | 0x80000000) ^ 2, *(uint16_t *)ReadPos);
g_MMU->SH_PhysicalAddress(MemAddress ^ 2, *(uint16_t *)ReadPos);
*context.Eip = (uint32_t)(ReadPos + 2);
return true;
default:
@ -248,23 +248,23 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
}
break;
case 0x88:
g_MMU->SB_NonMemory((MemAddress | 0x80000000) ^ 3, *(uint8_t *)Reg);
g_MMU->SB_PhysicalAddress(MemAddress ^ 3, *(uint8_t *)Reg);
*context.Eip = (uint32_t)ReadPos;
return true;
case 0x8A:
{
uint8_t Value = 0;
g_MMU->LB_NonMemory((MemAddress | 0x80000000) ^ 3, Value);
g_MMU->LB_PhysicalAddress(MemAddress ^ 3, Value);
*(uint32_t *)Reg = Value;
*context.Eip = (uint32_t)ReadPos;
return true;
}
case 0x8B:
g_MMU->LW_NonMemory(MemAddress | 0x80000000, *((uint32_t *)Reg));
g_MMU->LW_PhysicalAddress(MemAddress, *((uint32_t *)Reg));
*context.Eip = (uint32_t)ReadPos;
return true;
case 0x89:
g_MMU->SW_NonMemory(MemAddress | 0x80000000, *(uint32_t *)Reg);
g_MMU->SW_PhysicalAddress(MemAddress, *(uint32_t *)Reg);
*context.Eip = (uint32_t)ReadPos;
return true;
case 0xC6:
@ -276,7 +276,7 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
}
return false;
}
g_MMU->SB_NonMemory((MemAddress | 0x80000000) ^ 3, *(uint8_t *)ReadPos);
g_MMU->SB_PhysicalAddress(MemAddress ^ 3, *(uint8_t *)ReadPos);
*context.Eip = (uint32_t)(ReadPos + 1);
return true;
case 0xC7:
@ -288,7 +288,7 @@ bool CMipsMemoryVM::FilterX86Exception(uint32_t MemAddress, X86_CONTEXT & contex
}
return false;
}
g_MMU->SW_NonMemory(MemAddress | 0x80000000, *(uint32_t *)ReadPos);
g_MMU->SW_PhysicalAddress(MemAddress, *(uint32_t *)ReadPos);
*context.Eip = (uint32_t)(ReadPos + 4);
return true;
}
@ -407,13 +407,13 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
Arm32Opcode * OpCode32 = (Arm32Opcode *)context.arm_pc;
if (OpCode->Reg.opcode == ArmLDR_Reg)
{
g_MMU->LW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode->Reg.rt]);
g_MMU->LW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode->Reg.rt]);
context.arm_pc = context.arm_pc + 2;
return true;
}
if (OpCode->Reg.opcode == ArmSTR_Reg)
{
g_MMU->SW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode->Reg.rt]);
g_MMU->SW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode->Reg.rt]);
context.arm_pc = context.arm_pc + 2;
return true;
}
@ -421,7 +421,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->imm2.opcode == 0xF84 && OpCode32->imm2.Opcode2 == 0)
{
// 42 f8 03 c0 str.w ip, [r2, r3]
g_MMU->SW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode32->imm2.rt]);
g_MMU->SW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode32->imm2.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -429,7 +429,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->imm12.opcode == 0xF8C)
{
// c9 f8 00 b0 str.w r11, [r9]
g_MMU->SW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode32->imm2.rt]);
g_MMU->SW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode32->imm2.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -437,7 +437,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->imm12.opcode == 0xF8D)
{
// dc f8 70 70 ldr.w r7, [ip, #112]
g_MMU->LW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode32->imm12.rt]);
g_MMU->LW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode32->imm12.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -446,14 +446,14 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
{
// 17847001 strne r7, [r4, r1]
// e789300c str r3, [r9, ip]
g_MMU->SW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode32->reg_cond_imm5.rt]);
g_MMU->SW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode32->reg_cond_imm5.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
if (OpCode->Reg.opcode == 0x2A) // STRB
{
g_MMU->SB_NonMemory((MemAddress | 0x80000000) ^ 3, *ArmRegisters[OpCode->Reg.rt]);
g_MMU->SB_PhysicalAddress(MemAddress ^ 3, *ArmRegisters[OpCode->Reg.rt]);
context.arm_pc = context.arm_pc + 2;
return true;
}
@ -461,7 +461,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->reg_cond_imm5.opcode == 3 && OpCode32->reg_cond_imm5.opcode1 == 1 && OpCode32->reg_cond_imm5.opcode2 == 0 && OpCode32->reg_cond_imm5.opcode3 == 0)
{
// 17c32001 strbne r2, [r3, r1]
g_MMU->SB_NonMemory((MemAddress | 0x80000000) ^ 3, *ArmRegisters[OpCode32->reg_cond_imm5.rt]);
g_MMU->SB_PhysicalAddress(MemAddress ^ 3, *ArmRegisters[OpCode32->reg_cond_imm5.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -469,7 +469,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->reg_cond_imm8.opcode == 0 && OpCode32->reg_cond_imm8.opcode1 == 1 && OpCode32->reg_cond_imm8.opcode2 == 0 && OpCode32->reg_cond_imm8.opcode3 == 0xB)
{
// 11c020b0 strhne r2, [r0]
g_MMU->SH_NonMemory((MemAddress | 0x80000000) ^ 2, *ArmRegisters[OpCode32->reg_cond_imm8.rt]);
g_MMU->SH_PhysicalAddress(MemAddress ^ 2, *ArmRegisters[OpCode32->reg_cond_imm8.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -477,7 +477,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode->Imm5.opcode == 0x10)
{
// 00 80 strh r0, [r0, #0]
g_MMU->SH_NonMemory((MemAddress | 0x80000000) ^ 2, *ArmRegisters[OpCode->Imm5.rt]);
g_MMU->SH_PhysicalAddress(MemAddress ^ 2, *ArmRegisters[OpCode->Imm5.rt]);
context.arm_pc = context.arm_pc + 2;
return true;
}
@ -485,7 +485,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode->Reg.opcode == 0x29)
{
// 14 52 strh r4, [r2, r0]
g_MMU->SH_NonMemory((MemAddress | 0x80000000) ^ 2, *ArmRegisters[OpCode->Reg.rt]);
g_MMU->SH_PhysicalAddress(MemAddress ^ 2, *ArmRegisters[OpCode->Reg.rt]);
context.arm_pc = context.arm_pc + 2;
return true;
}
@ -493,7 +493,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode->Imm5.opcode == 0xC)
{
// 2e 60 str r6, [r5, #0]
g_MMU->SW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode->Imm5.rt]);
g_MMU->SH_PhysicalAddress(MemAddress ^ 2, *ArmRegisters[OpCode->Imm5.rt]);
context.arm_pc = context.arm_pc + 2;
return true;
}
@ -501,7 +501,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode->Imm5.opcode == 0xD)
{
// 3F 68 ldr r7, [r7, #0]
g_MMU->LW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode->Imm5.rt]);
g_MMU->LW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode->Imm5.rt]);
context.arm_pc = context.arm_pc + 2;
return true;
}
@ -509,7 +509,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode->Imm5.opcode == 0xE)
{
// b8 70 strb r0, [r7, #2]
g_MMU->SB_NonMemory((MemAddress | 0x80000000) ^ 3, *ArmRegisters[OpCode->Imm5.rt]);
g_MMU->SB_PhysicalAddress(MemAddress ^ 3, *ArmRegisters[OpCode->Imm5.rt]);
context.arm_pc = context.arm_pc + 2;
return true;
}
@ -517,7 +517,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->reg_cond.opcode == 0 && OpCode32->reg_cond.opcode1 == 0 && OpCode32->reg_cond.opcode2 == 0 && OpCode32->reg_cond.opcode3 == 0xB)
{
// 118320b1 strhne r2, [r3, r1]
g_MMU->SH_NonMemory((MemAddress | 0x80000000) ^ 2, *ArmRegisters[OpCode32->reg_cond.rt]);
g_MMU->SH_PhysicalAddress(MemAddress ^ 2, *ArmRegisters[OpCode32->reg_cond.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -525,7 +525,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->reg_cond_imm12.opcode == 2 && OpCode32->reg_cond_imm12.opcode1 == 0 && OpCode32->reg_cond_imm12.opcode2 == 0)
{
// e48a1004 str r1, [sl], #4
g_MMU->SW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode32->reg_cond_imm12.rt]);
g_MMU->SW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode32->reg_cond_imm12.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -533,7 +533,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
/*if (OpCode32->uint16.opcode == ArmLDRH_W)
{
// f833 c001 ldrh.w ip, [r3, r1]
g_MMU->LH_NonMemory((MemAddress | 0x80000000) ^ 2, ArmRegisters[OpCode32->uint16.rt]);
g_MMU->LH_PhysicalAddress(MemAddress ^ 2, ArmRegisters[OpCode32->uint16.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -541,7 +541,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->uint32.opcode == ArmLDRH_Reg && OpCode32->uint32.opcode2 == 0xB)
{
// e19a20b2 ldrh r2, [sl, r2]
g_MMU->LH_NonMemory((MemAddress | 0x80000000) ^ 2, ArmRegisters[OpCode32->uint32.rt], false);
g_MMU->LH_PhysicalAddress(MemAddress ^ 2, ArmRegisters[OpCode32->uint32.rt], false);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -550,7 +550,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
{
// 119330b1 ldrhne r3, [r3, r1]
// 11d000b0 ldrhne r0, [r0]
!g_MMU->LH_NonMemory((MemAddress | 0x80000000) ^ 2, ArmRegisters[OpCode32->reg_cond.rt], false);
!g_MMU->LH_PhysicalAddress(MemAddress ^ 2, ArmRegisters[OpCode32->reg_cond.rt], false);
context.arm_pc = context.arm_pc + 4;
return true;
}*/
@ -558,7 +558,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->reg_cond_imm5.opcode == 3 && OpCode32->reg_cond_imm5.opcode1 == 0 && OpCode32->reg_cond_imm5.opcode2 == 1 && OpCode32->reg_cond_imm5.opcode3 == 0)
{
// 1790a001 ldrne sl, [r0, r1]
g_MMU->LW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode32->reg_cond_imm5.rt]);
g_MMU->LW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode32->reg_cond_imm5.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}
@ -566,7 +566,7 @@ bool CMipsMemoryVM::FilterArmException(uint32_t MemAddress, mcontext_t & context
if (OpCode32->imm2.opcode == 0xF85 && OpCode32->imm2.Opcode2 == 0)
{
// 52 f8 21 30 ldr.w r3, [r2, r1, lsl #2]
g_MMU->LW_NonMemory(MemAddress | 0x80000000, *ArmRegisters[OpCode32->imm2.rt]);
g_MMU->LW_PhysicalAddress(MemAddress, *ArmRegisters[OpCode32->imm2.rt]);
context.arm_pc = context.arm_pc + 4;
return true;
}

173
Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp
View File

@ -370,7 +370,6 @@ bool CMipsMemoryVM::LB_Memory(uint64_t VAddr, uint8_t & Value)
return false;
}
uint32_t VAddr32 = (uint32_t)VAddr;
if (HaveReadBP() && g_Debugger->ReadBP8(VAddr32) && MemoryBreakpoint())
{
return false;
@ -381,7 +380,7 @@ bool CMipsMemoryVM::LB_Memory(uint64_t VAddr, uint8_t & Value)
Value = *(uint8_t *)(MemoryPtr + (VAddr32 ^ 3));
return true;
}
return LB_NonMemory(VAddr32, Value);
return LB_VAddr32(VAddr32, Value);
}
bool CMipsMemoryVM::LH_Memory(uint64_t VAddr, uint16_t & Value)
@ -392,7 +391,6 @@ bool CMipsMemoryVM::LH_Memory(uint64_t VAddr, uint16_t & Value)
return false;
}
uint32_t VAddr32 = (uint32_t)VAddr;
if ((VAddr32 & 1) != 0)
{
m_Reg.DoAddressError(VAddr, true);
@ -408,7 +406,7 @@ bool CMipsMemoryVM::LH_Memory(uint64_t VAddr, uint16_t & Value)
Value = *(uint16_t *)(MemoryPtr + (VAddr32 ^ 2));
return true;
}
return LH_NonMemory(VAddr32, Value);
return LH_VAddr32(VAddr32, Value);
}
bool CMipsMemoryVM::LW_Memory(uint64_t VAddr, uint32_t & Value)
@ -434,13 +432,7 @@ bool CMipsMemoryVM::LW_Memory(uint64_t VAddr, uint32_t & Value)
Value = *(uint32_t *)(MemoryPtr + VAddr32);
return true;
}
uint32_t BaseAddress = m_TLB_ReadMap[VAddr32 >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBReadMiss(VAddr);
return false;
}
return LW_NonMemory(VAddr32, Value);
return LW_VAddr32(VAddr32, Value);
}
bool CMipsMemoryVM::LD_Memory(uint64_t VAddr, uint64_t & Value)
@ -468,12 +460,7 @@ bool CMipsMemoryVM::LD_Memory(uint64_t VAddr, uint64_t & Value)
*((uint32_t *)(&Value) + 0) = *(uint32_t *)(MemoryPtr + VAddr32 + 4);
return true;
}
uint32_t BaseAddress = m_TLB_ReadMap[VAddr32 >> 12];
if (BaseAddress == -1)
{
return false;
}
return LD_NonMemory(VAddr32, Value);
return LD_VAddr32(VAddr32, Value);
}
bool CMipsMemoryVM::SB_Memory(uint64_t VAddr, uint32_t Value)
@ -495,7 +482,7 @@ bool CMipsMemoryVM::SB_Memory(uint64_t VAddr, uint32_t Value)
*(uint8_t *)(MemoryPtr + (VAddr32 ^ 3)) = (uint8_t)Value;
return true;
}
return SB_NonMemory(VAddr32, Value);
return SB_VAddr32(VAddr32, Value);
}
bool CMipsMemoryVM::SH_Memory(uint64_t VAddr, uint32_t Value)
@ -522,7 +509,7 @@ bool CMipsMemoryVM::SH_Memory(uint64_t VAddr, uint32_t Value)
*(uint16_t *)(MemoryPtr + (VAddr32 ^ 2)) = (uint16_t)Value;
return true;
}
return SH_NonMemory(VAddr32, Value);
return SH_VAddr32(VAddr32, Value);
}
bool CMipsMemoryVM::SW_Memory(uint64_t VAddr, uint32_t Value)
@ -549,7 +536,7 @@ bool CMipsMemoryVM::SW_Memory(uint64_t VAddr, uint32_t Value)
*(uint32_t *)(MemoryPtr + VAddr32) = Value;
return true;
}
return SW_NonMemory(VAddr32, Value);
return SW_VAddr32(VAddr32, Value);
}
bool CMipsMemoryVM::SD_Memory(uint64_t VAddr, uint64_t Value)
@ -578,7 +565,7 @@ bool CMipsMemoryVM::SD_Memory(uint64_t VAddr, uint64_t Value)
*(uint32_t *)(MemoryPtr + VAddr32 + 4) = *((uint32_t *)(&Value));
return true;
}
return SD_NonMemory(VAddr32, Value);
return SD_VAddr32(VAddr32, Value);
}
bool CMipsMemoryVM::ValidVaddr(uint32_t VAddr) const
@ -596,7 +583,7 @@ bool CMipsMemoryVM::VAddrToPAddr(uint32_t VAddr, uint32_t & PAddr) const
return true;
}
bool CMipsMemoryVM::LB_NonMemory(uint32_t VAddr, uint8_t & Value)
bool CMipsMemoryVM::LB_VAddr32(uint32_t VAddr, uint8_t & Value)
{
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1)
@ -604,8 +591,44 @@ bool CMipsMemoryVM::LB_NonMemory(uint32_t VAddr, uint8_t & Value)
m_Reg.DoTLBReadMiss(VAddr);
return false;
}
return LB_PhysicalAddress(BaseAddress + VAddr, Value);
}
uint32_t PAddr = BaseAddress + VAddr;
bool CMipsMemoryVM::LH_VAddr32(uint32_t VAddr, uint16_t & Value)
{
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBReadMiss(VAddr);
return false;
}
return LH_PhysicalAddress(BaseAddress + VAddr, Value);
}
bool CMipsMemoryVM::LW_VAddr32(uint32_t VAddr, uint32_t & Value)
{
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.TriggerAddressException(VAddr, EXC_RMISS);
return false;
}
return LW_PhysicalAddress(BaseAddress + VAddr, Value);
}
bool CMipsMemoryVM::LD_VAddr32(uint32_t VAddr, uint64_t & Value)
{
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.TriggerAddressException(VAddr, EXC_RMISS);
return false;
}
return LD_PhysicalAddress(BaseAddress + VAddr, Value);
}
bool CMipsMemoryVM::LB_PhysicalAddress(uint32_t PAddr, uint8_t & Value)
{
uint32_t ReadAddress = PAddr & ~3;
uint32_t Value32;
switch (PAddr & 0xFFF00000)
@ -634,16 +657,8 @@ bool CMipsMemoryVM::LB_NonMemory(uint32_t VAddr, uint8_t & Value)
return true;
}
bool CMipsMemoryVM::LH_NonMemory(uint32_t VAddr, uint16_t & Value)
bool CMipsMemoryVM::LH_PhysicalAddress(uint32_t PAddr, uint16_t & Value)
{
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBReadMiss(VAddr);
return false;
}
uint32_t PAddr = BaseAddress + VAddr;
uint32_t ReadAddress = PAddr & ~1;
uint32_t Value32;
switch (PAddr & 0xFFF00000)
@ -672,15 +687,8 @@ bool CMipsMemoryVM::LH_NonMemory(uint32_t VAddr, uint16_t & Value)
return true;
}
bool CMipsMemoryVM::LW_NonMemory(uint32_t VAddr, uint32_t & Value)
bool CMipsMemoryVM::LW_PhysicalAddress(uint32_t PAddr, uint32_t & Value)
{
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBReadMiss(VAddr);
return false;
}
uint32_t PAddr = BaseAddress + VAddr;
switch (PAddr & 0xFFF00000)
{
case 0x03F00000: m_RDRAMRegistersHandler.Read32(PAddr, Value); break;
@ -716,15 +724,8 @@ bool CMipsMemoryVM::LW_NonMemory(uint32_t VAddr, uint32_t & Value)
return true;
}
bool CMipsMemoryVM::LD_NonMemory(uint32_t VAddr, uint64_t & Value)
bool CMipsMemoryVM::LD_PhysicalAddress(uint32_t PAddr, uint64_t & Value)
{
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBReadMiss(VAddr);
return false;
}
uint32_t PAddr = BaseAddress + VAddr;
if (PAddr < 0x800000)
{
Value = 0;
@ -736,7 +737,7 @@ bool CMipsMemoryVM::LD_NonMemory(uint32_t VAddr, uint64_t & Value)
return false;
}
bool CMipsMemoryVM::SB_NonMemory(uint32_t VAddr, uint32_t Value)
bool CMipsMemoryVM::SB_VAddr32(uint32_t VAddr, uint32_t Value)
{
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1)
@ -744,7 +745,44 @@ bool CMipsMemoryVM::SB_NonMemory(uint32_t VAddr, uint32_t Value)
m_Reg.DoTLBWriteMiss(VAddr);
return false;
}
uint32_t PAddr = BaseAddress + VAddr;
return SB_PhysicalAddress(BaseAddress + VAddr, Value);
}
bool CMipsMemoryVM::SH_VAddr32(uint32_t VAddr, uint32_t Value)
{
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBWriteMiss(VAddr);
return false;
}
return SH_PhysicalAddress(BaseAddress + VAddr, Value);
}
bool CMipsMemoryVM::SW_VAddr32(uint32_t VAddr, uint32_t Value)
{
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBWriteMiss(VAddr);
return false;
}
return SW_PhysicalAddress(BaseAddress + VAddr, Value);
}
bool CMipsMemoryVM::SD_VAddr32(uint32_t VAddr, uint64_t Value)
{
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBWriteMiss(VAddr);
return false;
}
return SD_PhysicalAddress(BaseAddress + VAddr, Value);
}
bool CMipsMemoryVM::SB_PhysicalAddress(uint32_t PAddr, uint32_t Value)
{
switch (PAddr & 0xFFF00000)
{
case 0x00000000:
@ -777,15 +815,8 @@ bool CMipsMemoryVM::SB_NonMemory(uint32_t VAddr, uint32_t Value)
return true;
}
bool CMipsMemoryVM::SH_NonMemory(uint32_t VAddr, uint32_t Value)
bool CMipsMemoryVM::SH_PhysicalAddress(uint32_t PAddr, uint32_t Value)
{
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBWriteMiss(VAddr);
return false;
}
uint32_t PAddr = BaseAddress + VAddr;
switch (PAddr & 0xFFF00000)
{
case 0x00000000:
@ -807,7 +838,8 @@ bool CMipsMemoryVM::SH_NonMemory(uint32_t VAddr, uint32_t Value)
}
if (CGameSettings::bSMM_StoreInstruc())
{
m_TLB_WriteMap[VAddr >> 12] = PAddr - VAddr;
m_TLB_WriteMap[(0x80000000 + PAddr) >> 12] = PAddr - (0x80000000 + PAddr);
m_TLB_WriteMap[(0xA0000000 + PAddr) >> 12] = PAddr - (0xA0000000 + PAddr);
}
*(uint16_t *)(m_RDRAM + (PAddr ^ 2)) = (uint16_t)Value;
}
@ -830,15 +862,8 @@ bool CMipsMemoryVM::SH_NonMemory(uint32_t VAddr, uint32_t Value)
return true;
}
bool CMipsMemoryVM::SW_NonMemory(uint32_t VAddr, uint32_t Value)
bool CMipsMemoryVM::SW_PhysicalAddress(uint32_t PAddr, uint32_t Value)
{
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBWriteMiss((int64_t)((int32_t)VAddr));
return false;
}
uint32_t PAddr = BaseAddress + VAddr;
switch (PAddr & 0xFFF00000)
{
case 0x00000000:
@ -861,8 +886,8 @@ bool CMipsMemoryVM::SW_NonMemory(uint32_t VAddr, uint32_t Value)
}
if (CGameSettings::bSMM_StoreInstruc())
{
m_TLB_WriteMap[(0x80000000 + PAddr) >> 12] = PAddr - VAddr;
m_TLB_WriteMap[(0xA0000000 + PAddr) >> 12] = PAddr - VAddr;
m_TLB_WriteMap[(0x80000000 + PAddr) >> 12] = PAddr - (0x80000000 + PAddr);
m_TLB_WriteMap[(0xA0000000 + PAddr) >> 12] = PAddr - (0xA0000000 + PAddr);
}
*(uint32_t *)(m_RDRAM + PAddr) = Value;
}
@ -900,15 +925,8 @@ bool CMipsMemoryVM::SW_NonMemory(uint32_t VAddr, uint32_t Value)
return true;
}
bool CMipsMemoryVM::SD_NonMemory(uint32_t VAddr, uint64_t Value)
bool CMipsMemoryVM::SD_PhysicalAddress(uint32_t PAddr, uint64_t Value)
{
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1)
{
m_Reg.DoTLBWriteMiss(VAddr);
return false;
}
uint32_t PAddr = BaseAddress + VAddr;
switch (PAddr & 0xFFF00000)
{
case 0x00000000:
@ -938,7 +956,6 @@ bool CMipsMemoryVM::SD_NonMemory(uint32_t VAddr, uint64_t Value)
}
return false;
}
return true;
}

26
Source/Project64-core/N64System/Mips/MemoryVirtualMem.h
View File

@ -163,15 +163,25 @@ private:
static void RdramChanged(CMipsMemoryVM * _this);
static void ChangeMiIntrMask();
bool LB_NonMemory(uint32_t VAddr, uint8_t & Value);
bool LH_NonMemory(uint32_t VAddr, uint16_t & Value);
bool LW_NonMemory(uint32_t VAddr, uint32_t & Value);
bool LD_NonMemory(uint32_t VAddr, uint64_t & Value);
bool LB_VAddr32(uint32_t VAddr, uint8_t & Value);
bool LH_VAddr32(uint32_t VAddr, uint16_t & Value);
bool LW_VAddr32(uint32_t VAddr, uint32_t & Value);
bool LD_VAddr32(uint32_t VAddr, uint64_t & Value);
bool SB_NonMemory(uint32_t VAddr, uint32_t Value);
bool SH_NonMemory(uint32_t VAddr, uint32_t Value);
bool SW_NonMemory(uint32_t VAddr, uint32_t Value);
bool SD_NonMemory(uint32_t VAddr, uint64_t Value);
bool LB_PhysicalAddress(uint32_t PAddr, uint8_t & Value);
bool LH_PhysicalAddress(uint32_t PAddr, uint16_t & Value);
bool LW_PhysicalAddress(uint32_t PAddr, uint32_t & Value);
bool LD_PhysicalAddress(uint32_t PAddr, uint64_t & Value);
bool SB_VAddr32(uint32_t VAddr, uint32_t Value);
bool SH_VAddr32(uint32_t VAddr, uint32_t Value);
bool SW_VAddr32(uint32_t VAddr, uint32_t Value);
bool SD_VAddr32(uint32_t VAddr, uint64_t Value);
bool SB_PhysicalAddress(uint32_t PAddr, uint32_t Value);
bool SH_PhysicalAddress(uint32_t PAddr, uint32_t Value);
bool SW_PhysicalAddress(uint32_t PAddr, uint32_t Value);
bool SD_PhysicalAddress(uint32_t PAddr, uint64_t Value);
#if defined(__i386__) || defined(_M_IX86)

1
Source/Project64-core/N64System/Recompiler/Recompiler.cpp
View File

@ -202,7 +202,6 @@ void CRecompiler::RecompilerMain_Lookup_validate()
WriteTrace(TraceRecompiler, TraceInfo, "Start");
bool & Done = m_EndEmulation;
uint32_t & PC = PROGRAM_COUNTER;
uint32_t PhysicalAddr;
while (!Done)

38
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -3337,8 +3337,8 @@ void CX86RecompilerOps::LW_KnownAddress(const asmjit::x86::Gp & Reg, uint32_t VA
default:
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.PushImm32("m_TempValue32", (uint32_t)&m_TempValue32);
m_Assembler.push(PAddr | 0xA0000000);
m_Assembler.CallThis((uint32_t)(g_MMU), AddressOf(&CMipsMemoryVM::LW_NonMemory), "CMipsMemoryVM::LW_NonMemory", 12);
m_Assembler.push(PAddr);
m_Assembler.CallThis((uint32_t)(g_MMU), AddressOf(&CMipsMemoryVM::LW_PhysicalAddress), "CMipsMemoryVM::LW_PhysicalAddress", 12);
m_RegWorkingSet.AfterCallDirect();
m_Assembler.MoveVariableToX86reg(Reg, &m_TempValue32, "m_TempValue32");
break;
@ -3348,8 +3348,8 @@ void CX86RecompilerOps::LW_KnownAddress(const asmjit::x86::Gp & Reg, uint32_t VA
case 0x04100000:
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.PushImm32("m_TempValue32", (uint32_t)&m_TempValue32);
m_Assembler.push(PAddr | 0xA0000000);
m_Assembler.CallThis((uint32_t)(g_MMU), AddressOf(&CMipsMemoryVM::LW_NonMemory), "CMipsMemoryVM::LW_NonMemory", 12);
m_Assembler.push(PAddr);
m_Assembler.CallThis((uint32_t)(g_MMU), AddressOf(&CMipsMemoryVM::LW_PhysicalAddress), "CMipsMemoryVM::LW_PhysicalAddress", 12);
m_RegWorkingSet.AfterCallDirect();
m_Assembler.MoveVariableToX86reg(Reg, &m_TempValue32, "m_TempValue32");
break;
@ -9915,7 +9915,7 @@ void CX86RecompilerOps::CompileLoadMemoryValue(asmjit::x86::Gp AddressReg, asmji
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.PushImm32("m_TempValue32", (uint32_t)&m_TempValue32);
m_Assembler.push(AddressReg);
m_Assembler.CallThis((uint32_t)(&m_MMU), AddressOf(&CMipsMemoryVM::LW_NonMemory), "CMipsMemoryVM::LW_NonMemory", 12);
m_Assembler.CallThis((uint32_t)(&m_MMU), AddressOf(&CMipsMemoryVM::LW_VAddr32), "CMipsMemoryVM::LW_VAddr32", 12);
m_Assembler.test(asmjit::x86::al, asmjit::x86::al);
m_RegWorkingSet.AfterCallDirect();
CompileExit((uint32_t)-1, (uint32_t)-1, m_RegWorkingSet, ExitReason_NormalNoSysCheck, false, &CX86Ops::JeLabel);
@ -9927,7 +9927,7 @@ void CX86RecompilerOps::CompileLoadMemoryValue(asmjit::x86::Gp AddressReg, asmji
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.PushImm32("m_TempValue32", (uint32_t)&m_TempValue32);
m_Assembler.push(AddressReg);
m_Assembler.CallThis((uint32_t)(&m_MMU), AddressOf(&CMipsMemoryVM::LH_NonMemory), "CMipsMemoryVM::LH_NonMemory", 12);
m_Assembler.CallThis((uint32_t)(&m_MMU), AddressOf(&CMipsMemoryVM::LH_VAddr32), "CMipsMemoryVM::LH_VAddr32", 12);
m_Assembler.test(asmjit::x86::al, asmjit::x86::al);
m_RegWorkingSet.AfterCallDirect();
CompileExit((uint32_t)-1, (uint32_t)-1, m_RegWorkingSet, ExitReason_NormalNoSysCheck, false, &CX86Ops::JeLabel);
@ -9940,7 +9940,7 @@ void CX86RecompilerOps::CompileLoadMemoryValue(asmjit::x86::Gp AddressReg, asmji
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.PushImm32("m_TempValue32", (uint32_t)&m_TempValue32);
m_Assembler.push(AddressReg);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::LB_NonMemory), "CMipsMemoryVM::LB_NonMemory", 12);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::LB_VAddr32), "CMipsMemoryVM::LB_VAddr32", 12);
m_Assembler.test(asmjit::x86::al, asmjit::x86::al);
m_RegWorkingSet.AfterCallDirect();
CompileExit((uint32_t)-1, (uint32_t)-1, m_RegWorkingSet, ExitReason_NormalNoSysCheck, false, &CX86Ops::JeLabel);
@ -10095,7 +10095,7 @@ void CX86RecompilerOps::CompileStoreMemoryValue(asmjit::x86::Gp AddressReg, asmj
m_Assembler.push(ValueReg);
}
m_Assembler.push(AddressReg);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::SB_NonMemory), "CMipsMemoryVM::SB_NonMemory", 12);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::SB_VAddr32), "CMipsMemoryVM::SB_VAddr32", 12);
if (OpsExecuted != 0)
{
m_Assembler.AddConstToVariable(g_NextTimer, "g_NextTimer", OpsExecuted);
@ -10122,7 +10122,7 @@ void CX86RecompilerOps::CompileStoreMemoryValue(asmjit::x86::Gp AddressReg, asmj
m_Assembler.push(ValueReg);
}
m_Assembler.push(AddressReg);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::SH_NonMemory), "CMipsMemoryVM::SH_NonMemory", 12);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::SH_VAddr32), "CMipsMemoryVM::SH_VAddr32", 12);
if (OpsExecuted != 0)
{
m_Assembler.AddConstToVariable(g_NextTimer, "g_NextTimer", OpsExecuted);
@ -10149,7 +10149,7 @@ void CX86RecompilerOps::CompileStoreMemoryValue(asmjit::x86::Gp AddressReg, asmj
m_Assembler.push(ValueReg);
}
m_Assembler.push(AddressReg);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory", 12);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::SW_VAddr32), "CMipsMemoryVM::SW_VAddr32", 12);
if (OpsExecuted != 0)
{
m_Assembler.AddConstToVariable(g_NextTimer, "g_NextTimer", OpsExecuted);
@ -10178,7 +10178,7 @@ void CX86RecompilerOps::CompileStoreMemoryValue(asmjit::x86::Gp AddressReg, asmj
m_Assembler.push(ValueRegHi);
}
m_Assembler.push(AddressReg);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::SD_NonMemory), "CMipsMemoryVM::SD_NonMemory", 12);
m_Assembler.CallThis((uint32_t)&m_MMU, AddressOf(&CMipsMemoryVM::SD_VAddr32), "CMipsMemoryVM::SD_VAddr32", 12);
if (OpsExecuted != 0)
{
m_Assembler.AddConstToVariable(g_NextTimer, "g_NextTimer", OpsExecuted);
@ -10615,8 +10615,8 @@ void CX86RecompilerOps::SW_Const(uint32_t Value, uint32_t VAddr)
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.push(Value);
m_Assembler.push(PAddr | 0xA0000000);
m_Assembler.CallThis((uint32_t)g_MMU, AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory", 12);
m_Assembler.push(PAddr);
m_Assembler.CallThis((uint32_t)g_MMU, AddressOf(&CMipsMemoryVM::SW_PhysicalAddress), "CMipsMemoryVM::SW_PhysicalAddress", 12);
m_RegWorkingSet.AfterCallDirect();
break;
case 0x0404001C: m_Assembler.MoveConstToVariable(&g_Reg->SP_SEMAPHORE_REG, "SP_SEMAPHORE_REG", 0); break;
@ -10635,8 +10635,8 @@ void CX86RecompilerOps::SW_Const(uint32_t Value, uint32_t VAddr)
case 0x0410000C:
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.push(Value);
m_Assembler.push(PAddr | 0xA0000000);
m_Assembler.CallThis((uint32_t)g_MMU, AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory", 12);
m_Assembler.push(PAddr);
m_Assembler.CallThis((uint32_t)g_MMU, AddressOf(&CMipsMemoryVM::SW_PhysicalAddress), "CMipsMemoryVM::SW_PhysicalAddress", 12);
m_RegWorkingSet.AfterCallDirect();
break;
default:
@ -10972,8 +10972,8 @@ void CX86RecompilerOps::SW_Const(uint32_t Value, uint32_t VAddr)
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.push(Value);
m_Assembler.push(PAddr | 0xA0000000);
m_Assembler.CallThis((uint32_t)(g_MMU), AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory", 12);
m_Assembler.push(PAddr);
m_Assembler.CallThis((uint32_t)(g_MMU), AddressOf(&CMipsMemoryVM::SW_PhysicalAddress), "CMipsMemoryVM::SW_PhysicalAddress", 12);
m_RegWorkingSet.AfterCallDirect();
}
}
@ -11079,8 +11079,8 @@ void CX86RecompilerOps::SW_Register(const asmjit::x86::Gp & Reg, uint32_t VAddr)
}
m_RegWorkingSet.BeforeCallDirect();
m_Assembler.push(Reg);
m_Assembler.push(PAddr | 0xA0000000);
m_Assembler.CallThis((uint32_t)(g_MMU), AddressOf(&CMipsMemoryVM::SW_NonMemory), "CMipsMemoryVM::SW_NonMemory", 12);
m_Assembler.push(PAddr);
m_Assembler.CallThis((uint32_t)(g_MMU), AddressOf(&CMipsMemoryVM::SW_PhysicalAddress), "CMipsMemoryVM::SW_PhysicalAddress", 12);
m_RegWorkingSet.AfterCallDirect();
break;
case 0x04300000: