Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
This commit is contained in:
parent
8b14b6d7d1
commit
ae4af8746b
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@ -69,7 +69,7 @@ void CInterpreterCPU::ExecuteCPU()
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{
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if (!g_MMU->MemoryValue32(PROGRAM_COUNTER, Opcode.Value))
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{
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g_Reg->DoTLBReadMiss(PipelineStage == PIPELINE_STAGE_JUMP, PROGRAM_COUNTER);
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g_Reg->DoTLBReadMiss(PROGRAM_COUNTER);
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PROGRAM_COUNTER = JumpToLocation;
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PipelineStage = PIPELINE_STAGE_NORMAL;
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continue;
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@ -133,7 +133,7 @@ void CInterpreterCPU::ExecuteCPU()
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PipelineStage = PIPELINE_STAGE_NORMAL;
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if ((PROGRAM_COUNTER & 0x3) != 0)
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{
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GenerateAddressErrorException((int32_t)JumpToLocation, true);
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g_Reg->DoAddressError((int32_t)JumpToLocation, true);
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PROGRAM_COUNTER = JumpToLocation;
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PipelineStage = PIPELINE_STAGE_NORMAL;
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}
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@ -281,7 +281,7 @@ void CInterpreterCPU::ExecuteOps(int32_t Cycles)
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}
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else
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{
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g_Reg->DoTLBReadMiss(PipelineStage == PIPELINE_STAGE_JUMP, PROGRAM_COUNTER);
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g_Reg->DoTLBReadMiss(PROGRAM_COUNTER);
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PROGRAM_COUNTER = JumpToLocation;
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PipelineStage = PIPELINE_STAGE_NORMAL;
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}
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@ -1091,7 +1091,7 @@ void R4300iOp::SWL()
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}
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else
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{
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GenerateTLBWriteException(Address, __FUNCTION__);
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g_Reg->DoTLBWriteMiss(Address);
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}
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}
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@ -1124,7 +1124,7 @@ void R4300iOp::SDL()
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}
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else
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{
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GenerateTLBWriteException(Address, __FUNCTION__);
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g_Reg->DoTLBWriteMiss(Address);
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}
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}
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@ -1152,7 +1152,7 @@ void R4300iOp::SDR()
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}
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else
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{
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GenerateTLBWriteException(Address, __FUNCTION__);
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g_Reg->DoTLBWriteMiss(Address);
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}
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}
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@ -1170,7 +1170,7 @@ void R4300iOp::SWR()
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}
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else
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{
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GenerateTLBWriteException(Address, __FUNCTION__);
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g_Reg->DoTLBWriteMiss(Address);
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}
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}
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@ -3043,31 +3043,6 @@ bool R4300iOp::MemoryBreakpoint()
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return false;
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}
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void R4300iOp::GenerateAddressErrorException(uint64_t VAddr, bool FromRead)
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{
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g_Reg->DoAddressError(VAddr, FromRead);
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}
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void R4300iOp::GenerateTLBReadException(uint64_t VAddr, const char * function)
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{
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if (bShowTLBMisses())
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{
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g_Notify->DisplayError(stdstr_f("%s TLB: %X", function, (uint32_t)VAddr).c_str());
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}
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g_Reg->DoTLBReadMiss(g_System->m_PipelineStage == PIPELINE_STAGE_JUMP, VAddr);
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}
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void R4300iOp::GenerateTLBWriteException(uint64_t VAddr, const char * function)
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{
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if (bShowTLBMisses())
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{
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g_Notify->DisplayError(stdstr_f("%s TLB: %X", function, (uint32_t)VAddr).c_str());
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}
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g_Reg->DoTLBWriteMiss(g_System->m_PipelineStage == PIPELINE_STAGE_JUMP, VAddr);
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g_System->m_PipelineStage = PIPELINE_STAGE_JUMP;
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g_System->m_JumpToLocation = (*_PROGRAM_COUNTER);
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}
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bool R4300iOp::TestCop1UsableException(void)
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{
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if (g_Reg->STATUS_REGISTER.CU1 == 0)
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@ -260,9 +260,6 @@ protected:
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static Func Jump_CoP1_L[64];
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static Func Jump_CoP2[32];
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static void GenerateAddressErrorException(uint64_t VAddr, bool FromRead);
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static void GenerateTLBReadException(uint64_t VAddr, const char * function);
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static void GenerateTLBWriteException(uint64_t VAddr, const char * function);
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static bool TestCop1UsableException(void);
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static bool CheckFPUInput32(const float & Value);
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static bool CheckFPUInput32Conv(const float & Value);
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@ -365,7 +365,7 @@ bool CMipsMemoryVM::LB_Memory(uint64_t VAddr, uint8_t & Value)
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{
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if (!b32BitCore() && (uint64_t)((int32_t)VAddr) != VAddr)
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{
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GenerateAddressErrorException(VAddr, true);
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m_Reg.DoAddressError(VAddr, true);
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return false;
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}
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uint32_t VAddr32 = (uint32_t)VAddr;
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@ -387,14 +387,14 @@ bool CMipsMemoryVM::LH_Memory(uint64_t VAddr, uint16_t & Value)
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{
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if (!b32BitCore() && (uint64_t)((int32_t)VAddr) != VAddr)
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{
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GenerateAddressErrorException(VAddr, true);
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m_Reg.DoAddressError(VAddr, true);
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return false;
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}
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uint32_t VAddr32 = (uint32_t)VAddr;
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if ((VAddr32 & 1) != 0)
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{
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GenerateAddressErrorException(VAddr, true);
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m_Reg.DoAddressError(VAddr, true);
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return false;
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}
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if (HaveReadBP() && g_Debugger->ReadBP16(VAddr32) && MemoryBreakpoint())
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@ -414,13 +414,13 @@ bool CMipsMemoryVM::LW_Memory(uint64_t VAddr, uint32_t & Value)
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{
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if (!b32BitCore() && (uint64_t)((int32_t)VAddr) != VAddr)
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{
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GenerateAddressErrorException(VAddr, true);
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m_Reg.DoAddressError(VAddr, true);
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return false;
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}
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uint32_t VAddr32 = (uint32_t)VAddr;
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if ((VAddr32 & 3) != 0)
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{
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GenerateAddressErrorException(VAddr, true);
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m_Reg.DoAddressError(VAddr, true);
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return false;
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}
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if (HaveReadBP() && g_Debugger->ReadBP32(VAddr32) && MemoryBreakpoint())
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@ -436,7 +436,7 @@ bool CMipsMemoryVM::LW_Memory(uint64_t VAddr, uint32_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr32 >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBReadException(VAddr, __FUNCTION__);
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m_Reg.DoTLBReadMiss(VAddr);
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return false;
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}
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return LW_NonMemory(VAddr32, Value);
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@ -446,14 +446,14 @@ bool CMipsMemoryVM::LD_Memory(uint64_t VAddr, uint64_t & Value)
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{
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if (!b32BitCore() && (uint64_t)((int32_t)VAddr) != VAddr)
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{
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GenerateAddressErrorException(VAddr, true);
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m_Reg.DoAddressError(VAddr, true);
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return false;
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}
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uint32_t VAddr32 = (uint32_t)VAddr;
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if ((VAddr32 & 7) != 0)
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{
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GenerateAddressErrorException(VAddr, true);
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m_Reg.DoAddressError(VAddr, true);
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return false;
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}
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if (HaveReadBP() && g_Debugger->ReadBP64(VAddr32) && MemoryBreakpoint())
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@ -479,7 +479,7 @@ bool CMipsMemoryVM::SB_Memory(uint64_t VAddr, uint32_t Value)
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{
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if (!b32BitCore() && (uint64_t)((int32_t)VAddr) != VAddr)
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{
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GenerateAddressErrorException(VAddr, false);
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m_Reg.DoAddressError(VAddr, false);
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return false;
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}
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uint32_t VAddr32 = (uint32_t)VAddr;
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@ -501,14 +501,14 @@ bool CMipsMemoryVM::SH_Memory(uint64_t VAddr, uint32_t Value)
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{
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if (!b32BitCore() && (uint64_t)((int32_t)VAddr) != VAddr)
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{
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GenerateAddressErrorException(VAddr, false);
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m_Reg.DoAddressError(VAddr, false);
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return false;
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}
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uint32_t VAddr32 = (uint32_t)VAddr;
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if ((VAddr32 & 1) != 0)
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{
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GenerateAddressErrorException(VAddr, false);
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m_Reg.DoAddressError(VAddr, false);
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return false;
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}
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if (HaveWriteBP() && g_Debugger->WriteBP16(VAddr32) && MemoryBreakpoint())
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@ -528,14 +528,14 @@ bool CMipsMemoryVM::SW_Memory(uint64_t VAddr, uint32_t Value)
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{
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if (!b32BitCore() && (uint64_t)((int32_t)VAddr) != VAddr)
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{
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GenerateAddressErrorException(VAddr, false);
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m_Reg.DoAddressError(VAddr, false);
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return false;
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}
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uint32_t VAddr32 = (uint32_t)VAddr;
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if ((VAddr32 & 3) != 0)
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{
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GenerateAddressErrorException(VAddr, false);
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m_Reg.DoAddressError(VAddr, false);
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return false;
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}
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if (HaveWriteBP() && g_Debugger->WriteBP32(VAddr32) && MemoryBreakpoint())
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@ -555,14 +555,14 @@ bool CMipsMemoryVM::SD_Memory(uint64_t VAddr, uint64_t Value)
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{
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if (!b32BitCore() && (uint64_t)((int32_t)VAddr) != VAddr)
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{
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GenerateAddressErrorException(VAddr, false);
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m_Reg.DoAddressError(VAddr, false);
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return false;
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}
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uint32_t VAddr32 = (uint32_t)VAddr;
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if ((VAddr & 7) != 0)
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{
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GenerateAddressErrorException(VAddr, false);
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m_Reg.DoAddressError(VAddr, false);
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return false;
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}
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if (HaveWriteBP() && g_Debugger->WriteBP64(VAddr32) && MemoryBreakpoint())
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@ -600,7 +600,7 @@ bool CMipsMemoryVM::LB_NonMemory(uint32_t VAddr, uint8_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBReadException(VAddr, __FUNCTION__);
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m_Reg.DoTLBReadMiss(VAddr);
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return false;
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}
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@ -638,7 +638,7 @@ bool CMipsMemoryVM::LH_NonMemory(uint32_t VAddr, uint16_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBReadException(VAddr, __FUNCTION__);
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m_Reg.DoTLBReadMiss(VAddr);
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return false;
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}
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@ -676,7 +676,7 @@ bool CMipsMemoryVM::LW_NonMemory(uint32_t VAddr, uint32_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBReadException(VAddr, __FUNCTION__);
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m_Reg.DoTLBReadMiss(VAddr);
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return false;
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}
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uint32_t PAddr = BaseAddress + VAddr;
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@ -720,7 +720,7 @@ bool CMipsMemoryVM::LD_NonMemory(uint32_t VAddr, uint64_t & Value)
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uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBReadException(VAddr, __FUNCTION__);
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m_Reg.DoTLBReadMiss(VAddr);
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return false;
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}
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uint32_t PAddr = BaseAddress + VAddr;
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@ -740,7 +740,7 @@ bool CMipsMemoryVM::SB_NonMemory(uint32_t VAddr, uint32_t Value)
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uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBWriteException(VAddr, __FUNCTION__);
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m_Reg.DoTLBWriteMiss(VAddr);
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return false;
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}
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uint32_t PAddr = BaseAddress + VAddr;
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@ -781,7 +781,7 @@ bool CMipsMemoryVM::SH_NonMemory(uint32_t VAddr, uint32_t Value)
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uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBWriteException(VAddr, __FUNCTION__);
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m_Reg.DoTLBWriteMiss(VAddr);
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return false;
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}
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uint32_t PAddr = BaseAddress + VAddr;
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@ -834,7 +834,7 @@ bool CMipsMemoryVM::SW_NonMemory(uint32_t VAddr, uint32_t Value)
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uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBWriteException((int64_t)((int32_t)VAddr), __FUNCTION__);
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m_Reg.DoTLBWriteMiss((int64_t)((int32_t)VAddr));
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return false;
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}
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uint32_t PAddr = BaseAddress + VAddr;
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@ -904,7 +904,7 @@ bool CMipsMemoryVM::SD_NonMemory(uint32_t VAddr, uint64_t Value)
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uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
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if (BaseAddress == -1)
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{
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GenerateTLBWriteException(VAddr, __FUNCTION__);
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m_Reg.DoTLBWriteMiss(VAddr);
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return false;
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}
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uint32_t PAddr = BaseAddress + VAddr;
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@ -806,7 +806,7 @@ bool CRegisters::DoIntrException()
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return true;
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}
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void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
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void CRegisters::DoTLBReadMiss(uint64_t BadVaddr)
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{
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CAUSE_REGISTER.ExceptionCode = EXC_RMISS;
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CAUSE_REGISTER.CoprocessorUnitNumber = 0;
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@ -815,7 +815,7 @@ void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
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ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
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if ((STATUS_REGISTER.ExceptionLevel) == 0)
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{
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if (DelaySlot)
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if (m_System.m_PipelineStage == PIPELINE_STAGE_JUMP)
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{
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CAUSE_REGISTER.BranchDelay = 1;
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EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
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@ -837,16 +837,12 @@ void CRegisters::DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr)
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}
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else
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{
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if (HaveDebugger())
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{
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g_Notify->DisplayError(stdstr_f("TLBMiss - EXL set\nBadVaddr = %X\nAddress defined: %s", (uint32_t)BadVaddr, g_TLB->AddressDefined((uint32_t)BadVaddr) ? "true" : "false").c_str());
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}
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m_System.m_JumpToLocation = 0x80000180;
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}
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m_System.m_PipelineStage = PIPELINE_STAGE_JUMP;
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}
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void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr)
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void CRegisters::DoTLBWriteMiss(uint64_t BadVaddr)
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{
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CAUSE_REGISTER.ExceptionCode = EXC_WMISS;
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CAUSE_REGISTER.CoprocessorUnitNumber = 0;
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@ -855,7 +851,7 @@ void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr)
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ENTRYHI_REGISTER = (BadVaddr & 0xFFFFE000);
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if ((STATUS_REGISTER.ExceptionLevel) == 0)
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{
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if (DelaySlot)
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if (g_System->m_PipelineStage == PIPELINE_STAGE_JUMP)
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{
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CAUSE_REGISTER.BranchDelay = 1;
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EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - 4);
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@ -867,25 +863,22 @@ void CRegisters::DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr)
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}
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if (g_TLB->AddressDefined((uint32_t)BadVaddr))
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{
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m_PROGRAM_COUNTER = 0x80000180;
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m_System.m_JumpToLocation = 0x80000180;
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}
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else
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{
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m_PROGRAM_COUNTER = 0x80000000;
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m_System.m_JumpToLocation = 0x80000000;
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}
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STATUS_REGISTER.ExceptionLevel = 1;
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}
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else
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{
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if (HaveDebugger())
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{
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g_Notify->DisplayError(stdstr_f("TLBMiss - EXL set\nBadVaddr = %X\nAddress defined: %s", (uint32_t)BadVaddr, g_TLB->AddressDefined((uint32_t)BadVaddr) ? "true" : "false").c_str());
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}
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m_PROGRAM_COUNTER = 0x80000180;
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m_System.m_JumpToLocation = 0x80000180;
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}
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m_System.m_PipelineStage = PIPELINE_STAGE_JUMP;
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}
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void CRegisters::TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor)
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void CRegisters::TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor, bool SpecialOffset)
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{
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if (GenerateLog() && LogExceptions())
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{
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@ -899,11 +892,29 @@ void CRegisters::TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor)
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}
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}
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uint32_t ExceptionBase = 0x80000000;
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uint16_t ExceptionOffset = 0x0180;
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if (SpecialOffset && STATUS_REGISTER.ExceptionLevel == 0)
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{
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switch (STATUS_REGISTER.PrivilegeMode)
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{
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case PrivilegeMode_Kernel:
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ExceptionOffset = STATUS_REGISTER.KernelExtendedAddressing == 0 ? 0x0000 : 0x0080;
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break;
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case PrivilegeMode_Supervisor:
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ExceptionOffset = STATUS_REGISTER.SupervisorExtendedAddressing == 0 ? 0x0000 : 0x0080;
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break;
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case PrivilegeMode_User:
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ExceptionOffset = STATUS_REGISTER.UserExtendedAddressing == 0 ? 0x0000 : 0x0080;
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break;
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}
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}
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CAUSE_REGISTER.ExceptionCode = ExceptionCode;
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CAUSE_REGISTER.CoprocessorUnitNumber = Coprocessor;
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CAUSE_REGISTER.BranchDelay = m_System.m_PipelineStage == PIPELINE_STAGE_JUMP;
|
||||
EPC_REGISTER = (int64_t)((int32_t)m_PROGRAM_COUNTER - (CAUSE_REGISTER.BranchDelay ? 4 : 0));
|
||||
STATUS_REGISTER.ExceptionLevel = 1;
|
||||
m_System.m_PipelineStage = PIPELINE_STAGE_JUMP;
|
||||
m_System.m_JumpToLocation = 0x80000180;
|
||||
m_System.m_JumpToLocation = ExceptionBase | ExceptionOffset;
|
||||
}
|
|
@ -453,12 +453,12 @@ public:
|
|||
void CheckInterrupts();
|
||||
void DoAddressError(uint64_t BadVaddr, bool FromRead);
|
||||
bool DoIntrException();
|
||||
void DoTLBReadMiss(bool DelaySlot, uint64_t BadVaddr);
|
||||
void DoTLBWriteMiss(bool DelaySlot, uint64_t BadVaddr);
|
||||
void DoTLBReadMiss(uint64_t BadVaddr);
|
||||
void DoTLBWriteMiss(uint64_t BadVaddr);
|
||||
void FixFpuLocations();
|
||||
void Reset(bool bPostPif, CMipsMemoryVM & MMU);
|
||||
void SetAsCurrentSystem();
|
||||
void TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor = 0);
|
||||
void TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor = 0, bool SpecialOffset = false);
|
||||
|
||||
uint64_t Cop0_MF(COP0Reg Reg);
|
||||
void Cop0_MT(COP0Reg Reg, uint64_t Value);
|
||||
|
|
|
@ -87,7 +87,7 @@ void CRecompiler::RecompilerMain_VirtualTable()
|
|||
{
|
||||
if (!m_MMU.ValidVaddr(PC))
|
||||
{
|
||||
m_Registers.DoTLBReadMiss(false, PC);
|
||||
m_Registers.DoTLBReadMiss(PC);
|
||||
PC = g_System->m_JumpToLocation;
|
||||
g_System->m_PipelineStage = PIPELINE_STAGE_NORMAL;
|
||||
if (!m_MMU.ValidVaddr(PC))
|
||||
|
@ -149,7 +149,7 @@ void CRecompiler::RecompilerMain_Lookup()
|
|||
{
|
||||
if (!m_MMU.VAddrToPAddr(PROGRAM_COUNTER, PhysicalAddr))
|
||||
{
|
||||
m_Registers.DoTLBReadMiss(false, PROGRAM_COUNTER);
|
||||
m_Registers.DoTLBReadMiss(PROGRAM_COUNTER);
|
||||
if (!m_MMU.VAddrToPAddr(PROGRAM_COUNTER, PhysicalAddr))
|
||||
{
|
||||
g_Notify->DisplayError(stdstr_f("Failed to translate PC to a PAddr: %X\n\nEmulation stopped", PROGRAM_COUNTER).c_str());
|
||||
|
@ -209,7 +209,7 @@ void CRecompiler::RecompilerMain_Lookup_validate()
|
|||
{
|
||||
if (!m_MMU.VAddrToPAddr(PC, PhysicalAddr))
|
||||
{
|
||||
m_Registers.DoTLBReadMiss(false, PC);
|
||||
m_Registers.DoTLBReadMiss(PC);
|
||||
if (!m_MMU.VAddrToPAddr(PC, PhysicalAddr))
|
||||
{
|
||||
g_Notify->DisplayError(stdstr_f("Failed to translate PC to a PAddr: %X\n\nEmulation stopped", PC).c_str());
|
||||
|
|
|
@ -50,7 +50,7 @@ void CX86RecompilerOps::x86CompilerBreakPoint()
|
|||
uint32_t OpcodeValue;
|
||||
if (!g_MMU->MemoryValue32(g_Reg->m_PROGRAM_COUNTER, OpcodeValue))
|
||||
{
|
||||
g_Reg->DoTLBReadMiss(false, g_Reg->m_PROGRAM_COUNTER);
|
||||
g_Reg->DoTLBReadMiss(g_Reg->m_PROGRAM_COUNTER);
|
||||
g_Reg->m_PROGRAM_COUNTER = g_System->JumpToLocation();
|
||||
g_System->m_PipelineStage = PIPELINE_STAGE_NORMAL;
|
||||
continue;
|
||||
|
@ -9693,9 +9693,9 @@ void CX86RecompilerOps::CompileExit(uint32_t JumpPC, uint32_t TargetPC, CRegInfo
|
|||
ExitCodeBlock();
|
||||
break;
|
||||
case ExitReason_TLBReadMiss:
|
||||
m_Assembler.MoveConstToVariable(&g_System->m_PipelineStage, "System->m_PipelineStage", InDelaySlot ? PIPELINE_STAGE_JUMP : PIPELINE_STAGE_NORMAL);
|
||||
m_Assembler.MoveVariableToX86reg(asmjit::x86::edx, g_TLBLoadAddress, "g_TLBLoadAddress");
|
||||
m_Assembler.push(asmjit::x86::edx);
|
||||
m_Assembler.PushImm32(InDelaySlot ? "true" : "false", InDelaySlot);
|
||||
m_Assembler.CallThis((uint32_t)g_Reg, AddressOf(&CRegisters::DoTLBReadMiss), "CRegisters::DoTLBReadMiss", 12);
|
||||
m_Assembler.MoveVariableToX86reg(asmjit::x86::edx, &g_System->m_JumpToLocation, "System->m_JumpToLocation");
|
||||
m_Assembler.MoveX86regToVariable(&g_Reg->m_PROGRAM_COUNTER, "PROGRAM_COUNTER", asmjit::x86::edx);
|
||||
|
|
|
@ -12,7 +12,6 @@ bool CDebugSettings::m_Stepping = false;
|
|||
bool CDebugSettings::m_SkipOp = false;
|
||||
bool CDebugSettings::m_WaitingForStep = false;
|
||||
bool CDebugSettings::m_bRecordRecompilerAsm = false;
|
||||
bool CDebugSettings::m_bShowTLBMisses = false;
|
||||
bool CDebugSettings::m_RecordExecutionTimes = false;
|
||||
bool CDebugSettings::m_HaveExecutionBP = false;
|
||||
bool CDebugSettings::m_HaveWriteBP = false;
|
||||
|
|
|
@ -32,10 +32,6 @@ public:
|
|||
{
|
||||
return m_bRecordRecompilerAsm;
|
||||
}
|
||||
static inline bool bShowTLBMisses(void)
|
||||
{
|
||||
return m_bShowTLBMisses;
|
||||
}
|
||||
static inline bool bRecordExecutionTimes(void)
|
||||
{
|
||||
return m_RecordExecutionTimes;
|
||||
|
@ -111,7 +107,6 @@ private:
|
|||
static bool m_SkipOp;
|
||||
static bool m_WaitingForStep;
|
||||
static bool m_bRecordRecompilerAsm;
|
||||
static bool m_bShowTLBMisses;
|
||||
static bool m_RecordExecutionTimes;
|
||||
static bool m_HaveExecutionBP;
|
||||
static bool m_HaveWriteBP;
|
||||
|
|
Loading…
Reference in New Issue