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185 Commits

Author SHA1 Message Date
Lior Halphon ce80acc818 Fixed HDMA timing )But still not verified) 2018-07-20 12:34:52 +03:00
Lior Halphon b7b35c9b59 CGB-C timing 2018-07-03 22:25:09 +03:00
Lior Halphon 0a78f735d3 Fetcher Y is not cached on CGB-C 2018-07-03 22:14:53 +03:00
Lior Halphon 18ae18a95c LYC bit on CGB-C 2018-07-03 21:56:32 +03:00
Lior Halphon 6a7c084177 Fixed window regression 2018-06-18 21:57:01 +03:00
Lior Halphon 45c73e0175 Replaced the is_cgb bool with a more future compatible model enum. Removed the GB_init_cgb API and replaced it with an extended GB_init and GB_switch_model_and_reset APIs that now receive a model parameter. Increased the struct version. 2018-06-16 13:59:33 +03:00
Lior Halphon ca01ff6f79 Finally, perfect emulation of the STAT write bug. 2018-06-08 17:16:15 +03:00
Lior Halphon 127324d2d6 Fixed regression involving rendering a window with negative X position. Closes #75 2018-06-07 23:08:46 +03:00
Lior Halphon f1dfa2a1bc More sensible implementation of the STAT interrupt. 2018-06-04 02:07:38 +03:00
Lior Halphon 8721a48206 Fixed incorrect double speed behavior. 2018-06-03 00:36:05 +03:00
Lior Halphon 7003e31b7e Fixed a regression with STAT blocking. 2018-06-02 04:00:10 +03:00
Lior Halphon 9693b2de6a Refined the STAT bug behavior. Still not perfect. 2018-05-26 17:06:49 +03:00
Lior Halphon 855ffb490a A HBlank interrupt cannot occur in the last M-cycle of HBlank. Correct emulation of STAT access conflicts on the CGB (Test: CPU-E, single speed only). Fixes a minor graphical glitch in Pokémon Puzzle Challenge. 2018-05-25 23:42:36 +03:00
Lior Halphon 713dc02e46 A bit tacky, but T-cycle accurate emulation of LYC write conflicts on the CGB. Only single speed mode verified. Closes #54 2018-05-11 12:38:55 +03:00
Lior Halphon af3554c1d1 More accurate emulation of the LYC register and interrupt. (Still not perfect on a CGB) 2018-04-27 13:40:39 +03:00
Lior Halphon 0f8385a798 Refined line 153 behavior on a CGB. Verified on CGB-E. 2018-04-25 00:08:06 +03:00
Lior Halphon 5be2b3db29 It appears that OAM DMA blocks PPU access to OAM 2018-04-07 13:59:36 +03:00
Lior Halphon 0725b008be Further simplifications 2018-04-07 13:02:53 +03:00
Lior Halphon 097b768127 Update comments 2018-04-07 03:36:47 +03:00
Lior Halphon 9ce028056a Cleanup 2018-04-07 03:26:10 +03:00
Lior Halphon fed2556fc3 More reasonable implementation of sprite timings 2018-04-07 03:00:26 +03:00
Lior Halphon 0751eae90b Moved the fetcher state machine to another function 2018-04-06 19:29:49 +03:00
Lior Halphon 0461fb5b2a Simplified FIFO logic 2018-04-06 19:11:48 +03:00
Lior Halphon cb01259073 Fixed #61 2018-04-06 11:37:49 +03:00
Lior Halphon a6ed2029b7 New information about PPU changes between CGB-B and CGB-E 2018-04-06 03:19:47 +03:00
Lior Halphon cc95c89d3c Surprise! The CGB has a 16-bit VRAM data bus 2018-04-05 16:15:51 +03:00
Lior Halphon 9aadc80f75 Implemented some obscure PPU rendering quirks, verified some timings 2018-04-05 15:33:21 +03:00
Lior Halphon d785e45308 More accurate emulation of LCDC.0 2018-04-05 12:27:01 +03:00
Lior Halphon d8e0683c35 Fixed a bug where skipping a sprite by modifying LCDC flags mid-scanline will disable sprites for the rest of the scalene. 2018-04-05 00:51:37 +03:00
Lior Halphon 5d63892949 T-cycle accurate timing of the extra OAM interrupt. Fixes vblank_stat_intr-GS, related to #54 2018-04-03 01:43:24 +03:00
Lior Halphon e163026ca9 The STAT bug does not occur during the glitched mode 0 2018-04-02 01:05:32 +03:00
Lior Halphon 9339a6027f Slight refinement to the last fix 2018-04-01 22:20:26 +03:00
Lior Halphon ec64c041ab The OAM interrupt is internally implemented differently from the other 3. Fixed the stat_write_if tests, relates to #54 2018-04-01 21:45:56 +03:00
Lior Halphon 73dc3560a5 Mode 0 interrupts do not occur in the glitched mode 0 of the first line 0. The extra OAM interrupt bug also affects DMG. 2018-03-31 13:18:02 +03:00
Lior Halphon 0a2d6e6dcb Fixed DMG timing regression 2018-03-31 12:21:34 +03:00
Lior Halphon 9811dceca1 Emulate another OAM timing quirk; a sprite at x = 0 has extra penalty if SCX is not 0. Fixes intr_2_mode0_timing_sprites_scx*_nops, affects #54 2018-03-30 17:06:27 +03:00
Lior Halphon 2c44ffbe39 More accurate fetcher penalty emulation, fixed intr_2_mode0_timing_sprites_nops, affects #54 2018-03-30 02:53:49 +03:00
Kyle Swanson 7bfe5de9c7 chmod -x 2018-03-28 21:37:34 -07:00
Lior Halphon 0e3d2770d9 Properly handle cases where an object’s X position is modified between the OAM mode and rendering mode 2018-03-27 22:13:08 +03:00
Lior Halphon 4986930511 Mostly complete emulation of the OAM bug. Passes oam_bug-2. 2018-03-27 15:46:00 +03:00
Lior Halphon 5cb74fb684 Bugfix: turning the PPU off during OAM mode made the OAM bug persist while the LCD is off 2018-03-24 02:58:37 +03:00
Lior Halphon 4e3928df81 Turns out the behavior differs between DMG and CGB – in DMG mode, the objects enabled bit is checked before halting the FIFOs, meaning that disabled sprites do not affect Mode 3’s length on the DMG. 2018-03-23 20:01:27 +03:00
Lior Halphon 48a8db233d Refinement to the last fix 2018-03-23 19:54:11 +03:00
Lior Halphon e9eeace995 The object enabled bit is checked only when popping from the object FIFO. Objects affect timing even when disabled. 2018-03-23 19:50:19 +03:00
Lior Halphon 04bfc89816 Cycle accurate OAM search mode 2018-03-23 19:07:14 +03:00
Lior Halphon c11af7ea26 Fix CGB timings 2018-03-23 12:58:51 +03:00
Lior Halphon e9f243a913 Fix sprite priority 2018-03-21 00:02:35 +02:00
Lior Halphon cb33a5b25a Fix Aevilla 2018-03-20 20:08:29 +02:00
Lior Halphon 3883b7d86a Merge branch 'master' into timing 
# Conflicts:
#	Core/display.c
#	Core/z80_cpu.c
 2018-03-19 23:46:33 +02:00
Lior Halphon b50c97f4a7 Prevent starting HDMA in the middle of an instruction, making both the CPU and DMA access memory at the same time. Closes #47 2018-03-19 20:01:31 +02:00
Lior Halphon 202eb2b5cc Fix stat_lyc_onoff 2018-03-18 20:32:19 +02:00
Lior Halphon 80b1275e07 Fix stat_lyc_onoff 2018-03-18 20:08:45 +02:00
Lior Halphon 12ae5745db While fixing some rendering issues, this change was incorrect. 2018-03-17 21:04:48 +02:00
Lior Halphon 269bac4626 More CGB fixes 2018-03-17 20:34:55 +02:00
Lior Halphon 21b75494a2 More CGB fixes (currently on DMG-mode CGB is verified). Halt interrupt timing isn’t correct yet. 2018-03-11 00:17:57 +02:00
Lior Halphon 15b6c48d7c Fixed vblank_stat_intr-C 2018-03-10 15:52:22 +02:00
Lior Halphon c267ad00b5 Goodbye 2018-03-09 23:34:23 +02:00
Lior Halphon e8b107efdb In double speed mode, there are no quirks where IF and STAT don’t update together 2018-03-09 23:31:49 +02:00
Lior Halphon cb6bb0590e Starting to fix CGB timing quirks 2018-03-09 21:11:35 +02:00
Lior Halphon 9083e883fe CGB BG rendering 2018-03-09 18:52:36 +02:00
Lior Halphon a32f232bb1 Fixed OAM-window priority glitch, fixed OAM glitch in Prehistoric Man 2018-03-09 17:10:19 +02:00
Lior Halphon 1149c266cf More regression fixes, actually fix Pinball Deluxe this time 2018-03-08 23:22:03 +02:00
Lior Halphon 544ca2be4c Changing the timings of memory writes so they’re not effectively one T-cycle late. This screws up APU’s cycle accuracy for now. 2018-03-05 21:17:37 +02:00
Lior Halphon 88a11b891f Object rendering 2018-03-04 23:27:31 +02:00
Lior Halphon 3d1c8b50c4 OAM search and OAM timing in mode 3 2018-03-04 22:21:56 +02:00
Lior Halphon 476133abd0 The scrolled y value is cached and not recalculated 2018-03-03 20:51:38 +02:00
Lior Halphon 518746f664 fixed rendering off by one 2018-03-03 19:52:48 +02:00
Lior Halphon 496c5589e6 Added window support 2018-03-03 19:36:21 +02:00
Lior Halphon 5ea33cc931 Cleanup 2018-03-03 19:05:29 +02:00
Lior Halphon b08f02c4f3 Rewriting the PPU rendering: T-cycle accurate background rendering. DMG only, CGB completely broken 2018-03-03 15:47:36 +02:00
Lior Halphon a67db0595b Fixed window behavior 2018-03-01 22:03:56 +02:00
Lior Halphon 7248403be7 Fixed several DMG regressions, fixes Pinball Deluxe again 2018-03-01 00:12:04 +02:00
Lior Halphon 90a943d05a Emulate an HDMA quirk required to properly emulate Aevilia 2018-02-25 22:32:41 +02:00
Lior Halphon ef670986c6 Rewrote PPU (currently only emulates DMG correctly) to use the new timing mechanism. Removed “future interrupts” (No longer required because SameBoy is now T-cycle based) 2018-02-25 00:48:45 +02:00
Lior Halphon 42ab746a66 Starting to remove the delayed interrupts hack – done for timer interrupt, broken for display interrupts 2018-02-23 15:33:44 +02:00
Lior Halphon 56eac9f875 Removed some dead code from display.c 2018-02-20 21:23:27 +02:00
Lior Halphon 9802ca41dd Components not affected by CGB’s double speed mode now operate in 8MHz mode to theoretically make advance_cycles(gb, 1) safe. 2018-02-20 21:17:12 +02:00
Lior Halphon 1c61b006ba Added rewinding support to the core and the Cocoa frontend 2018-02-10 14:42:14 +02:00
Lior Halphon f0e772ca97 Fixed: Loading states in DMG mode results in a black screen 2017-12-22 21:58:31 +02:00
Lior Halphon e71154b7e0 Fixed set_color_correction breaking DMG’s palette 2017-10-16 20:48:39 +03:00
Lior Halphon 65dd02cc52 Added 3 color correction profiles, added color correction setting to Cocoa GUI, improved cross-platform and cross-frontend save-state compatibility 2017-10-12 17:22:22 +03:00
Lior Halphon 7a41a9b417 Refined OAM interrupt timing. Fixes Pinball Deluxe in DMG mode; closes #1. 2017-09-23 21:08:05 +03:00
Lior Halphon 09b7e2fff4 Fixed a bug in scx_delay’s calculation 2017-09-11 23:56:35 +03:00
Lior Halphon 02841ddde6 Whoops 2017-09-09 16:55:55 +03:00
Lior Halphon 026baddbab Implemented delayed/future interrupts for DMG hblank interrupt. Restores vblank_stat_intr-GS support. 2017-09-09 13:45:01 +03:00
Lior Halphon 1e90400916 Reimplemented delayed/future interrupts, currently correct only for CGB. 2017-09-09 13:32:12 +03:00
Lior Halphon 742c9e95d3 Updated previous timing improvements to correctly implement double speed behavior 2017-09-08 23:46:38 +03:00
Lior Halphon e5d354e896 Refined SCX’s effects on PPU timing 2017-09-08 23:02:24 +03:00
Lior Halphon 0f1fa3176f Refinements to LCD timing (breaks vblank_stat_intr-GS for now) 2017-09-08 12:59:57 +03:00
Lior Halphon 0f643e01b7 Removing the delayed interrupt mechanism, research is not complete enough for implementation 2017-09-08 12:58:35 +03:00
Lior Halphon 9bde98dede SCY latching is now correctly emulated, rendering mode timing refined. 2017-09-04 15:45:18 +03:00
Lior Halphon a1a13c61bf On CGB, the VBlank and STAT interrupts are “delayed” by one T-cycle (relative to IF) since they’re not aligned to a T-Cycle 2017-09-03 00:41:52 +03:00
Lior Halphon 0532d2a159 A test ROM I wrote seems to contradicts some of AntonioND’s findings regrading PPU timing in CGB mode. CGB mode now behaves like DMG mode until I figure out what caused the difference. 2017-09-02 23:51:02 +03:00
Lior Halphon 9b490396bb Fixed timing when turning the LCD display on during double speed mode 2017-09-02 23:26:45 +03:00
Lior Halphon cbbaf2ee84 Refined Window behavior once more, Fixes #12 (While not breaking Donkey Kong or 007) 2017-08-20 01:34:12 +03:00
Lior Halphon 7df4e56454 KEY1 is only writable in CGB mode; screen should be black is LCD is on while in stop mode. 2017-08-12 21:42:47 +03:00
Lior Halphon c59272d46d Misc minor fixes, fixes several Mooneye-GB tests 2017-06-21 20:39:23 +03:00
Lior Halphon abf7efcc5a Fixed lcdon_write_timing. 2017-06-18 21:27:07 +03:00
Lior Halphon 86c9f9d89d Updated SameBoy to pass Mooneye-GB’s lcdon_timing test (on a DMG), as well as refined related CBG behaviors. 2017-06-17 22:17:58 +03:00
Lior Halphon a9475fbdf4 Refined the behavior of the last fix on a DMG. 2017-06-03 20:06:52 +03:00