Commit Graph

157 Commits

Author SHA1 Message Date
brandman211 3a56f65c3f Implemented the XXXR opcodes. As of now, I have Jump, MVO@, MVI@, and XORR enabled and tested. There might be an off by one error with MVO@. 2012-07-27 03:33:24 +00:00
brandman211 b96e014327 -Reverted disassembly printout as it'll now match up with my comparison.
-Fixed the branching disassembly; the direction just negates the offset and the second parameter only belongs to BEXT. All of my sources contradict each other, but this seems sensible.
2012-07-24 05:29:24 +00:00
brandman211 d469a4e568 -Put the disassembly in parenthesis and put the opcode to the left of it in the logs. This is uglier, but it's initially easier for comparison this way.
-RegisterSP now increments in MVO@ instead of decrements. I'm not sure how this allows the stack to function properly, but it seems to work.
2012-07-24 03:05:57 +00:00
brandman211 743480e26f -Logging now uses a static StreamWriter instead of building the string and writing on destruction.
-Applied to the old Gameboy core. Why not? It at least fixes that annoying bug from before if we ever care to use it again.
-Both logs are now written to different files.
2012-07-22 18:40:28 +00:00
brandman211 9f2bcf3318 -Fixed logging.
--It now just builds a strings and writes on finalization.
-Fixed up format strings.
-As RegisterPC already increments upon reading the third decle, I now just store PC as the return address for jumping instead of PC + 1.
2012-07-22 18:08:10 +00:00
brandman211 60c5a1ce58 Added logging for the CP1610. Not working for some reason. 2012-07-22 17:18:11 +00:00
brandman211 0a0763966c -Refactored of the executor / disassembler / Intellicart to use more descriptive variable names and types to clear up a lot of confusion.
-Added implementation for NOP (6 cycles of nothing).
-Made SWAP actually store the result (Still disabled).
-Added breaks to the swap / shift / rotate cases (Yikes).

Instruction disassembly:

JSRD R5, $1026
MVI@ R7, R6
JSR R5, $1A83
MVO@ R5, R6
MVO@ R0, R6
MVO@ R1, R6
MVI@ R7, R4
MVI@ R7, R0
JSR R5, $1738
MVO@ R5, R6
XORR R5, R5 <- Needs implementation.
2012-07-21 05:25:52 +00:00
brandman211 259ec356bd -Updated the disassembly based on a more accurate resource.
-Retrieved the double bit from the swap / shift / rotate instructions in a more proper way.

TODO: Use more specific variables; most of them suck, and with these docs, I have better names for them.
2012-07-20 23:06:59 +00:00
brandman211 610acf6ad6 -Made MVI@ and ADD@ follow the stack and immediate mode rules for incrementing / decrementing the SP / PC.
-Disabled Intellicart hook for ReadMemory, which seemed to be interfering.
-Implemented MVO@.
-Several instructions are now executed in succession until it hits the unimplemented "XORR R5, R5".

I should probably refactor Disassemble and Execute to label registers as source / destination to avoid further confusion at some point. My disassembly might have the source / destination registers flipped as well.
2012-07-20 07:22:41 +00:00
brandman211 b2323458ba Implemented / tested MVI@ and AND@.
-They both seem to work, but the operands for AND@ are both 0, so this seems fishy.
-I don't know for sure if AND@ executes cycles in the same way that MVI@ as the documentation isn't clear on this, but I assumed it did.

According to my disassembler, the first 5 instructions run on the Executive ROM are:

JSRD R5, $1026
MVI@ R7, R6
ADD@ R6, R1
JSR R5, $1A83
HLT

Considering that I hit a HLT, I figure something is going terribly wrong. Perhaps it has to do with my lack of an interrupt system?
2012-07-20 05:02:26 +00:00
brandman211 ab8e98c41a -Finished the disassembler with the branches.
-Added bytesToAdvance assignments to the relevant opcodes I added yesterday.

TODO: Implement more stuff in Execute and use the Executive ROM as a test case.
2012-07-20 03:30:03 +00:00
brandman211 10274734f9 -My jumping seems to work, so I enabled it in Execute.
-Finished the disassembler except for branching.
-Merged the XXXI instructions with XXX@ for R7 as the address register as they are redundant.
2012-07-19 06:58:14 +00:00
brandman211 e73c48219a -Loaded EROM / GROM.
-Fixed disassembly for JMP:
--Now it uses the parameter pc, not RegisterPC.
--I was loading both the second and third value from the second's address.
--Casting the calculated addresses to bytes when addresses are 16-bit was a bad idea.
--Removed a closing parenthesis I accidentally stuck in the formatting.

It seems that I've gotten far enough to use the Executive ROM as a test case! Now to go instruction by instruction and see if they work as planned and hope this will all eventually make something.
2012-07-19 00:05:08 +00:00
brandman211 32baa013af -Made the memory map use ushort arrays because the Intellivision is 16-bit.
-Fixed JMP disassembly; I need to return on an invalid opcode because I was breaking out of the inner switch statement, not both that and the outer one.
2012-07-09 23:19:57 +00:00
brandman211 9b8a9d93f1 Opcodes up to 0x07F. 2012-07-09 03:27:27 +00:00
brandman211 bb532aa2d9 Opcodes up to 0x5F. 2012-07-08 21:49:09 +00:00
brandman211 61cada6190 -Made HLT throw an exception.
-Made all instructions in the executor, even implemented ones, throw exceptions. I will get rid of the exceptions as I test the instructions.
-Added instructions up to and including 0x57 to disassembly and executor.
2012-07-08 19:52:12 +00:00
brandman211 a4912e66c0 -Wasn't supposed to actually increment the PC in the disassembler.
-Cleaned up the 0x004 (Jump) disassembler.
-Implemented 0x004 in the executor.
2012-07-08 08:42:32 +00:00
brandman211 778274a12d -Set up the disassembly decoder just like the executor.
-Disassembled opcodes up to and including 0x7.
2012-07-08 08:17:07 +00:00
brandman211 8d254113c2 Finished the opcode decoder. Over a thousand lines in one day...now just to make them do stuff! 2012-07-08 03:53:12 +00:00
brandman211 1c480c98b4 -Created functions for calculating the flags.
-Implemented ADCR.
-Decoded all opcodes up to 0x23F.

TODO: Try vecna's idea of testing the instructions by running a game and implementing instructions as I need them...but first I'll need to implement loading of an Intellivision game.
2012-07-08 01:58:06 +00:00
brandman211 2457c68ed7 Starting IntelliHawk with the CP1610, using the other processors in BizHawk, BlissJ, and this (http://wiki.intellivision.us/index.php?title=CP1610) page as references.
-Definitions.
--Registers, Flags, TotalExecutedCycles, PendingCycles, ReadMemory, and WriteMemory.
-Execute.
--Implemented opcodes 0x001-0x027 with the exception of 0x004 and 0x005.
2012-07-08 00:36:16 +00:00
brandman211 aad9f05310 -Made it so that the log file only opens when you're actually logging. As a result, now can now at least switch games when you're not logging without getting errors. 2012-05-24 17:27:45 +00:00
brandman211 b29c9835ff -Separated the logging from the save state function.
-Made it so that the log only opens when logging is true and that the file closes upon destruction.
--Still, BizHawk says that it can't open the file again when I load a game again. This is because the emulator class gets recreated without deleting the original one every time you load a game.
---adelikat convinced me not to care about this.
-Fixed the initial state of the GB CPU:
--It was setting AF to 0x01, not A. This is effectively setting F to 0x01, which gets overwritten later anyway.
--Two BIOS flags were used in different places; merging them gets the PC to start in the right place.
-By fixing the initial state, most of the log now matches up.
--The only differences are the VBA has some repeated records (Where all of the registers, including PC, are the same as the previous record) whereas BizHawk doesn't.
--This very well might be an issue with how I'm logging it
--Alternatively, it could be some kind of lagging mechanism.
--I'm not sure which version is even correct...VBA is far from accruate.
--All in all, considering that the vast majority of the diff comes out as the same, I think I fixed the biggest CPU related bug. Will investigate more later.
2012-05-24 17:19:33 +00:00
beirich 2aef2b8606 68000: savestate support (text) 2012-05-21 04:44:36 +00:00
brandman211 9623f073eb Added a logging flag for GB using the SaveStateText function. 2012-05-20 06:43:41 +00:00
beirich d322c3c00f Fix some bugs responsible for out-of-bounds array access crash on ym2612 2012-04-29 01:40:38 +00:00
zeromus b1d62ed574 6502-add some opcodes not handled by the instruction tests, but which are cursorily covered by the instr_timing test, which now passes 2012-04-18 08:04:06 +00:00
zeromus 97b66a907f 6502-implement undocumented opcodes. pass all instruction tests 2012-04-18 05:22:58 +00:00
zeromus d3321f552f nes accuracy fixes
- pass more apu_test 4-jitter and 6-irq_flag_timing (necessary for timing on other tests)
- pass all cpu interrupt tests
- pass all sprite hit tests
2012-03-25 09:25:27 +00:00
zeromus 0cf6b0bcb7 switch atari 2600 to new 6502 core 2012-03-24 03:45:47 +00:00
pjgat09 5e65c7e977 TIA: Removed code for cosmic ark starfield (to be added back later, in a cleaner way). Changed the definition of a frame to start with the first scanline where VSYNC is disabled.
MOS6507: Fixed a copy-paste mistake with SBC instructions where it would remove another cycle. This fixes the screen bounce issue with pitfall.
2012-03-20 22:45:15 +00:00
zeromus 471b3ffb98 nes-fix soft reset functionality which had got broken when i upgraded the cpu core 2012-03-18 03:46:06 +00:00
zeromus 2b21ca7127 add new, more detailed 6502X cpu core, use it in the nes core as experiment. win almost all the speed back, pass some more tests. 2012-03-15 21:28:37 +00:00
zeromus 20a242c27e sync mos6502 from my last core generator checkin 2012-03-15 20:40:50 +00:00
pjgat09 32bc215c2e MOS6507: Hacked in BCD mode (borrowed from HuC6280). Pitfall's time counter now works correctly 2012-03-14 16:03:14 +00:00
beirich ca47082737 fix some PCE savestate desyncs 2012-03-12 00:14:44 +00:00
pjgat09 23cb513188 MOS6507: adjusted for instructions with a variable cycle count 2012-03-11 07:08:48 +00:00
pjgat09 84a11eacdf Switched over to using the 6507 to allow for some modifications to the CPU
MOS6507: now executes instructions on the last cycle. This corrects a syncing issue with the TIA
TIA: added ball data, partially implemented HMOVE, implemented VBLANK
2012-03-11 03:22:44 +00:00
beirich bc2e7995cc clone 6502 into 6507 2012-03-11 03:09:43 +00:00
taotao54321 c6fcda4418 6502 disassembler: print the destination address of branch, not the offset 2012-03-10 19:10:12 +00:00
taotao54321 9ab33cba8b 6502: partially implemented unofficial NOPs for "Puzznic (U)", "Puzznic (J)".
It is quite insufficient, but at least, we have to increment program counter appropriately.
For immediate addressing mode, it will be correct. For other addressing modes, I don't know whether they access memory, so further investigation will be needed.
2012-03-08 16:48:36 +00:00
taotao54321 26ff1a1bc5 cosmetics (indent for BRK opcode) 2012-03-08 15:33:52 +00:00
zeromus fd6ac896fc general cleanup.. remove a bunch of warnings.. improve log console system a bit.. add new icons for log console window.. remove old demo psx interop system and add new, simpler one, which isnt really tested yet but is way less annoying. 2012-02-24 20:38:35 +00:00
zeromus 5f66de57ec discohawk-add capability for searching for mis-extensioned files (broadens compatibility a bit) and autodetecting audio tracks based on extension where otherwise marked as binary. 2012-01-21 21:23:19 +00:00
beirich 51f2e28e1b 68000: fix ASL/ASR bug. Correct calculation of carry flag on subtracty operations 2011-10-30 15:35:14 +00:00
beirich b4793ec43c 68000: flags were not calculated in EXT 2011-10-27 04:15:16 +00:00
beirich 7ae6dfb534 68000: implement CMPM 2011-10-27 04:02:11 +00:00
beirich e96912dab0 68000: fix dumb MULS/MULU/DIVS/DIVU bug 2011-10-27 03:06:33 +00:00
beirich 5a5a424cc7 gen: some work on renderer. 2011-10-18 03:48:37 +00:00
beirich 0924ad07fd 68000: fix bug in CMP instruction >_> 2011-10-13 02:38:23 +00:00
beirich 7cedd71729 68000: fix bug with ADDQ.W/SUBQ.W operating on address registers 2011-10-12 02:20:03 +00:00
beirich 04b93b5b8b erp, disable insanely slow 68000 logging in the checked-in version 2011-10-11 04:03:06 +00:00
beirich 5b5c7c2890 68000: add MULU, MULS, DIVU, DIVS, MOVE to CCR
Some genesis source reorganization
2011-10-11 03:52:44 +00:00
beirich c787b70613 68000: implement EORI, ROXL, ROXR. Fix bugs on ADDI.L and SUBI.L. Complete MOVA timings. Work on An/PC Indexed addressing modes. 2011-10-09 19:15:31 +00:00
beirich 2d2bfae611 68000: implement NEG, fix bug on ANDI.L 2011-10-09 06:19:59 +00:00
beirich a1d8e9a209 68000: implement UNLK, RTE, TRAP, ANDI to SR, and EORI to SR 2011-10-09 03:51:57 +00:00
beirich 1c38de023e 68000: implement BSET, BCLR, BCHG, and NOT 2011-10-08 23:26:29 +00:00
beirich 18de3c9efc 68000: implement AND, OR, EOR. Fix interrupt bug. Fix bug with SR register 2011-10-08 19:57:22 +00:00
beirich ccea71e74d 68000: interrupt support.
gen: fire vertical interrupt, now some games show sega logo before immediately crashing!
2011-10-08 15:44:41 +00:00
beirich 18a3f3f87a 68000: more flags fixes, especially N flag calculation. derp. :| 2011-10-07 05:13:15 +00:00
beirich 575a8940cb 68000: more add/sub flags fixes 2011-10-07 04:21:20 +00:00
beirich f2ca21759c 68000 timings and flags fixes, some new opcode handlers 2011-10-07 03:04:48 +00:00
beirich 8fb8a35317 Genesis core revive! Get it back to where loading a genesis rom doesnt crash everything immediately 2011-10-01 17:06:25 +00:00
beirich cf8216ac46 pce-cd: basically working pretty okay! (fixed bug causing issues with extended ADPCM playback sequences) 2011-09-28 05:03:22 +00:00
beirich f3dc6068ce delete extra/external 68k core 2011-09-27 02:46:23 +00:00
beirich 9aa70c4fa9 Much improved pce-cd savestateyfulness
Cleanup and stateyness of SCSI bus still in progress; states not done yet
2011-09-16 04:59:59 +00:00
beirich a8aaaef45e [PCE] ADPCM playback more or less working correctly now
plus some cleanup
2011-09-05 17:45:01 +00:00
beirich 8571853828 still-in-the-midst-of-it turbocd check-in 2011-08-29 02:47:03 +00:00
beirich 0a5157d9a6 Extremely preliminary TurboCD support 2011-08-14 18:20:13 +00:00
beirich 91baebf8b2 [PCE] Implement ORA under T-Flag, fixes City Hunter 2011-07-23 21:24:43 +00:00
beirich 47def064fa significant PCE timing/compat improvements, still poking at a few things 2011-07-19 03:53:07 +00:00
beirich 3f27ac0b2a Fix PCE Populous by supporting its custom SaveRAM.
+ Unsubstantial TurboCD progress.
2011-07-15 02:08:18 +00:00
beirich c8727ae01f fix some gamedb stuff, add some genesis games to db, get genesis back to a state where it at least loads roms correctly 2011-07-10 04:54:18 +00:00
zeromus 14cbe68303 fix 6502 disassembly 2011-06-10 03:43:17 +00:00
zeromus 72100bd304 [NES] ELROM emulation (cv3 and laser invasion tested) and core savestate logic brought up to date. savestates for newer mappers still need reworking. 2011-06-09 19:45:07 +00:00
zeromus d0ea2f7106 [NES] one last cpu bug 2011-06-07 01:31:06 +00:00
zeromus 00debfe6dd [NES] battletoads beyotch 2011-06-07 01:05:57 +00:00
zeromus e6afb2359b [nes] timing and accuracy work. 2011-06-06 10:27:42 +00:00
zeromus db28312787 [NES] fully consolidated text/binary serialization, and don't save screen buffer to binary savestates 2011-04-17 22:51:53 +00:00
zeromus 35f339149c remove stupid jscript dependency in core emulator 2011-04-17 08:49:49 +00:00
zeromus 9fd79ee576 [ARM] and some long overdue cleanup 2011-04-04 05:24:12 +00:00
zeromus e78708213c [ARM] add handful of floating point instructions and most importantly: NOP! 2011-04-04 05:13:45 +00:00
zeromus 510e52271b [ARM] 2011-04-03 07:58:12 +00:00
zeromus 5cd5e799a6 add 5% of the world's slowest ARM cpu emulator 2011-04-03 05:24:31 +00:00
zeromus 2fe2aae243 [NES] rewind for the masses 2011-03-21 02:22:10 +00:00
zeromus 6493b65690 [NES] fix some input bugs 2011-03-20 02:25:47 +00:00
zeromus f7bf5bdd17 [NES] fix some interrupt-related bugs to pass more cpu tests, add reset handling, improve iNES header handling some more 2011-03-20 02:12:10 +00:00
zeromus c7f0c457ad [NES] work on sound, improve square waves muchly, add 6502 IRQ signal, make add some infrastructure to keep from buffering samples while core is silenced. 2011-03-19 09:12:56 +00:00
beirich 0a354c2748 PCE: Fix a bug in the timer; fix glitch in VBlank interrupt handling (fixing intro in Dungeon Explorer) 2011-03-19 06:00:33 +00:00
beirich d211a6d3c5 PCE: Fix timer issue causing Battle Royale to break 2011-03-18 04:24:31 +00:00
beirich 5c9ee84ed4 PCE minor updates 2011-03-18 03:39:11 +00:00
beirich 3cdd222f51 HuC6280: Fix glitch in low-speed mode 2011-03-17 05:54:21 +00:00
beirich 4c9057060b HuC6280: Implement high/low speed modes 2011-03-17 04:29:46 +00:00
beirich ac3acfd721 oops, didn't get rid of all the 1-cycle page boundary penalties 2011-03-13 02:32:13 +00:00
beirich 420bad0a2e HuC6280: Accepting an interrupt takes 8 cycles; Correcting handling of T flag on RTI and PLP instructions; 1-cycle penalty for accesses across page boundaries does not apply 2011-03-13 02:22:29 +00:00
beirich e07349c582 [PCE] improve cpu instruction timing 2011-03-06 06:06:49 +00:00
zeromus 0d5cff7408 [NES] mapper cleanup and savestates 2011-03-01 09:32:12 +00:00
zeromus c21d92f694 [NES] add SxROM (mmc1), including save ram support. also add some undocumented NOP variants to 6502 core because I thought I needed them 2011-03-01 07:25:14 +00:00
zeromus ee336bec15 [NES] add 6502 BRK instruction and some mapper=2 games (incl. castlevania and megaman) 2011-02-28 07:53:19 +00:00