68000: implement EORI, ROXL, ROXR. Fix bugs on ADDI.L and SUBI.L. Complete MOVA timings. Work on An/PC Indexed addressing modes.
This commit is contained in:
beirich
parent
2d2bfae611
commit
c787b70613
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@ -34,11 +34,14 @@ namespace BizHawk.Emulation.CPUs.M68000
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else if (Opcodes[op] == PEA) PEA_Disasm(info);
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else if (Opcodes[op] == ANDI) ANDI_Disasm(info);
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else if (Opcodes[op] == EORI) EORI_Disasm(info);
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else if (Opcodes[op] == ORI) ORI_Disasm(info);
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else if (Opcodes[op] == LSLd) LSLd_Disasm(info);
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else if (Opcodes[op] == LSRd) LSRd_Disasm(info);
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else if (Opcodes[op] == ASLd) ASLd_Disasm(info);
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else if (Opcodes[op] == ASRd) ASRd_Disasm(info);
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else if (Opcodes[op] == LSLd) LSLd_Disasm(info);
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else if (Opcodes[op] == LSRd) LSRd_Disasm(info);
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else if (Opcodes[op] == ROXLd) ROXLd_Disasm(info);
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else if (Opcodes[op] == ROXRd) ROXRd_Disasm(info);
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else if (Opcodes[op] == ROLd) ROLd_Disasm(info);
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else if (Opcodes[op] == RORd) RORd_Disasm(info);
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else if (Opcodes[op] == SWAP) SWAP_Disasm(info);
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@ -74,9 +74,7 @@ namespace BizHawk.Emulation.CPUs.M68000
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V = false;
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C = false;
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throw new NotTestedException();
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switch (size)
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{
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case 0: // Byte
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@ -299,6 +297,85 @@ namespace BizHawk.Emulation.CPUs.M68000
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info.Length = pc - info.PC;
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}
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void EORI()
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{
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int size = (op >> 6) & 3;
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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V = false;
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C = false;
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switch (size)
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{
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case 0: // byte
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{
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sbyte immed = (sbyte) ReadWord(PC); PC += 2;
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sbyte value = (sbyte) (PeekValueB(mode, reg) ^ immed);
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WriteValueB(mode, reg, value);
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N = (value & 0x80) != 0;
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Z = value == 0;
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PendingCycles -= mode == 0 ? 8 : 12 + EACyclesBW[mode, reg];
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return;
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}
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case 1: // word
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{
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short immed = ReadWord(PC); PC += 2;
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short value = (short)(PeekValueW(mode, reg) ^ immed);
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WriteValueW(mode, reg, value);
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N = (value & 0x8000) != 0;
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Z = value == 0;
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PendingCycles -= mode == 0 ? 8 : 12 + EACyclesBW[mode, reg];
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return;
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}
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case 2: // long
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{
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int immed = ReadLong(PC); PC += 4;
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int value = PeekValueL(mode, reg) ^ immed;
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WriteValueL(mode, reg, value);
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N = (value & 0x80000000) != 0;
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Z = value == 0;
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PendingCycles -= mode == 0 ? 16 : 20 + EACyclesL[mode, reg];
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return;
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}
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}
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}
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void EORI_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int size = (op >> 6) & 3;
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int mode = (op >> 3) & 7;
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int reg = (op >> 0) & 7;
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switch (size)
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{
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case 0: // byte
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{
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info.Mnemonic = "eori.b";
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sbyte immed = (sbyte) ReadWord(pc); pc += 2;
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info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 1, ref pc));
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break;
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}
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case 1: // word
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{
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info.Mnemonic = "eori.w";
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short immed = ReadWord(pc); pc += 2;
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info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 2, ref pc));
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break;
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}
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case 2: // long
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{
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info.Mnemonic = "eori.l";
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int immed = ReadLong(pc); pc += 4;
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info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 4, ref pc));
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break;
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}
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}
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info.Length = pc - info.PC;
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}
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void OR0() // OR <ea>, Dn
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{
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int dstReg = (op >> 9) & 0x07;
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@ -1003,6 +1080,152 @@ namespace BizHawk.Emulation.CPUs.M68000
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info.Length = pc - info.PC;
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}
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void ROXLd()
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{
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int rot = (op >> 9) & 7;
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int size = (op >> 6) & 3;
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int m = (op >> 5) & 1;
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int reg = op & 7;
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if (m == 0 && rot == 0) rot = 8;
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else if (m == 1) rot = D[rot].s32 & 63;
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C = X;
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V = false;
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switch (size)
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{
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case 0: // byte
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for (int i = 0; i < rot; i++)
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{
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C = (D[reg].u8 & 0x80) != 0;
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D[reg].u8 = (byte)((D[reg].u8 << 1) | (X ? 1 : 0));
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X = C;
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}
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N = (D[reg].s8 & 0x80) != 0;
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Z = D[reg].s8 == 0;
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PendingCycles -= 6 + (rot * 2);
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return;
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case 1: // word
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for (int i = 0; i < rot; i++)
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{
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C = (D[reg].u16 & 0x8000) != 0;
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D[reg].u16 = (ushort)((D[reg].u16 << 1) | (X ? 1 : 0));
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X = C;
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}
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N = (D[reg].s16 & 0x8000) != 0;
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Z = D[reg].s16 == 0;
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PendingCycles -= 6 + (rot * 2);
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return;
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case 2: // long
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for (int i = 0; i < rot; i++)
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{
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C = (D[reg].s32 & 0x80000000) != 0;
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D[reg].s32 = ((D[reg].s32 << 1) | (X ? 1 : 0));
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X = C;
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}
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N = (D[reg].s32 & 0x80000000) != 0;
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Z = D[reg].s32 == 0;
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PendingCycles -= 8 + (rot * 2);
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return;
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}
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}
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void ROXLd_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int rot = (op >> 9) & 7;
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int size = (op >> 6) & 3;
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int m = (op >> 5) & 1;
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int reg = op & 7;
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if (m == 0 && rot == 0) rot = 8;
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switch (size)
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{
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case 0: info.Mnemonic = "roxl.b"; break;
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case 1: info.Mnemonic = "roxl.w"; break;
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case 2: info.Mnemonic = "roxl.l"; break;
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}
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if (m == 0) info.Args = rot + ", D" + reg;
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else info.Args = "D" + rot + ", D" + reg;
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info.Length = pc - info.PC;
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}
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void ROXRd()
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{
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int rot = (op >> 9) & 7;
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int size = (op >> 6) & 3;
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int m = (op >> 5) & 1;
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int reg = op & 7;
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if (m == 0 && rot == 0) rot = 8;
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else if (m == 1) rot = D[rot].s32 & 63;
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C = X;
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V = false;
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switch (size)
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{
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case 0: // byte
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for (int i = 0; i < rot; i++)
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{
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C = (D[reg].u8 & 1) != 0;
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D[reg].u8 = (byte)((D[reg].u8 >> 1) | (X ? 0x80 : 0));
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X = C;
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}
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N = (D[reg].s8 & 0x80) != 0;
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Z = D[reg].s8 == 0;
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PendingCycles -= 6 + (rot * 2);
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return;
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case 1: // word
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for (int i = 0; i < rot; i++)
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{
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C = (D[reg].u16 & 1) != 0;
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D[reg].u16 = (ushort)((D[reg].u16 >> 1) | (X ? 0x8000 : 0));
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X = C;
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}
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N = (D[reg].s16 & 0x8000) != 0;
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Z = D[reg].s16 == 0;
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PendingCycles -= 6 + (rot * 2);
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return;
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case 2: // long
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for (int i = 0; i < rot; i++)
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{
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C = (D[reg].s32 & 1) != 0;
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D[reg].u32 = ((D[reg].u32 >> 1) | (X ? 0x80000000 : 0));
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X = C;
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}
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N = (D[reg].s32 & 0x80000000) != 0;
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Z = D[reg].s32 == 0;
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PendingCycles -= 8 + (rot * 2);
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return;
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}
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}
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void ROXRd_Disasm(DisassemblyInfo info)
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{
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int pc = info.PC + 2;
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int rot = (op >> 9) & 7;
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int size = (op >> 6) & 3;
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int m = (op >> 5) & 1;
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int reg = op & 7;
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if (m == 0 && rot == 0) rot = 8;
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switch (size)
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{
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case 0: info.Mnemonic = "roxr.b"; break;
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case 1: info.Mnemonic = "roxr.w"; break;
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case 2: info.Mnemonic = "roxr.l"; break;
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}
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if (m == 0) info.Args = rot + ", D" + reg;
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else info.Args = "D" + rot + ", D" + reg;
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info.Length = pc - info.PC;
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}
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void SWAP()
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{
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int reg = op & 7;
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@ -90,16 +90,19 @@ namespace BizHawk.Emulation.CPUs.M68000
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case 2: PendingCycles -= 8; break;
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case 3: PendingCycles -= 8; break;
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case 4: PendingCycles -= 10; break;
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case 5: PendingCycles -= 12; break;
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case 6: PendingCycles -= 14; break;
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case 7:
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switch (srcReg)
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{
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case 0: PendingCycles -= 12; break;
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case 1: PendingCycles -= 16; break;
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case 2: PendingCycles -= 12; break;
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case 3: PendingCycles -= 14; break;
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case 4: PendingCycles -= 8; break;
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default: throw new NotImplementedException();
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default: throw new InvalidOperationException();
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}
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break;
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default: throw new NotImplementedException();
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}
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} else { // Long
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A[dstReg].s32 = ReadValueL(srcMode, srcReg);
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@ -110,16 +113,19 @@ namespace BizHawk.Emulation.CPUs.M68000
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case 2: PendingCycles -= 12; break;
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case 3: PendingCycles -= 12; break;
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case 4: PendingCycles -= 14; break;
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case 5: PendingCycles -= 16; break;
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case 6: PendingCycles -= 18; break;
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case 7:
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switch (srcReg)
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{
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case 0: PendingCycles -= 16; break;
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case 1: PendingCycles -= 20; break;
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case 2: PendingCycles -= 16; break;
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case 3: PendingCycles -= 18; break;
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case 4: PendingCycles -= 12; break;
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default: throw new NotImplementedException();
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default: throw new InvalidOperationException();
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}
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break;
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default: throw new NotImplementedException();
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}
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}
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}
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@ -169,7 +169,7 @@ namespace BizHawk.Emulation.CPUs.M68000
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}
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case 2: // long
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{
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int immed = ReadLong(PC); PC += 2;
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int immed = ReadLong(PC); PC += 4;
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int value = PeekValueL(mode, reg);
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long result = value + immed;
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long uresult = (uint)value + (uint)immed;
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@ -492,7 +492,7 @@ namespace BizHawk.Emulation.CPUs.M68000
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}
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case 2: // long
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{
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int immed = ReadLong(PC); PC += 2;
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int immed = ReadLong(PC); PC += 4;
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int value = PeekValueL(mode, reg);
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long result = value - immed;
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long uresult = (uint)value - (uint)immed;
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@ -302,10 +302,7 @@ namespace BizHawk.Emulation.CPUs.M68000
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case 2: return A[reg].s32; // (An)
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case 3: return A[reg].s32; // (An)+
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case 4: return A[reg].s32; // -(An)
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case 5: // (d16,An)
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addr = A[reg].s32 + ReadWord(PC);
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PC += 2;
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return addr;
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case 5: addr = A[reg].s32 + ReadWord(PC); PC += 2; return addr; // (d16,An)
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case 6: return A[reg].s32 + GetIndex(); // (d8,An,Xn)
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case 7:
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switch (reg)
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@ -324,6 +321,7 @@ namespace BizHawk.Emulation.CPUs.M68000
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string DisassembleValue(int mode, int reg, int size, ref int pc)
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{
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string value;
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int addr;
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switch (mode)
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{
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case 0: return "D"+reg; // Dn
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@ -331,33 +329,15 @@ namespace BizHawk.Emulation.CPUs.M68000
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case 2: return "(A"+reg+")"; // (An)
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case 3: return "(A"+reg+")+"; // (An)+
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case 4: return "-(A"+reg+")"; // -(An)
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case 5: // (d16,An)
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// TODO need to figure out how to print signed-hex
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value = string.Format("(${0:X},A{1})", ReadWord(pc), reg);
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pc += 2;
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return value;
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case 6: return "NOT IMPLEMENTED"; // (d8,An,Xn)
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//return ReadByte(A[reg].Long + GetIndex());
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case 5: value = string.Format("(${0:X},A{1})", ReadWord(pc), reg); pc += 2; return value; // (d16,An)
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case 6: addr = ReadWord(pc); pc += 2; return DisassembleIndex("A" + reg, (short) addr); // (d8,An,Xn)
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case 7:
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switch (reg)
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{
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case 0: // (imm).W
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value = String.Format("(${0:X})", ReadWord(pc));
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pc += 2;
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return value;
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case 1: // (imm).L
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value = String.Format("(${0:X})", ReadLong(pc));
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pc += 4;
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return value;
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case 2: // (d16,PC)
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value = String.Format("(${0:X})", pc + ReadWord(pc));
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pc += 2;
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return value;
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case 3: // (d8,PC,Xn)
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return "NOT IMPLEMENTED";
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/* uint _pc = PC;
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value = ReadByte((_pc + GetIndex()));
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return value;*/
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case 0: value = String.Format("(${0:X})", ReadWord(pc)); pc += 2; return value; // (imm).W
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case 1: value = String.Format("(${0:X})", ReadLong(pc)); pc += 4; return value; // (imm).L
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case 2: value = String.Format("(${0:X})", pc + ReadWord(pc)); pc += 2; return value; // (d16,PC)
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case 3: addr = ReadWord(pc); pc += 2; return DisassembleIndex("PC", (short)addr); // (d8,PC,Xn)
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case 4:
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switch (size)
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{
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@ -400,18 +380,15 @@ namespace BizHawk.Emulation.CPUs.M68000
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case 2: return "(A"+reg+")"; // (An)
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case 3: return "(A"+reg+")+"; // (An)+
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case 4: return "-(A"+reg+")"; // -(An)
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case 5: // (d16,An)
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addr = ReadWord(pc);
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pc += 2;
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return String.Format("({0},A{1})", addr, reg);
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case 6: return "NOT IMPLEMENTED"; // (d8,An,Xn)
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case 5: addr = ReadWord(pc); pc += 2; return String.Format("({0},A{1})", addr, reg); // (d16,An)
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case 6: addr = ReadWord(pc); pc += 2; return DisassembleIndex("A" + reg, (short)addr); // (d8,An,Xn)
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case 7:
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switch (reg)
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{
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case 0: addr = ReadWord(pc); pc += 2; return String.Format("${0:X}.w",addr); // (imm).w
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case 1: addr = ReadLong(pc); pc += 4; return String.Format("${0:X}.l",addr); // (imm).l
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case 2: addr = ReadWord(pc); pc += 2; return String.Format("(${0:X},PC)",addr); // (d16,PC)
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case 3: return "NOT IMPLEMENTED"; // (d8,PC,Xn)
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case 3: addr = ReadWord(pc); pc += 2; return DisassembleIndex("PC", (short)addr); // (d8,PC,Xn)
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case 4: return "INVALID"; // immediate
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}
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break;
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@ -573,9 +550,9 @@ namespace BizHawk.Emulation.CPUs.M68000
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short extension = ReadWord(PC); PC += 2;
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int da = (extension >> 15) & 0x1;
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int reg = (extension >> 12) & 0x7;
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int size = (extension >> 11) & 0x1;
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int da = (extension >> 15) & 0x1;
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int reg = (extension >> 12) & 0x7;
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int size = (extension >> 11) & 0x1;
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int scale = (extension >> 9) & 0x3;
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sbyte displacement = (sbyte)extension;
|
||||
|
||||
|
|
@ -622,5 +599,28 @@ namespace BizHawk.Emulation.CPUs.M68000
|
|||
|
||||
return displacement + indexReg;
|
||||
}
|
||||
|
||||
string DisassembleIndex(string baseRegister, short extension)
|
||||
{
|
||||
int d_a = (extension >> 15) & 0x1;
|
||||
int reg = (extension >> 12) & 0x7;
|
||||
int size = (extension >> 11) & 0x1;
|
||||
int scale = (extension >> 9) & 0x3;
|
||||
sbyte displacement = (sbyte)extension;
|
||||
|
||||
string scaleFactor;
|
||||
switch (scale)
|
||||
{
|
||||
case 0: scaleFactor = ""; break;
|
||||
case 1: scaleFactor = "2"; break;
|
||||
case 2: scaleFactor = "4"; break;
|
||||
default: scaleFactor = "8"; break;
|
||||
}
|
||||
|
||||
string offsetRegister = (d_a == 0) ? "D" : "A";
|
||||
string sizeStr = size == 0 ? ".w" : ".l";
|
||||
string displacementStr = displacement == 0 ? "" : ("," + displacement);
|
||||
return string.Format("({0},{1}{2}{3}{4}{5})", baseRegister, scaleFactor, offsetRegister, reg, sizeStr, displacementStr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -21,11 +21,14 @@ namespace BizHawk.Emulation.CPUs.M68000
|
|||
Assign("pea", PEA, "0100100001", "AmXn");
|
||||
|
||||
Assign("andi", ANDI, "00000010", "Size2_1", "AmXn");
|
||||
Assign("eori", EORI, "00001010", "Size2_1", "AmXn");
|
||||
Assign("ori", ORI, "00000000", "Size2_1", "AmXn");
|
||||
Assign("lsl", LSLd, "1110", "Data3", "1", "Size2_1", "Data1", "01", "Xn");
|
||||
Assign("lsr", LSRd, "1110", "Data3", "0", "Size2_1", "Data1", "01", "Xn");
|
||||
Assign("asl", ASLd, "1110", "Data3", "1", "Size2_1", "Data1", "00", "Xn");
|
||||
Assign("asr", ASRd, "1110", "Data3", "0", "Size2_1", "Data1", "00", "Xn");
|
||||
Assign("lsl", LSLd, "1110", "Data3", "1", "Size2_1", "Data1", "01", "Xn");
|
||||
Assign("lsr", LSRd, "1110", "Data3", "0", "Size2_1", "Data1", "01", "Xn");
|
||||
Assign("roxl", ROXLd, "1110", "Data3", "1", "Size2_1", "Data1", "10", "Xn");
|
||||
Assign("roxr", ROXRd, "1110", "Data3", "0", "Size2_1", "Data1", "10", "Xn");
|
||||
Assign("rol", ROLd, "1110", "Data3", "1", "Size2_1", "Data1", "11", "Xn");
|
||||
Assign("ror", RORd, "1110", "Data3", "0", "Size2_1", "Data1", "11", "Xn");
|
||||
Assign("swap", SWAP, "0100100001000","Xn");
|
||||
|
|
@ -107,7 +110,7 @@ namespace BizHawk.Emulation.CPUs.M68000
|
|||
foreach (var opcode in opList)
|
||||
{
|
||||
int opc = Convert.ToInt32(opcode, 2);
|
||||
if (Opcodes[opc] != null && instr.NotIn("movea","andi2sr","ori2sr","ext","dbcc","swap"))
|
||||
if (Opcodes[opc] != null && instr.NotIn("movea","andi2sr","eori2sr","ori2sr","ext","dbcc","swap"))
|
||||
Console.WriteLine("Setting opcode for {0}, a handler is already set. overwriting. {1:X4}", instr, opc);
|
||||
Opcodes[opc] = exec;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue