-Made HLT throw an exception.
-Made all instructions in the executor, even implemented ones, throw exceptions. I will get rid of the exceptions as I test the instructions. -Added instructions up to and including 0x57 to disassembly and executor.
This commit is contained in:
brandman211
parent
a4912e66c0
commit
61cada6190
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@ -10,7 +10,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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public string Disassemble(ushort pc, out int bytesToAdvance)
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{
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bytesToAdvance = 1;
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int second, third, op1, op2, op3;
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byte register;
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int second, third, op1, op2;
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string result = "";
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int opcode = ReadMemory(RegisterPC) & 0x3FF;
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switch (opcode)
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@ -28,15 +29,15 @@ namespace BizHawk.Emulation.CPUs.CP1610
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second = ReadMemory((byte)(RegisterPC + 1));
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third = ReadMemory((byte)(RegisterPC + 1));
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// rr indicates the register into which to store the return address
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op1 = (second >> 8) & 0x3;
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register = (byte)(((second >> 8) & 0x3) + 4);
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// ff indicates how to affect the Interrupt (I) flag in the CP1610
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op2 = second & 0x3;
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op1 = second & 0x3;
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// aaaaaaaaaaaaaaaa indicates the address to where the CP1610 should Jump
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op3 = ((second << 8) & 0xFC00) | (third & 0x3FF);
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op2 = ((second << 8) & 0xFC00) | (third & 0x3FF);
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result = "J";
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if (op1 != 0x3)
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if (register != 0x7)
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result += "SR";
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switch (op2)
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switch (op1)
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{
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case 0x1:
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result += "E";
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@ -48,9 +49,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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// Unknown opcode.
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break;
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}
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if (op1 != 0x3)
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result += " R" + (op1 + 4) + ",";
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result += string.Format(" ${0:X4})", op3);
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if (register != 0x3)
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result += " R" + register + ",";
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result += string.Format(" ${0:X4})", op2);
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bytesToAdvance = 3;
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return result;
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case 0x005:
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@ -59,7 +60,6 @@ namespace BizHawk.Emulation.CPUs.CP1610
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return "CLRC";
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case 0x007:
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return "SETC";
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// INCR
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case 0x008:
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case 0x009:
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case 0x00A:
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@ -68,8 +68,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x00D:
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case 0x00E:
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case 0x00F:
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throw new NotImplementedException();
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// DECR
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register = (byte)(opcode & 0x7);
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return "INCR R" + register;
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case 0x010:
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case 0x011:
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case 0x012:
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@ -78,8 +78,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x015:
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case 0x016:
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case 0x017:
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throw new NotImplementedException();
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// COMR
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register = (byte)(opcode & 0x7);
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return "DECR R" + register;
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case 0x018:
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case 0x019:
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case 0x01A:
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@ -88,8 +88,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x01D:
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case 0x01E:
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case 0x01F:
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throw new NotImplementedException();
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// NEGR
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register = (byte)(opcode & 0x7);
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return "COMR R" + register;
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case 0x020:
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case 0x021:
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case 0x022:
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@ -98,8 +98,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x025:
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case 0x026:
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case 0x027:
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throw new NotImplementedException();
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// ADCR
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register = (byte)(opcode & 0x7);
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return "NEGR R" + register;
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case 0x028:
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case 0x029:
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case 0x02A:
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@ -108,22 +108,20 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x02D:
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case 0x02E:
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case 0x02F:
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throw new NotImplementedException();
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// GSWD
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register = (byte)(opcode & 0x7);
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return "ADCR R" + register;
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case 0x030:
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case 0x031:
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case 0x032:
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case 0x033:
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throw new NotImplementedException();
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// NOP
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register = (byte)(opcode & 0x3);
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return "GSWD R" + register;
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case 0x034:
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case 0x035:
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throw new NotImplementedException();
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// SIN
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return "NOP";
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case 0x036:
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case 0x037:
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throw new NotImplementedException();
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// RSWD
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return "SIN";
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case 0x038:
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case 0x039:
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case 0x03A:
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@ -132,8 +130,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x03D:
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case 0x03E:
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case 0x03F:
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throw new NotImplementedException();
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// SWAP
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register = (byte)(opcode & 0x7);
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return "RSWD R" + register;
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case 0x040:
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case 0x041:
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case 0x042:
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@ -142,8 +140,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x045:
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case 0x046:
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case 0x047:
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throw new NotImplementedException();
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// SLL
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register = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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return "SWAP R" + register + ", " + (op1 + 1);
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case 0x048:
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case 0x049:
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case 0x04A:
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@ -152,8 +151,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x04D:
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case 0x04E:
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case 0x04F:
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throw new NotImplementedException();
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// RLC
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register = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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return "SLL R" + register + ", " + (op1 + 1);
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case 0x050:
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case 0x051:
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case 0x052:
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@ -162,7 +162,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x055:
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case 0x056:
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case 0x057:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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return "RLC R" + register + ", " + (op1 + 1);
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// SLLC
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case 0x058:
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case 0x059:
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@ -23,6 +23,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
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FlagS = ((result & 0x8000) != 0);
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}
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private void Calc_FlagS_7(int result)
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{
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FlagS = ((result & 0x80) != 0);
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}
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private void Calc_FlagZ(int result)
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{
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FlagZ = (result == 0);
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@ -30,8 +35,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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public void Execute(int cycles)
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{
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byte target;
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int second, third, op1, op2, op3, temp, result;
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byte register;
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int second, third, op1, op2, temp, result = 0;
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PendingCycles += cycles;
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while (PendingCycles > 0)
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{
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@ -39,33 +44,38 @@ namespace BizHawk.Emulation.CPUs.CP1610
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switch (opcode)
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{
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case 0x000: // HLT
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throw new NotImplementedException();
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// Unexpected behavior.
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throw new ArgumentException();
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case 0x001: // SDBD
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throw new NotImplementedException();
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FlagD = true;
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PendingCycles -= 4; TotalExecutedCycles += 4;
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break;
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case 0x002: // EIS
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throw new NotImplementedException();
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FlagI = true;
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PendingCycles -= 4; TotalExecutedCycles += 4;
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break;
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case 0x003: // DIS
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throw new NotImplementedException();
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FlagI = false;
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PendingCycles -= 4; TotalExecutedCycles += 4;
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break;
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case 0x004: // J, JE, JD, JSR, JSRE, JSRD
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throw new NotImplementedException();
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// 0000:0000:0000:0100 0000:00rr:aaaa:aaff 0000:00aa:aaaa:aaaa
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second = ReadMemory(RegisterPC++);
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third = ReadMemory(RegisterPC++);
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// rr indicates the register into which to store the return address
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op1 = (second >> 8) & 0x3;
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register = (byte)(((second >> 8) & 0x3) + 4);
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// ff indicates how to affect the Interrupt (I) flag in the CP1610
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op2 = second & 0x3;
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op1 = second & 0x3;
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// aaaaaaaaaaaaaaaa indicates the address to where the CP1610 should Jump
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op3 = ((second << 8) & 0xFC00) | (third & 0x3FF);
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if (op1 != 0x3)
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op2 = ((second << 8) & 0xFC00) | (third & 0x3FF);
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if (register != 0x7)
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// Store the return address.
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Register[op1 + 4] = (ushort)((RegisterPC + 1) & 0xFFFF);
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switch (op2)
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Register[register] = (ushort)((RegisterPC + 1) & 0xFFFF);
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switch (op1)
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{
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case 0x1:
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FlagI = true;
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@ -77,16 +87,21 @@ namespace BizHawk.Emulation.CPUs.CP1610
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// Unknown opcode.
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throw new ArgumentException();
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}
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RegisterPC = (ushort)op3;
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RegisterPC = (ushort)op2;
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PendingCycles -= 12; TotalExecutedCycles += 12;
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break;
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case 0x005: // TCI
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throw new NotImplementedException();
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// Little or no use in Intellivision.
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PendingCycles -= 4; TotalExecutedCycles += 4;
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break;
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case 0x006: // CLRC
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throw new NotImplementedException();
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FlagC = false;
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PendingCycles -= 4; TotalExecutedCycles += 4;
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break;
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case 0x007: // SETC
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throw new NotImplementedException();
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FlagC = true;
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PendingCycles -= 4; TotalExecutedCycles += 4;
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break;
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@ -99,11 +114,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x00D:
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case 0x00E:
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case 0x00F:
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target = (byte)(opcode & 0x7);
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result = (Register[target] + 1) & 0xFFFF;
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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result = (Register[register] + 1) & 0xFFFF;
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[target] = (ushort)result;
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Register[register] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// DECR
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@ -115,11 +131,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x015:
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case 0x016:
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case 0x017:
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target = (byte)(opcode & 0x7);
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result = (Register[target] - 1) & 0xFFFF;
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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result = (Register[register] - 1) & 0xFFFF;
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[target] = (ushort)result;
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Register[register] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// COMR
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@ -131,11 +148,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x01D:
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case 0x01E:
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case 0x01F:
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target = (byte)(opcode & 0x7);
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result = Register[target] ^ 0xFFFF;
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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result = Register[register] ^ 0xFFFF;
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[target] = (ushort)result;
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Register[register] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// NEGR
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@ -147,8 +165,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x025:
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case 0x026:
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case 0x027:
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target = (byte)(opcode & 0x7);
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op1 = Register[target];
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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op1 = Register[register];
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temp = (op1 ^ 0xFFFF);
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result = temp + 1;
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Calc_FlagC(result);
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@ -156,7 +175,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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Calc_FlagS(result);
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Calc_FlagZ(result);
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result &= 0xFFFF;
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Register[target] = (ushort)result;
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Register[register] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// ADCR
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@ -168,8 +187,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x02D:
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case 0x02E:
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case 0x02F:
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target = (byte)(opcode & 0x7);
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op1 = Register[target];
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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op1 = Register[register];
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op2 = FlagC ? 1 : 0;
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result = op1 + op2;
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Calc_FlagC(result);
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@ -177,7 +197,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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Calc_FlagS(result);
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Calc_FlagZ(result);
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result &= 0xFFFF;
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Register[target] = (ushort)result;
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Register[register] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// GSWD
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@ -186,14 +206,23 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x032:
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case 0x033:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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temp = ((FlagS ? 1 : 0) << 3) | ((FlagZ ? 1 : 0) << 2) | ((FlagO ? 1 : 0) << 1) | (FlagC ? 1 : 0);
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Register[register] = (ushort)((temp << 12) | (temp << 4));
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// NOP
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case 0x034:
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case 0x035:
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throw new NotImplementedException();
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break;
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// SIN
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case 0x036:
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case 0x037:
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throw new NotImplementedException();
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// Little or no use in Intellivision.
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// RSWD
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case 0x038:
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case 0x039:
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@ -204,6 +233,14 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x03E:
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case 0x03F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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op1 = Register[register];
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FlagC = ((op1 & 0x80) != 0) ? true : false;
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FlagO = ((op1 & 0x40) != 0) ? true : false;
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FlagZ = ((op1 & 0x20) != 0) ? true : false;
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FlagS = ((op1 & 0x10) != 0) ? true : false;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// SWAP
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case 0x040:
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case 0x041:
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@ -214,6 +251,24 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x046:
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case 0x047:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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op2 = Register[register];
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temp = op2 & 0xFF;
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if (op1 == 0)
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{
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// Single swap.
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result = (temp << 8) | ((op2 >> 8) & 0xFF);
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PendingCycles -= 6; TotalExecutedCycles += 6;
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}
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else
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{
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// Double swap.
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result = (temp << 8) | temp;
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PendingCycles -= 8; TotalExecutedCycles += 8;
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}
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Calc_FlagS_7(result);
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Calc_FlagZ(result);
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// SLL
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case 0x048:
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case 0x049:
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@ -224,6 +279,23 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x04E:
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case 0x04F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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result = Register[register] << 1;
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if (op1 == 0)
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{
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// Single shift.
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PendingCycles -= 6; TotalExecutedCycles += 6;
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}
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else
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{
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// Double shift.
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result <<= 1;
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PendingCycles -= 8; TotalExecutedCycles += 8;
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}
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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// RLC
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case 0x050:
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case 0x051:
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|
|
@ -234,6 +306,27 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x056:
|
||||
case 0x057:
|
||||
throw new NotImplementedException();
|
||||
register = (byte)(opcode & 0x3);
|
||||
op1 = opcode & 0x4;
|
||||
op2 = Register[register];
|
||||
result = (op2 << 1) | (FlagC ? 1 : 0);
|
||||
FlagC = ((op2 & 0x8000) != 0);
|
||||
if (op1 == 0)
|
||||
{
|
||||
// Single rotate.
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Double rotate.
|
||||
result <<= 1;
|
||||
result |= (FlagO ? 1 : 0);
|
||||
FlagO = ((op2 & 0x4000) != 0);
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register] = (ushort)result;
|
||||
// SLLC
|
||||
case 0x058:
|
||||
case 0x059:
|
||||
|
|
|
|||
Loading…
Reference in New Issue