-Made MVI@ and ADD@ follow the stack and immediate mode rules for incrementing / decrementing the SP / PC.
-Disabled Intellicart hook for ReadMemory, which seemed to be interfering. -Implemented MVO@. -Several instructions are now executed in succession until it hits the unimplemented "XORR R5, R5". I should probably refactor Disassemble and Execute to label registers as source / destination to avoid further confusion at some point. My disassembly might have the source / destination registers flipped as well.
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@ -1008,7 +1008,17 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x27D:
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case 0x27E:
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case 0x27F:
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throw new NotImplementedException();
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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WriteMemory(Register[register1], Register[register2]);
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// Stack mode.
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if (register1 == 0x6)
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RegisterSP--;
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// Immediate mode.
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if (register1 == 0x7)
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RegisterPC++;
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PendingCycles -= 9; TotalExecutedCycles += 9;
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break;
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// MVI
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case 0x280:
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case 0x281:
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@ -1097,6 +1107,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
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Register[register2] |= (ushort)(ReadMemory(Register[register1]) & 0xFF);
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PendingCycles -= 10; TotalExecutedCycles += 10;
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}
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// Stack mode.
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if (register1 == 0x6)
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RegisterSP++;
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// Immediate mode.
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if (register1 == 0x7)
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RegisterPC++;
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break;
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// ADD
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case 0x2C0:
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@ -1186,6 +1202,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
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op1 |= (ushort)(ReadMemory(Register[register1]) & 0xFF);
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PendingCycles -= 10; TotalExecutedCycles += 10;
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}
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// Stack mode.
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if (register1 == 0x6)
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RegisterSP++;
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// Immediate mode.
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if (register1 == 0x7)
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RegisterPC++;
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break;
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op2 = Register[register2];
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result = op1 + op2;
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Calc_FlagC(result);
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@ -45,8 +45,11 @@ namespace BizHawk.Emulation.Consoles.Intellivision
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default:
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throw new NotImplementedException();
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}
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/*
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TODO: Fix Intellicart hook.
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if (cart != null)
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return (ushort)cart;
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*/
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return core;
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}
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