-Made MVI@ and ADD@ follow the stack and immediate mode rules for incrementing / decrementing the SP / PC.

-Disabled Intellicart hook for ReadMemory, which seemed to be interfering.
-Implemented MVO@.
-Several instructions are now executed in succession until it hits the unimplemented "XORR R5, R5".

I should probably refactor Disassemble and Execute to label registers as source / destination to avoid further confusion at some point. My disassembly might have the source / destination registers flipped as well.
This commit is contained in:
brandman211 2012-07-20 07:22:41 +00:00
parent 6f295fe0c8
commit 610acf6ad6
2 changed files with 27 additions and 1 deletions

View File

@ -1008,7 +1008,17 @@ namespace BizHawk.Emulation.CPUs.CP1610
case 0x27D:
case 0x27E:
case 0x27F:
throw new NotImplementedException();
register1 = (byte)((opcode >> 3) & 0x7);
register2 = (byte)(opcode & 0x7);
WriteMemory(Register[register1], Register[register2]);
// Stack mode.
if (register1 == 0x6)
RegisterSP--;
// Immediate mode.
if (register1 == 0x7)
RegisterPC++;
PendingCycles -= 9; TotalExecutedCycles += 9;
break;
// MVI
case 0x280:
case 0x281:
@ -1097,6 +1107,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
Register[register2] |= (ushort)(ReadMemory(Register[register1]) & 0xFF);
PendingCycles -= 10; TotalExecutedCycles += 10;
}
// Stack mode.
if (register1 == 0x6)
RegisterSP++;
// Immediate mode.
if (register1 == 0x7)
RegisterPC++;
break;
// ADD
case 0x2C0:
@ -1186,6 +1202,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
op1 |= (ushort)(ReadMemory(Register[register1]) & 0xFF);
PendingCycles -= 10; TotalExecutedCycles += 10;
}
// Stack mode.
if (register1 == 0x6)
RegisterSP++;
// Immediate mode.
if (register1 == 0x7)
RegisterPC++;
break;
op2 = Register[register2];
result = op1 + op2;
Calc_FlagC(result);

View File

@ -45,8 +45,11 @@ namespace BizHawk.Emulation.Consoles.Intellivision
default:
throw new NotImplementedException();
}
/*
TODO: Fix Intellicart hook.
if (cart != null)
return (ushort)cart;
*/
return core;
}