Implemented / tested MVI@ and AND@.
-They both seem to work, but the operands for AND@ are both 0, so this seems fishy. -I don't know for sure if AND@ executes cycles in the same way that MVI@ as the documentation isn't clear on this, but I assumed it did. According to my disassembler, the first 5 instructions run on the Executive ROM are: JSRD R5, $1026 MVI@ R7, R6 ADD@ R6, R1 JSR R5, $1A83 HLT Considering that I hit a HLT, I figure something is going terribly wrong. Perhaps it has to do with my lack of an interrupt system?
This commit is contained in:
brandman211
parent
96e7d85122
commit
b2323458ba
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@ -35,7 +35,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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public void Execute(int cycles)
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{
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byte register;
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byte register1, register2;
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int second, third, op1, op2, temp, result = 0;
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PendingCycles += cycles;
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while (PendingCycles > 0)
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@ -66,14 +66,14 @@ namespace BizHawk.Emulation.CPUs.CP1610
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second = ReadMemory(RegisterPC++);
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third = ReadMemory(RegisterPC++);
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// rr indicates the register into which to store the return address
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register = (byte)(((second >> 8) & 0x3) + 4);
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register1 = (byte)(((second >> 8) & 0x3) + 4);
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// ff indicates how to affect the Interrupt (I) flag in the CP1610
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op1 = second & 0x3;
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// aaaaaaaaaaaaaaaa indicates the address to where the CP1610 should Jump
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op2 = ((second << 8) & 0xFC00) | (third & 0x3FF);
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if (register != 0x7)
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if (register1 != 0x7)
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// Store the return address.
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Register[register] = (ushort)((RegisterPC + 1) & 0xFFFF);
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Register[register1] = (ushort)((RegisterPC + 1) & 0xFFFF);
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switch (op1)
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{
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case 0x1:
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@ -114,11 +114,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x00E:
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case 0x00F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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result = (Register[register] + 1) & 0xFFFF;
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register1 = (byte)(opcode & 0x7);
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result = (Register[register1] + 1) & 0xFFFF;
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// DECR
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@ -131,11 +131,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x016:
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case 0x017:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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result = (Register[register] - 1) & 0xFFFF;
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register1 = (byte)(opcode & 0x7);
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result = (Register[register1] - 1) & 0xFFFF;
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// COMR
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@ -148,11 +148,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x01E:
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case 0x01F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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result = Register[register] ^ 0xFFFF;
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register1 = (byte)(opcode & 0x7);
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result = Register[register1] ^ 0xFFFF;
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// NEGR
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@ -165,8 +165,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x026:
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case 0x027:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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op1 = Register[register];
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register1 = (byte)(opcode & 0x7);
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op1 = Register[register1];
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temp = (op1 ^ 0xFFFF);
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result = temp + 1;
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Calc_FlagC(result);
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@ -174,7 +174,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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Calc_FlagS(result);
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Calc_FlagZ(result);
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result &= 0xFFFF;
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// ADCR
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@ -187,8 +187,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x02E:
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case 0x02F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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op1 = Register[register];
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register1 = (byte)(opcode & 0x7);
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op1 = Register[register1];
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op2 = FlagC ? 1 : 0;
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result = op1 + op2;
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Calc_FlagC(result);
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@ -196,7 +196,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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Calc_FlagS(result);
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Calc_FlagZ(result);
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result &= 0xFFFF;
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// GSWD
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@ -205,9 +205,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x032:
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case 0x033:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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temp = ((FlagS ? 1 : 0) << 3) | ((FlagZ ? 1 : 0) << 2) | ((FlagO ? 1 : 0) << 1) | (FlagC ? 1 : 0);
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Register[register] = (ushort)((temp << 12) | (temp << 4));
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Register[register1] = (ushort)((temp << 12) | (temp << 4));
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PendingCycles -= 6; TotalExecutedCycles += 6;
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break;
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// NOP
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@ -232,8 +232,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x03E:
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case 0x03F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x7);
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op1 = Register[register];
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register1 = (byte)(opcode & 0x7);
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op1 = Register[register1];
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FlagC = ((op1 & 0x80) != 0) ? true : false;
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FlagO = ((op1 & 0x40) != 0) ? true : false;
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FlagZ = ((op1 & 0x20) != 0) ? true : false;
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@ -250,9 +250,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x046:
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case 0x047:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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op2 = Register[register];
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op2 = Register[register1];
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temp = op2 & 0xFF;
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if (op1 == 0)
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{
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@ -278,9 +278,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x04E:
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case 0x04F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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result = Register[register] << 1;
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result = Register[register1] << 1;
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if (op1 == 0)
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{
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// Single shift.
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@ -294,7 +294,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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}
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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// RLC
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case 0x050:
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case 0x051:
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@ -305,9 +305,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x056:
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case 0x057:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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op2 = Register[register];
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op2 = Register[register1];
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result = (op2 << 1) | (FlagC ? 1 : 0);
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FlagC = ((op2 & 0x8000) != 0);
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if (op1 == 0)
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@ -325,7 +325,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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}
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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// SLLC
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case 0x058:
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case 0x059:
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@ -336,9 +336,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x05E:
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case 0x05F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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op2 = Register[register];
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op2 = Register[register1];
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result = op2 << 1;
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FlagC = ((op2 & 0x8000) != 0);
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if (op1 == 0)
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}
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Calc_FlagS(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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// SLR
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case 0x060:
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case 0x061:
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@ -366,9 +366,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x066:
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case 0x067:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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result = Register[register] >> 1;
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result = Register[register1] >> 1;
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if (op1 == 0)
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{
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// Single shift.
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@ -382,7 +382,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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}
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Calc_FlagS_7(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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// SAR
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case 0x068:
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case 0x069:
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@ -393,9 +393,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x06E:
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case 0x06F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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op2 = Register[register];
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op2 = Register[register1];
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temp = op2 & 0x8000;
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result = (op2 >> 1) | temp;
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if (op1 == 0)
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@ -412,7 +412,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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}
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Calc_FlagS_7(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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// RRC
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case 0x070:
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case 0x071:
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@ -423,9 +423,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x076:
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case 0x077:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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op2 = Register[register];
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op2 = Register[register1];
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result = (op2 >> 1) | ((FlagC ? 1 : 0) << 15);
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FlagC = ((op2 & 0x1) != 0);
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if (op1 == 0)
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@ -443,7 +443,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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}
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Calc_FlagS_7(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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// SARC
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case 0x078:
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case 0x079:
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@ -454,9 +454,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x07E:
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case 0x07F:
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throw new NotImplementedException();
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register = (byte)(opcode & 0x3);
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register1 = (byte)(opcode & 0x3);
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op1 = opcode & 0x4;
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op2 = Register[register];
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op2 = Register[register1];
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temp = op2 & 0x8000;
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result = (op2 >> 1) | temp;
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FlagC = ((op2 & 0x1) != 0);
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@ -475,7 +475,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
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}
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Calc_FlagS_7(result);
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Calc_FlagZ(result);
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Register[register] = (ushort)result;
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Register[register1] = (ushort)result;
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// MOVR
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case 0x080:
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case 0x081:
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@ -1076,7 +1076,28 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x2BD:
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case 0x2BE:
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case 0x2BF:
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throw new NotImplementedException();
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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if (!FlagD)
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{
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Register[register2] = ReadMemory(Register[register1]);
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if (register1 != 0x6)
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{
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PendingCycles -= 8; TotalExecutedCycles += 8;
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}
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else
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{
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PendingCycles -= 11; TotalExecutedCycles += 11;
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}
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}
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else
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{
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// Double Byte Data.
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Register[register2] = (ushort)(ReadMemory(Register[register1]++) << 8);
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Register[register2] |= (ushort)(ReadMemory(Register[register1]) & 0xFF);
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PendingCycles -= 10; TotalExecutedCycles += 10;
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}
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break;
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// ADD
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case 0x2C0:
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case 0x2C1:
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@ -1144,7 +1165,36 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x2FD:
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case 0x2FE:
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case 0x2FF:
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throw new NotImplementedException();
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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if (!FlagD)
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{
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op1 = ReadMemory(Register[register1]);
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if (register1 != 0x6)
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{
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PendingCycles -= 8; TotalExecutedCycles += 8;
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}
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else
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{
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PendingCycles -= 11; TotalExecutedCycles += 11;
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}
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}
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else
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{
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// Double Byte Data.
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op1 = (ushort)(ReadMemory(Register[register1]++) << 8);
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op1 |= (ushort)(ReadMemory(Register[register1]) & 0xFF);
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PendingCycles -= 10; TotalExecutedCycles += 10;
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}
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op2 = Register[register2];
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result = op1 + op2;
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Calc_FlagC(result);
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Calc_FlagO_Add(op1, op2);
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Calc_FlagS(result);
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Calc_FlagZ(result);
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result &= 0xFFFF;
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Register[register2] = (ushort)result;
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break;
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// SUB
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case 0x300:
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case 0x301:
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Loading…
Reference in New Issue