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Opcodes up to 0x5F.

This commit is contained in:
brandman211 2012-07-08 21:49:09 +00:00
parent 61cada6190
commit bb532aa2d9
2 changed files with 23 additions and 2 deletions
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5
BizHawk.Emulation/CPUs/CP1610/Disassembler.cs
View File

@ -165,7 +165,6 @@ namespace BizHawk.Emulation.CPUs.CP1610
register = (byte)(opcode & 0x3);
op1 = opcode & 0x4;
return "RLC R" + register + ", " + (op1 + 1);
// SLLC
case 0x058:
case 0x059:
case 0x05A:
@ -174,7 +173,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
case 0x05D:
case 0x05E:
case 0x05F:
throw new NotImplementedException();
register = (byte)(opcode & 0x3);
op1 = opcode & 0x4;
return "SLLC R" + register + ", " + (op1 + 1);
// SLR
case 0x060:
case 0x061:

20
BizHawk.Emulation/CPUs/CP1610/Execute.cs
View File

@ -337,6 +337,26 @@ namespace BizHawk.Emulation.CPUs.CP1610
case 0x05E:
case 0x05F:
throw new NotImplementedException();
register = (byte)(opcode & 0x3);
op1 = opcode & 0x4;
op2 = Register[register];
result = op2 << 1;
FlagC = ((op2 & 0x8000) != 0);
if (op1 == 0)
{
// Single shift.
PendingCycles -= 6; TotalExecutedCycles += 6;
}
else
{
// Double shift.
result <<= 1;
FlagO = ((op2 & 0x4000) != 0);
PendingCycles -= 8; TotalExecutedCycles += 8;
}
Calc_FlagS(result);
Calc_FlagZ(result);
Register[register] = (ushort)result;
// SLR
case 0x060:
case 0x061: