-Refactored of the executor / disassembler / Intellicart to use more descriptive variable names and types to clear up a lot of confusion.
-Added implementation for NOP (6 cycles of nothing). -Made SWAP actually store the result (Still disabled). -Added breaks to the swap / shift / rotate cases (Yikes). Instruction disassembly: JSRD R5, $1026 MVI@ R7, R6 JSR R5, $1A83 MVO@ R5, R6 MVO@ R0, R6 MVO@ R1, R6 MVI@ R7, R4 MVI@ R7, R0 JSR R5, $1738 MVO@ R5, R6 XORR R5, R5 <- Needs implementation.
This commit is contained in:
brandman211
parent
1616cc7eb9
commit
0a0763966c
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@ -9,11 +9,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
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{
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public const string UNKNOWN = "???";
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public string Disassemble(ushort pc, out int bytesToAdvance)
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public string Disassemble(ushort pc, out int addrToAdvance)
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{
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bytesToAdvance = 1;
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byte register1, register2;
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int second, third, op1, op2;
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addrToAdvance = 1;
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byte dest, src, mem;
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int decle2, decle3;
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int cond;
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ushort addr, offset;
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string result = "";
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int opcode = ReadMemory(pc) & 0x3FF;
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switch (opcode)
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@ -28,18 +30,17 @@ namespace BizHawk.Emulation.CPUs.CP1610
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return "DIS";
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case 0x004:
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// 0000:0000:0000:0100 0000:00rr:aaaa:aaff 0000:00aa:aaaa:aaaa
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second = ReadMemory((ushort)(pc + 1));
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third = ReadMemory((ushort)(pc + 2));
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decle2 = ReadMemory((ushort)(pc + 1));
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decle3 = ReadMemory((ushort)(pc + 2));
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// rr indicates the register into which to store the return address
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register1 = (byte)(((second >> 8) & 0x3) + 4);
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// ff indicates how to affect the Interrupt (I) flag in the CP1610
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op1 = second & 0x3;
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dest = (byte)(((decle2 >> 8) & 0x3) + 4);
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// aaaaaaaaaaaaaaaa indicates the address to where the CP1610 should Jump
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op2 = ((second << 8) & 0xFC00) | (third & 0x3FF);
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addr = (ushort)(((decle2 << 8) & 0xFC00) | (decle3 & 0x3FF));
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result = "J";
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if (register1 != 0x7)
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if (dest != 0x7)
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result += "SR";
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switch (op1)
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// ff indicates how to affect the Interrupt (I) flag in the CP1610
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switch (decle2 & 0x3)
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{
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case 0x1:
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result += "E";
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@ -51,10 +52,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
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// Unknown opcode.
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return UNKNOWN;
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}
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if (register1 != 0x3)
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result += " R" + register1 + ",";
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result += string.Format(" ${0:X4}", op2);
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bytesToAdvance = 3;
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if (dest != 0x3)
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result += " R" + dest + ",";
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result += string.Format(" ${0:X4}", addr);
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addrToAdvance = 3;
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return result;
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case 0x005:
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return "TCI";
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@ -70,8 +71,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x00D:
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case 0x00E:
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case 0x00F:
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register1 = (byte)(opcode & 0x7);
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return "INCR R" + register1;
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dest = (byte)(opcode & 0x7);
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return "INCR R" + dest;
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case 0x010:
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case 0x011:
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case 0x012:
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@ -80,8 +81,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x015:
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case 0x016:
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case 0x017:
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register1 = (byte)(opcode & 0x7);
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return "DECR R" + register1;
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dest = (byte)(opcode & 0x7);
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return "DECR R" + dest;
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case 0x018:
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case 0x019:
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case 0x01A:
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@ -90,8 +91,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x01D:
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case 0x01E:
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case 0x01F:
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register1 = (byte)(opcode & 0x7);
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return "COMR R" + register1;
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dest = (byte)(opcode & 0x7);
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return "COMR R" + dest;
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case 0x020:
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case 0x021:
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case 0x022:
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@ -100,8 +101,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x025:
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case 0x026:
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case 0x027:
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register1 = (byte)(opcode & 0x7);
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return "NEGR R" + register1;
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dest = (byte)(opcode & 0x7);
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return "NEGR R" + dest;
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case 0x028:
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case 0x029:
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case 0x02A:
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@ -110,14 +111,14 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x02D:
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case 0x02E:
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case 0x02F:
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register1 = (byte)(opcode & 0x7);
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return "ADCR R" + register1;
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dest = (byte)(opcode & 0x7);
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return "ADCR R" + dest;
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case 0x030:
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case 0x031:
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case 0x032:
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case 0x033:
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register1 = (byte)(opcode & 0x3);
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return "GSWD R" + register1;
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dest = (byte)(opcode & 0x3);
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return "GSWD R" + dest;
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case 0x034:
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case 0x035:
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result = "NOP";
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@ -138,8 +139,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x03D:
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case 0x03E:
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case 0x03F:
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register1 = (byte)(opcode & 0x7);
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return "RSWD R" + register1;
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src = (byte)(opcode & 0x7);
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return "RSWD R" + src;
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case 0x040:
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case 0x041:
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case 0x042:
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@ -148,8 +149,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x045:
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case 0x046:
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case 0x047:
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register1 = (byte)(opcode & 0x3);
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result = "SWAP R" + register1;
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dest = (byte)(opcode & 0x3);
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result = "SWAP R" + dest;
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if (((opcode >> 3) & 0x1) != 0)
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result += ", 1";
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return result;
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@ -161,8 +162,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x04D:
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case 0x04E:
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case 0x04F:
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register1 = (byte)(opcode & 0x3);
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result = "SLL R" + register1;
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dest = (byte)(opcode & 0x3);
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result = "SLL R" + dest;
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if (((opcode >> 3) & 0x1) != 0)
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result += ", 1";
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return result;
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@ -174,8 +175,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x055:
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case 0x056:
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case 0x057:
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register1 = (byte)(opcode & 0x3);
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result = "RLC R" + register1;
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dest = (byte)(opcode & 0x3);
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result = "RLC R" + dest;
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if (((opcode >> 3) & 0x1) != 0)
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result += ", 1";
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return result;
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@ -187,8 +188,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x05D:
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case 0x05E:
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case 0x05F:
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register1 = (byte)(opcode & 0x3);
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result = "SLLC R" + register1;
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dest = (byte)(opcode & 0x3);
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result = "SLLC R" + dest;
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if (((opcode >> 3) & 0x1) != 0)
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result += ", 1";
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return result;
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@ -200,8 +201,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x065:
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case 0x066:
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case 0x067:
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register1 = (byte)(opcode & 0x3);
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result = "SLR R" + register1;
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dest = (byte)(opcode & 0x3);
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result = "SLR R" + dest;
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if (((opcode >> 3) & 0x1) != 0)
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result += ", 1";
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return result;
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@ -213,8 +214,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x06D:
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case 0x06E:
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case 0x06F:
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register1 = (byte)(opcode & 0x3);
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result = "SAR R" + register1;
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dest = (byte)(opcode & 0x3);
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result = "SAR R" + dest;
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if (((opcode >> 3) & 0x1) != 0)
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result += ", 1";
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return result;
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@ -226,8 +227,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x075:
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case 0x076:
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case 0x077:
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register1 = (byte)(opcode & 0x3);
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result = "RRC R" + register1;
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dest = (byte)(opcode & 0x3);
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result = "RRC R" + dest;
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if (((opcode >> 3) & 0x1) != 0)
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result += ", 1";
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return result;
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@ -239,8 +240,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x07D:
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case 0x07E:
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case 0x07F:
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register1 = (byte)(opcode & 0x3);
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result = "SARC R" + register1;
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dest = (byte)(opcode & 0x3);
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result = "SARC R" + dest;
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if (((opcode >> 3) & 0x1) != 0)
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result += ", 1";
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return result;
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@ -308,9 +309,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x0BD:
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case 0x0BE:
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case 0x0BF:
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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return "MOVR R" + register1 + ", R" + register2;
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src = (byte)((opcode >> 3) & 0x7);
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dest = (byte)(opcode & 0x7);
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return "MOVR R" + src + ", R" + dest;
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case 0x0C0:
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case 0x0C1:
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case 0x0C2:
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@ -375,9 +376,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x0FD:
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case 0x0FE:
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case 0x0FF:
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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return "ADDR R" + register1 + ", R" + register2;
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src = (byte)((opcode >> 3) & 0x7);
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dest = (byte)(opcode & 0x7);
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return "ADDR R" + src + ", R" + dest;
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case 0x100:
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case 0x101:
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case 0x102:
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@ -442,9 +443,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x13D:
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case 0x13E:
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case 0x13F:
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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return "SUBR R" + register1 + ", R" + register2;
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src = (byte)((opcode >> 3) & 0x7);
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dest = (byte)(opcode & 0x7);
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return "SUBR R" + src + ", R" + dest;
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case 0x140:
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case 0x141:
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case 0x142:
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@ -509,9 +510,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x17D:
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case 0x17E:
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case 0x17F:
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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return "CMPR R" + register1 + ", R" + register2;
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src = (byte)((opcode >> 3) & 0x7);
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dest = (byte)(opcode & 0x7);
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return "CMPR R" + src + ", R" + dest;
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case 0x180:
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case 0x181:
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case 0x182:
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@ -576,9 +577,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x1BD:
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case 0x1BE:
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case 0x1BF:
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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return "ANDR R" + register1 + ", R" + register2;
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src = (byte)((opcode >> 3) & 0x7);
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dest = (byte)(opcode & 0x7);
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return "ANDR R" + src + ", R" + dest;
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case 0x1C0:
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case 0x1C1:
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case 0x1C2:
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@ -643,9 +644,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x1FD:
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case 0x1FE:
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case 0x1FF:
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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return "XORR R" + register1 + ", R" + register2;
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src = (byte)((opcode >> 3) & 0x7);
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dest = (byte)(opcode & 0x7);
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return "XORR R" + src + ", R" + dest;
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// Branch Forward, no External Condition
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case 0x200: // B
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case 0x201: // BC
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@ -714,13 +715,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x23D:
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case 0x23E:
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case 0x23F:
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second = ReadMemory((ushort)(pc + 1));
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op1 = opcode & 0x15;
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offset = ReadMemory((ushort)(pc + 1));
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cond = opcode & 0x15;
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if ((opcode & 0x16) != 0)
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result = "BEXT";
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else
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{
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switch (op1)
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switch (cond)
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{
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case 0x0:
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result = "B";
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@ -772,14 +773,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
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break;
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}
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}
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op2 = (opcode >> 5) & 0x1;
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if (op1 != 0x8)
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if (cond != 0x8)
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{
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result += string.Format(" ${0:X4}", second);
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if (op1 != 0x0)
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result += ", " + op2;
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result += string.Format(" ${0:X4}", offset);
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if (cond != 0x0)
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result += ", " + ((opcode >> 5) & 0x1);
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}
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bytesToAdvance = 2;
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addrToAdvance = 2;
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return result;
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case 0x240:
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case 0x241:
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@ -789,10 +789,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x245:
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case 0x246:
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case 0x247:
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register1 = (byte)(opcode & 0x7);
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second = ReadMemory((ushort)(pc + 1));
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bytesToAdvance = 2;
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return "MVO R" + register1 + ", " + string.Format("${0:X4}", second);
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src = (byte)(opcode & 0x7);
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addr = ReadMemory((ushort)(pc + 1));
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addrToAdvance = 2;
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return "MVO R" + src + ", " + string.Format("${0:X4}", addr);
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case 0x248:
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case 0x249:
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case 0x24A:
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@ -849,9 +849,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x27D:
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case 0x27E:
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case 0x27F:
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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return "MVO@ R" + register2 + ", R" + register1;
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mem = (byte)((opcode >> 3) & 0x7);
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src = (byte)(opcode & 0x7);
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return "MVO@ R" + src + ", R" + mem;
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case 0x280:
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case 0x281:
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case 0x282:
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|
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@ -860,10 +860,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x285:
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case 0x286:
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case 0x287:
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register1 = (byte)(opcode & 0x7);
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second = ReadMemory((ushort)(pc + 1));
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bytesToAdvance = 2;
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return "MVI R" + register1 + ", " + string.Format("${0:X4}", second);
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dest = (byte)(opcode & 0x7);
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addr = ReadMemory((ushort)(pc + 1));
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addrToAdvance = 2;
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return "MVI R" + dest + ", " + string.Format("${0:X4}", addr);
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case 0x288:
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case 0x289:
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case 0x28A:
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@ -920,9 +920,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
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case 0x2BD:
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case 0x2BE:
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case 0x2BF:
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register1 = (byte)((opcode >> 3) & 0x7);
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register2 = (byte)(opcode & 0x7);
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return "MVI@ R" + register1 + ", R" + register2;
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mem = (byte)((opcode >> 3) & 0x7);
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dest = (byte)(opcode & 0x7);
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return "MVI@ R" + mem + ", R" + dest;
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case 0x2C0:
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case 0x2C1:
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case 0x2C2:
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@ -931,10 +931,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
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case 0x2C5:
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case 0x2C6:
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case 0x2C7:
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register1 = (byte)(opcode & 0x7);
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second = ReadMemory((ushort)(pc + 1));
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bytesToAdvance = 2;
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return "ADD R" + register1 + ", " + string.Format("${0:X4}", second);
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dest = (byte)(opcode & 0x7);
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addr = ReadMemory((ushort)(pc + 1));
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addrToAdvance = 2;
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return "ADD R" + dest + ", " + string.Format("${0:X4}", addr);
|
||||
case 0x2C8:
|
||||
case 0x2C9:
|
||||
case 0x2CA:
|
||||
|
|
@ -991,9 +991,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x2FD:
|
||||
case 0x2FE:
|
||||
case 0x2FF:
|
||||
register1 = (byte)((opcode >> 3) & 0x7);
|
||||
register2 = (byte)(opcode & 0x7);
|
||||
return "ADD@ R" + register1 + ", R" + register2;
|
||||
mem = (byte)((opcode >> 3) & 0x7);
|
||||
dest = (byte)(opcode & 0x7);
|
||||
return "ADD@ R" + mem + ", R" + dest;
|
||||
case 0x300:
|
||||
case 0x301:
|
||||
case 0x302:
|
||||
|
|
@ -1002,10 +1002,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x305:
|
||||
case 0x306:
|
||||
case 0x307:
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
second = ReadMemory((ushort)(pc + 1));
|
||||
bytesToAdvance = 2;
|
||||
return "SUB R" + register1 + ", " + string.Format("${0:X4}", second);
|
||||
mem = (byte)(opcode & 0x7);
|
||||
addr = ReadMemory((ushort)(pc + 1));
|
||||
addrToAdvance = 2;
|
||||
return "SUB R" + mem + ", " + string.Format("${0:X4}", addr);
|
||||
case 0x308:
|
||||
case 0x309:
|
||||
case 0x30A:
|
||||
|
|
@ -1062,9 +1062,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x33D:
|
||||
case 0x33E:
|
||||
case 0x33F:
|
||||
register1 = (byte)((opcode >> 3) & 0x7);
|
||||
register2 = (byte)(opcode & 0x7);
|
||||
return "SUB@ R" + register1 + ", R" + register2;
|
||||
mem = (byte)((opcode >> 3) & 0x7);
|
||||
dest = (byte)(opcode & 0x7);
|
||||
return "SUB@ R" + mem + ", R" + dest;
|
||||
case 0x340:
|
||||
case 0x341:
|
||||
case 0x342:
|
||||
|
|
@ -1073,10 +1073,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x345:
|
||||
case 0x346:
|
||||
case 0x347:
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
second = ReadMemory((ushort)(pc + 1));
|
||||
bytesToAdvance = 2;
|
||||
return "CMP R" + register1 + ", " + string.Format("${0:X4}", second);
|
||||
mem = (byte)(opcode & 0x7);
|
||||
addr = ReadMemory((ushort)(pc + 1));
|
||||
addrToAdvance = 2;
|
||||
return "CMP R" + mem + ", " + string.Format("${0:X4}", addr);
|
||||
case 0x348:
|
||||
case 0x349:
|
||||
case 0x34A:
|
||||
|
|
@ -1133,9 +1133,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x37D:
|
||||
case 0x37E:
|
||||
case 0x37F:
|
||||
register1 = (byte)((opcode >> 3) & 0x7);
|
||||
register2 = (byte)(opcode & 0x7);
|
||||
return "CMP@ R" + register1 + ", R" + register2;
|
||||
mem = (byte)((opcode >> 3) & 0x7);
|
||||
dest = (byte)(opcode & 0x7);
|
||||
return "CMP@ R" + mem + ", R" + dest;
|
||||
case 0x380:
|
||||
case 0x381:
|
||||
case 0x382:
|
||||
|
|
@ -1144,10 +1144,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x385:
|
||||
case 0x386:
|
||||
case 0x387:
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
second = ReadMemory((ushort)(pc + 1));
|
||||
bytesToAdvance = 2;
|
||||
return "AND R" + register1 + ", " + string.Format("${0:X4}", second);
|
||||
mem = (byte)(opcode & 0x7);
|
||||
addr = ReadMemory((ushort)(pc + 1));
|
||||
addrToAdvance = 2;
|
||||
return "AND R" + mem + ", " + string.Format("${0:X4}", addr);
|
||||
case 0x388:
|
||||
case 0x389:
|
||||
case 0x38A:
|
||||
|
|
@ -1204,9 +1204,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x3BD:
|
||||
case 0x3BE:
|
||||
case 0x3BF:
|
||||
register1 = (byte)((opcode >> 3) & 0x7);
|
||||
register2 = (byte)(opcode & 0x7);
|
||||
return "AND@ R" + register1 + ", R" + register2;
|
||||
mem = (byte)((opcode >> 3) & 0x7);
|
||||
dest = (byte)(opcode & 0x7);
|
||||
return "AND@ R" + mem + ", R" + dest;
|
||||
case 0x3C0:
|
||||
case 0x3C1:
|
||||
case 0x3C2:
|
||||
|
|
@ -1215,10 +1215,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x3C5:
|
||||
case 0x3C6:
|
||||
case 0x3C7:
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
second = ReadMemory((ushort)(pc + 1));
|
||||
bytesToAdvance = 2;
|
||||
return "XOR R" + register1 + ", " + string.Format("${0:X4}", second);
|
||||
mem = (byte)(opcode & 0x7);
|
||||
addr = ReadMemory((ushort)(pc + 1));
|
||||
addrToAdvance = 2;
|
||||
return "XOR R" + mem + ", " + string.Format("${0:X4}", addr);
|
||||
case 0x3C8:
|
||||
case 0x3C9:
|
||||
case 0x3CA:
|
||||
|
|
@ -1275,9 +1275,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x3FD:
|
||||
case 0x3FE:
|
||||
case 0x3FF:
|
||||
register1 = (byte)((opcode >> 3) & 0x7);
|
||||
register2 = (byte)(opcode & 0x7);
|
||||
return "XOR@ R" + register1 + ", R" + register2;
|
||||
mem = (byte)((opcode >> 3) & 0x7);
|
||||
dest = (byte)(opcode & 0x7);
|
||||
return "XOR@ R" + mem + ", R" + dest;
|
||||
}
|
||||
return UNKNOWN;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -35,8 +35,10 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
|
||||
public void Execute(int cycles)
|
||||
{
|
||||
byte register1, register2;
|
||||
int second, third, op1, op2, temp, result = 0;
|
||||
byte dest, src, mem;
|
||||
int decle2, decle3, result = 0;
|
||||
int ones, carry, status_word, lower, sign;
|
||||
ushort dest_value, src_value, mem_read, addr;
|
||||
PendingCycles += cycles;
|
||||
while (PendingCycles > 0)
|
||||
{
|
||||
|
|
@ -63,18 +65,17 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
break;
|
||||
case 0x004: // J, JE, JD, JSR, JSRE, JSRD
|
||||
// 0000:0000:0000:0100 0000:00rr:aaaa:aaff 0000:00aa:aaaa:aaaa
|
||||
second = ReadMemory(RegisterPC++);
|
||||
third = ReadMemory(RegisterPC++);
|
||||
decle2 = ReadMemory(RegisterPC++);
|
||||
decle3 = ReadMemory(RegisterPC++);
|
||||
// rr indicates the register into which to store the return address
|
||||
register1 = (byte)(((second >> 8) & 0x3) + 4);
|
||||
// ff indicates how to affect the Interrupt (I) flag in the CP1610
|
||||
op1 = second & 0x3;
|
||||
dest = (byte)(((decle2 >> 8) & 0x3) + 4);
|
||||
// aaaaaaaaaaaaaaaa indicates the address to where the CP1610 should Jump
|
||||
op2 = ((second << 8) & 0xFC00) | (third & 0x3FF);
|
||||
if (register1 != 0x7)
|
||||
addr = (ushort)(((decle2 << 8) & 0xFC00) | (decle3 & 0x3FF));
|
||||
if (dest != 0x7)
|
||||
// Store the return address.
|
||||
Register[register1] = (ushort)((RegisterPC + 1) & 0xFFFF);
|
||||
switch (op1)
|
||||
Register[dest] = (ushort)((RegisterPC + 1) & 0xFFFF);
|
||||
// ff indicates how to affect the Interrupt (I) flag in the CP1610
|
||||
switch (decle2 & 0x3)
|
||||
{
|
||||
case 0x1:
|
||||
FlagI = true;
|
||||
|
|
@ -86,7 +87,7 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
// Unknown opcode.
|
||||
throw new ArgumentException();
|
||||
}
|
||||
RegisterPC = (ushort)op2;
|
||||
RegisterPC = (ushort)addr;
|
||||
PendingCycles -= 12; TotalExecutedCycles += 12;
|
||||
break;
|
||||
case 0x005: // TCI
|
||||
|
|
@ -114,11 +115,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x00E:
|
||||
case 0x00F:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
result = (Register[register1] + 1) & 0xFFFF;
|
||||
dest = (byte)(opcode & 0x7);
|
||||
result = (Register[dest] + 1) & 0xFFFF;
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
break;
|
||||
// DECR
|
||||
|
|
@ -131,11 +132,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x016:
|
||||
case 0x017:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
result = (Register[register1] - 1) & 0xFFFF;
|
||||
dest = (byte)(opcode & 0x7);
|
||||
result = (Register[dest] - 1) & 0xFFFF;
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
break;
|
||||
// COMR
|
||||
|
|
@ -148,11 +149,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x01E:
|
||||
case 0x01F:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
result = Register[register1] ^ 0xFFFF;
|
||||
dest = (byte)(opcode & 0x7);
|
||||
result = (Register[dest] ^ 0xFFFF);
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
break;
|
||||
// NEGR
|
||||
|
|
@ -165,16 +166,16 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x026:
|
||||
case 0x027:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
op1 = Register[register1];
|
||||
temp = (op1 ^ 0xFFFF);
|
||||
result = temp + 1;
|
||||
dest = (byte)(opcode & 0x7);
|
||||
dest_value = Register[dest];
|
||||
ones = (dest_value ^ 0xFFFF);
|
||||
result = ones + 1;
|
||||
Calc_FlagC(result);
|
||||
Calc_FlagO_Add(temp, 1);
|
||||
Calc_FlagO_Add(ones, 1);
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
result &= 0xFFFF;
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
break;
|
||||
// ADCR
|
||||
|
|
@ -187,16 +188,16 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x02E:
|
||||
case 0x02F:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
op1 = Register[register1];
|
||||
op2 = FlagC ? 1 : 0;
|
||||
result = op1 + op2;
|
||||
dest = (byte)(opcode & 0x7);
|
||||
dest_value = Register[dest];
|
||||
carry = FlagC ? 1 : 0;
|
||||
result = dest_value + carry;
|
||||
Calc_FlagC(result);
|
||||
Calc_FlagO_Add(op1, op2);
|
||||
Calc_FlagO_Add(dest_value, carry);
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
result &= 0xFFFF;
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
break;
|
||||
// GSWD
|
||||
|
|
@ -205,15 +206,16 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x032:
|
||||
case 0x033:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
temp = ((FlagS ? 1 : 0) << 3) | ((FlagZ ? 1 : 0) << 2) | ((FlagO ? 1 : 0) << 1) | (FlagC ? 1 : 0);
|
||||
Register[register1] = (ushort)((temp << 12) | (temp << 4));
|
||||
dest = (byte)(opcode & 0x3);
|
||||
status_word = ((FlagS ? 1 : 0) << 3) | ((FlagZ ? 1 : 0) << 2) | ((FlagO ? 1 : 0) << 1) |
|
||||
(FlagC ? 1 : 0);
|
||||
Register[dest] = (ushort)((status_word << 12) | (status_word << 4));
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
break;
|
||||
// NOP
|
||||
case 0x034:
|
||||
case 0x035:
|
||||
throw new NotImplementedException();
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
break;
|
||||
// SIN
|
||||
case 0x036:
|
||||
|
|
@ -232,12 +234,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x03E:
|
||||
case 0x03F:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x7);
|
||||
op1 = Register[register1];
|
||||
FlagC = ((op1 & 0x80) != 0) ? true : false;
|
||||
FlagO = ((op1 & 0x40) != 0) ? true : false;
|
||||
FlagZ = ((op1 & 0x20) != 0) ? true : false;
|
||||
FlagS = ((op1 & 0x10) != 0) ? true : false;
|
||||
src = (byte)(opcode & 0x7);
|
||||
src_value = Register[src];
|
||||
FlagC = ((src_value & 0x80) != 0) ? true : false;
|
||||
FlagO = ((src_value & 0x40) != 0) ? true : false;
|
||||
FlagZ = ((src_value & 0x20) != 0) ? true : false;
|
||||
FlagS = ((src_value & 0x10) != 0) ? true : false;
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
break;
|
||||
// SWAP
|
||||
|
|
@ -250,24 +252,25 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x046:
|
||||
case 0x047:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
op1 = (opcode >> 3) & 0x1;
|
||||
op2 = Register[register1];
|
||||
temp = op2 & 0xFF;
|
||||
if (op1 == 0)
|
||||
dest = (byte)(opcode & 0x3);
|
||||
dest_value = Register[dest];
|
||||
lower = dest_value & 0xFF;
|
||||
if (((opcode >> 3) & 0x1) == 0)
|
||||
{
|
||||
// Single swap.
|
||||
result = (temp << 8) | ((op2 >> 8) & 0xFF);
|
||||
result = (lower << 8) | ((dest_value >> 8) & 0xFF);
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Double swap.
|
||||
result = (temp << 8) | temp;
|
||||
result = (lower << 8) | lower;
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
Calc_FlagS_7(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// SLL
|
||||
case 0x048:
|
||||
case 0x049:
|
||||
|
|
@ -278,10 +281,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x04E:
|
||||
case 0x04F:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
op1 = (opcode >> 3) & 0x1;
|
||||
result = Register[register1] << 1;
|
||||
if (op1 == 0)
|
||||
dest = (byte)(opcode & 0x3);
|
||||
result = Register[dest] << 1;
|
||||
if (((opcode >> 3) & 0x1) == 0)
|
||||
{
|
||||
// Single shift.
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
|
|
@ -294,7 +296,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
}
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// RLC
|
||||
case 0x050:
|
||||
case 0x051:
|
||||
|
|
@ -305,12 +308,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x056:
|
||||
case 0x057:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
op1 = (opcode >> 3) & 0x1;
|
||||
op2 = Register[register1];
|
||||
result = (op2 << 1) | (FlagC ? 1 : 0);
|
||||
FlagC = ((op2 & 0x8000) != 0);
|
||||
if (op1 == 0)
|
||||
dest = (byte)(opcode & 0x3);
|
||||
dest_value = Register[dest];
|
||||
result = (dest_value << 1) | (FlagC ? 1 : 0);
|
||||
FlagC = ((dest_value & 0x8000) != 0);
|
||||
if (((opcode >> 3) & 0x1) == 0)
|
||||
{
|
||||
// Single rotate.
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
|
|
@ -320,12 +322,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
// Double rotate.
|
||||
result <<= 1;
|
||||
result |= (FlagO ? 1 : 0);
|
||||
FlagO = ((op2 & 0x4000) != 0);
|
||||
FlagO = ((dest_value & 0x4000) != 0);
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// SLLC
|
||||
case 0x058:
|
||||
case 0x059:
|
||||
|
|
@ -336,12 +339,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x05E:
|
||||
case 0x05F:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
op1 = (opcode >> 3) & 0x1;
|
||||
op2 = Register[register1];
|
||||
result = op2 << 1;
|
||||
FlagC = ((op2 & 0x8000) != 0);
|
||||
if (op1 == 0)
|
||||
dest = (byte)(opcode & 0x3);
|
||||
dest_value = Register[dest];
|
||||
result = dest_value << 1;
|
||||
FlagC = ((dest_value & 0x8000) != 0);
|
||||
if (((opcode >> 3) & 0x1) == 0)
|
||||
{
|
||||
// Single shift.
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
|
|
@ -350,12 +352,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
{
|
||||
// Double shift.
|
||||
result <<= 1;
|
||||
FlagO = ((op2 & 0x4000) != 0);
|
||||
FlagO = ((dest_value & 0x4000) != 0);
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// SLR
|
||||
case 0x060:
|
||||
case 0x061:
|
||||
|
|
@ -366,10 +369,9 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x066:
|
||||
case 0x067:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
op1 = (opcode >> 3) & 0x1;
|
||||
result = Register[register1] >> 1;
|
||||
if (op1 == 0)
|
||||
dest = (byte)(opcode & 0x3);
|
||||
result = Register[dest] >> 1;
|
||||
if (((opcode >> 3) & 0x1) == 0)
|
||||
{
|
||||
// Single shift.
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
|
|
@ -382,7 +384,8 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
}
|
||||
Calc_FlagS_7(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// SAR
|
||||
case 0x068:
|
||||
case 0x069:
|
||||
|
|
@ -393,12 +396,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x06E:
|
||||
case 0x06F:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
op1 = (opcode >> 3) & 0x1;
|
||||
op2 = Register[register1];
|
||||
temp = op2 & 0x8000;
|
||||
result = (op2 >> 1) | temp;
|
||||
if (op1 == 0)
|
||||
dest = (byte)(opcode & 0x3);
|
||||
dest_value = Register[dest];
|
||||
sign = dest_value & 0x8000;
|
||||
result = (dest_value >> 1) | sign;
|
||||
if (((opcode >> 3) & 0x1) == 0)
|
||||
{
|
||||
// Single shift.
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
|
|
@ -407,12 +409,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
{
|
||||
// Double shift.
|
||||
result >>= 1;
|
||||
result |= temp;
|
||||
result |= sign;
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
Calc_FlagS_7(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// RRC
|
||||
case 0x070:
|
||||
case 0x071:
|
||||
|
|
@ -423,12 +426,11 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x076:
|
||||
case 0x077:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
op1 = (opcode >> 3) & 0x1;
|
||||
op2 = Register[register1];
|
||||
result = (op2 >> 1) | ((FlagC ? 1 : 0) << 15);
|
||||
FlagC = ((op2 & 0x1) != 0);
|
||||
if (op1 == 0)
|
||||
dest = (byte)(opcode & 0x3);
|
||||
dest_value = Register[dest];
|
||||
result = (dest_value >> 1) | ((FlagC ? 1 : 0) << 15);
|
||||
FlagC = ((dest_value & 0x1) != 0);
|
||||
if (((opcode >> 3) & 0x1) == 0)
|
||||
{
|
||||
// Single rotate.
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
|
|
@ -438,12 +440,13 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
// Double rotate.
|
||||
result >>= 1;
|
||||
result |= (FlagO ? 1 : 0) << 15;
|
||||
FlagO = ((op2 & 0x2) != 0);
|
||||
FlagO = ((dest_value & 0x2) != 0);
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
Calc_FlagS_7(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// SARC
|
||||
case 0x078:
|
||||
case 0x079:
|
||||
|
|
@ -454,13 +457,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x07E:
|
||||
case 0x07F:
|
||||
throw new NotImplementedException();
|
||||
register1 = (byte)(opcode & 0x3);
|
||||
op1 = (opcode >> 3) & 0x1;
|
||||
op2 = Register[register1];
|
||||
temp = op2 & 0x8000;
|
||||
result = (op2 >> 1) | temp;
|
||||
FlagC = ((op2 & 0x1) != 0);
|
||||
if (op1 == 0)
|
||||
dest = (byte)(opcode & 0x3);
|
||||
dest_value = Register[dest];
|
||||
sign = dest_value & 0x8000;
|
||||
result = (dest_value >> 1) | sign;
|
||||
FlagC = ((dest_value & 0x1) != 0);
|
||||
if (((opcode >> 3) & 0x1) == 0)
|
||||
{
|
||||
// Single shift.
|
||||
PendingCycles -= 6; TotalExecutedCycles += 6;
|
||||
|
|
@ -469,13 +471,14 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
{
|
||||
// Double shift.
|
||||
result >>= 1;
|
||||
result |= temp;
|
||||
FlagO = ((op2 & 0x2) != 0);
|
||||
result |= sign;
|
||||
FlagO = ((dest_value & 0x2) != 0);
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
Calc_FlagS_7(result);
|
||||
Calc_FlagZ(result);
|
||||
Register[register1] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// MOVR
|
||||
case 0x080:
|
||||
case 0x081:
|
||||
|
|
@ -1008,14 +1011,14 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x27D:
|
||||
case 0x27E:
|
||||
case 0x27F:
|
||||
register1 = (byte)((opcode >> 3) & 0x7);
|
||||
register2 = (byte)(opcode & 0x7);
|
||||
WriteMemory(Register[register1], Register[register2]);
|
||||
mem = (byte)((opcode >> 3) & 0x7);
|
||||
src = (byte)(opcode & 0x7);
|
||||
WriteMemory(Register[mem], Register[src]);
|
||||
// Stack mode.
|
||||
if (register1 == 0x6)
|
||||
if (mem == 0x6)
|
||||
RegisterSP--;
|
||||
// Immediate mode.
|
||||
if (register1 == 0x7)
|
||||
if (mem == 0x7)
|
||||
RegisterPC++;
|
||||
PendingCycles -= 9; TotalExecutedCycles += 9;
|
||||
break;
|
||||
|
|
@ -1086,12 +1089,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x2BD:
|
||||
case 0x2BE:
|
||||
case 0x2BF:
|
||||
register1 = (byte)((opcode >> 3) & 0x7);
|
||||
register2 = (byte)(opcode & 0x7);
|
||||
mem = (byte)((opcode >> 3) & 0x7);
|
||||
dest = (byte)(opcode & 0x7);
|
||||
if (!FlagD)
|
||||
{
|
||||
Register[register2] = ReadMemory(Register[register1]);
|
||||
if (register1 != 0x6)
|
||||
Register[dest] = ReadMemory(Register[mem]);
|
||||
if (mem != 0x6)
|
||||
{
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
|
|
@ -1103,15 +1106,15 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
else
|
||||
{
|
||||
// Double Byte Data.
|
||||
Register[register2] = (ushort)(ReadMemory(Register[register1]++) << 8);
|
||||
Register[register2] |= (ushort)(ReadMemory(Register[register1]) & 0xFF);
|
||||
Register[dest] = (ushort)(ReadMemory(Register[mem]++) << 8);
|
||||
Register[dest] |= (ushort)(ReadMemory(Register[mem]) & 0xFF);
|
||||
PendingCycles -= 10; TotalExecutedCycles += 10;
|
||||
}
|
||||
// Stack mode.
|
||||
if (register1 == 0x6)
|
||||
if (mem == 0x6)
|
||||
RegisterSP++;
|
||||
// Immediate mode.
|
||||
if (register1 == 0x7)
|
||||
if (mem == 0x7)
|
||||
RegisterPC++;
|
||||
break;
|
||||
// ADD
|
||||
|
|
@ -1181,12 +1184,12 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
case 0x2FD:
|
||||
case 0x2FE:
|
||||
case 0x2FF:
|
||||
register1 = (byte)((opcode >> 3) & 0x7);
|
||||
register2 = (byte)(opcode & 0x7);
|
||||
mem = (byte)((opcode >> 3) & 0x7);
|
||||
dest = (byte)(opcode & 0x7);
|
||||
if (!FlagD)
|
||||
{
|
||||
op1 = ReadMemory(Register[register1]);
|
||||
if (register1 != 0x6)
|
||||
mem_read = ReadMemory(Register[mem]);
|
||||
if (mem != 0x6)
|
||||
{
|
||||
PendingCycles -= 8; TotalExecutedCycles += 8;
|
||||
}
|
||||
|
|
@ -1198,25 +1201,24 @@ namespace BizHawk.Emulation.CPUs.CP1610
|
|||
else
|
||||
{
|
||||
// Double Byte Data.
|
||||
op1 = (ushort)(ReadMemory(Register[register1]++) << 8);
|
||||
op1 |= (ushort)(ReadMemory(Register[register1]) & 0xFF);
|
||||
mem_read = (ushort)(ReadMemory(Register[mem]++) << 8);
|
||||
mem_read |= (ushort)(ReadMemory(Register[mem]) & 0xFF);
|
||||
PendingCycles -= 10; TotalExecutedCycles += 10;
|
||||
}
|
||||
// Stack mode.
|
||||
if (register1 == 0x6)
|
||||
if (mem == 0x6)
|
||||
RegisterSP++;
|
||||
// Immediate mode.
|
||||
if (register1 == 0x7)
|
||||
if (mem == 0x7)
|
||||
RegisterPC++;
|
||||
break;
|
||||
op2 = Register[register2];
|
||||
result = op1 + op2;
|
||||
dest_value = Register[dest];
|
||||
result = mem_read + dest_value;
|
||||
Calc_FlagC(result);
|
||||
Calc_FlagO_Add(op1, op2);
|
||||
Calc_FlagO_Add(mem_read, dest_value);
|
||||
Calc_FlagS(result);
|
||||
Calc_FlagZ(result);
|
||||
result &= 0xFFFF;
|
||||
Register[register2] = (ushort)result;
|
||||
Register[dest] = (ushort)result;
|
||||
break;
|
||||
// SUB
|
||||
case 0x300:
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ namespace BizHawk.Emulation.Consoles.Intellivision
|
|||
{
|
||||
private ushort[] Intellicart = new ushort[65536];
|
||||
private bool[][] MemoryAttributes = new bool[32][];
|
||||
private int[][] FineAddresses = new int[32][];
|
||||
private ushort[][] FineAddresses = new ushort[32][];
|
||||
|
||||
private ushort[] CRC16_table =
|
||||
{
|
||||
|
|
@ -58,8 +58,7 @@ namespace BizHawk.Emulation.Consoles.Intellivision
|
|||
// Check to see if the header is valid.
|
||||
if (Rom[offset++] != 0xA8 || Rom[offset++] != (0xFF ^ Rom[offset++]))
|
||||
throw new ArgumentException();
|
||||
ushort crc;
|
||||
int expected;
|
||||
ushort crc, expected;
|
||||
// Parse for data segments.
|
||||
for (int segment = 0; segment < Rom[1]; segment++)
|
||||
{
|
||||
|
|
@ -68,22 +67,22 @@ namespace BizHawk.Emulation.Consoles.Intellivision
|
|||
byte upper_end = Rom[offset++];
|
||||
crc = UpdateCRC16(crc, upper_start);
|
||||
crc = UpdateCRC16(crc, upper_end);
|
||||
int start = upper_start << 8;
|
||||
int end = (upper_end << 8) | 0xFF;
|
||||
ushort start = (ushort)(upper_start << 8);
|
||||
ushort end = (ushort)((upper_end << 8) | 0xFF);
|
||||
// This range is invalid if it starts at a higher range than it ends.
|
||||
if (end < start)
|
||||
throw new ArgumentException();
|
||||
for (int addr = start; addr <= end; addr++)
|
||||
{
|
||||
int data;
|
||||
ushort data;
|
||||
byte high = Rom[offset++];
|
||||
byte low = Rom[offset++];
|
||||
crc = UpdateCRC16(crc, high);
|
||||
crc = UpdateCRC16(crc, low);
|
||||
data = (high << 8) | low;
|
||||
Intellicart[addr] = (ushort)data;
|
||||
data = (ushort)((high << 8) | low);
|
||||
Intellicart[addr] = data;
|
||||
}
|
||||
expected = (Rom[offset++] << 8) | Rom[offset++];
|
||||
expected = (ushort)((Rom[offset++] << 8) | Rom[offset++]);
|
||||
// Check if there is an invalid CRC.
|
||||
if (expected != crc)
|
||||
throw new ArgumentException();
|
||||
|
|
@ -116,19 +115,19 @@ namespace BizHawk.Emulation.Consoles.Intellivision
|
|||
else
|
||||
index = offset + 32 + (range >> 1);
|
||||
int range_start = range * 2048;
|
||||
int start = (((Rom[index] >> 4) & 0x07) << 8) + range_start;
|
||||
int end = (((Rom[index]) & 0x07) << 8) + 0xFF + range_start;
|
||||
ushort start = (ushort)((((Rom[index] >> 4) & 0x07) << 8) + range_start);
|
||||
ushort end = (ushort)((((Rom[index]) & 0x07) << 8) + 0xFF + range_start);
|
||||
// This range is invalid if it starts at a higher range than it ends.
|
||||
if (end < start)
|
||||
throw new ArgumentException();
|
||||
FineAddresses[range] = new int[2];
|
||||
FineAddresses[range] = new ushort[2];
|
||||
FineAddresses[range][0] = start;
|
||||
FineAddresses[range][1] = end;
|
||||
}
|
||||
crc = 0xFFFF;
|
||||
for (int index = 0; index < 48; index++)
|
||||
crc = UpdateCRC16(crc, Rom[offset++]);
|
||||
expected = (Rom[offset++] << 8) | (Rom[offset++] & 0xFF);
|
||||
expected = (ushort)((Rom[offset++] << 8) | (Rom[offset++] & 0xFF));
|
||||
// Check if there is an invalid CRC for the memory attributes / fine addresses.
|
||||
if (expected != crc)
|
||||
throw new ArgumentException();
|
||||
|
|
|
|||
Loading…
Reference in New Issue