68000: fix bug with ADDQ.W/SUBQ.W operating on address registers
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@ -239,17 +239,22 @@ namespace BizHawk.Emulation.CPUs.M68000
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}
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case 1: // word
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{
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short value = PeekValueW(mode, reg);
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int result = value + data;
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int uresult = (ushort)value + data;
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if (mode != 1)
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if (mode == 1)
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{
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int value = PeekValueL(mode, reg);
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WriteValueL(mode, reg, value+data);
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}
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else
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{
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short value = PeekValueW(mode, reg);
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int result = value + data;
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int uresult = (ushort)value + data;
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N = (result & 0x8000) != 0;
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Z = result == 0;
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V = result > short.MaxValue || result < short.MinValue;
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C = X = (uresult & 0x10000) != 0;
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WriteValueW(mode, reg, (short)result);
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}
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WriteValueW(mode, reg, (short)result);
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if (mode <= 1) PendingCycles -= 4;
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else PendingCycles -= 8 + EACyclesBW[mode, reg];
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return;
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@ -565,17 +570,22 @@ namespace BizHawk.Emulation.CPUs.M68000
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}
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case 1: // word
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{
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short value = PeekValueW(mode, reg);
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int result = value - data;
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int uresult = (ushort)value - data;
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if (mode != 1)
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if (mode == 1)
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{
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int value = PeekValueL(mode, reg);
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WriteValueL(mode, reg, value - data);
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}
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else
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{
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short value = PeekValueW(mode, reg);
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int result = value - data;
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int uresult = (ushort)value - data;
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N = (result & 0x8000) != 0;
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Z = result == 0;
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V = result > short.MaxValue || result < short.MinValue;
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C = X = (uresult & 0x10000) != 0;
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WriteValueW(mode, reg, (short)result);
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}
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WriteValueW(mode, reg, (short)result);
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if (mode <= 1) PendingCycles -= 4;
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else PendingCycles -= 8 + EACyclesBW[mode, reg];
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return;
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