[ARM] add handful of floating point instructions and most importantly: NOP!
This commit is contained in:
zeromus
parent
510e52271b
commit
e78708213c
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@ -163,10 +163,10 @@ namespace BizHawk.Emulation.CPUs.ARM
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}
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else opcode = opcode.Replace(crepl, "");
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if(opcode.Contains("{.size}"))
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{
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opcode = opcode.Replace("<{.size}>","." + args[argindex++].ToString());
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}
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if(opcode.Contains("{.fpsize}"))
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opcode = opcode.Replace("<{.fpsize}>",".F" + args[argindex++].ToString());
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if (opcode.Contains(".fpsize"))
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opcode = opcode.Replace("<.fpsize>", ".F" + args[argindex++].ToString());
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//---------
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string cpcomment = null;
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@ -215,6 +215,26 @@ namespace BizHawk.Emulation.CPUs.ARM
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break;
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}
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case "sdd":
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case "sdn":
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case "sdm":
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if ((bool)args[argindex++])
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item = "s" + args[argindex++].ToString();
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else
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item = "d" + args[argindex++].ToString();
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break;
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case "{sdd~sdn, }":
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{
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bool s = (bool)args[argindex++];
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uint rd = (uint)args[argindex++];
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uint rx = (uint)args[argindex++];
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if (disopt.showExplicitAccumulateRegisters || rd != rx)
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item = string.Format("{0}{1}, ", s ? "s" : "d", rd);
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else item = "";
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break;
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}
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case "fpscr": item = nstyle ? "fpscr" : "FPSCR"; break;
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case "const": item = string.Format("0x{0:x}", args[argindex++]); break;
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@ -228,7 +248,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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else item = string.Format(",#0x{0:x}", temp);
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break;
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}
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case "{,+/-#imm}":
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case "{, #+/-imm}":
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{
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uint temp = (uint)args[argindex + 1];
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if (temp == 0 && disopt.hideZeroOffset) item = "";
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@ -112,7 +112,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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opcode += "<c>";
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//we may want conditional logic here to control whether various registers are displayed (we used to have it, but i changed my mind)
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if (offset)
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return DISNEW(opcode, rt + ", [<Rn!><{,+/-#imm}>]", t, n, add, imm32);
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return DISNEW(opcode, rt + ", [<Rn!><{, #+/-imm}>]", t, n, add, imm32);
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else if (preindexed)
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return DISNEW(opcode, rt + ", [<Rn!>, <+/-><imm>]!", t, n, add, imm32);
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else if (postindex)
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@ -55,7 +55,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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.r("A==0 && op1 == #0x010", () => Execute_Unhandled("STRT on page A8-416"))
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.r("A==1 && op1 == #0x010 && B==0", () => Execute_Unhandled("STRT on page A8-416"))
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.r("A==0 && op1 == #xx0x1 && op1 != #0x011 && Rn != #1111", () => Execute_LDR_immediate_arm_A1())
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.r("A==0 && op1 == #xx0x1 && op1 != #0x011 && Rn == #1111", () => ExecuteArm_LDR_literal_A1())
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.r("A==0 && op1 == #xx0x1 && op1 != #0x011 && Rn == #1111", () => Execute_LDR_literal_A1())
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.r("A==1 && op1 == #xx0x1 && A != #0x011 && B==0", () => Execute_Unhandled("LDR (register) on page A8-124"))
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.r("A==0 && op1 == #0x011", () => Execute_Unhandled("LDRT on page A8-176"))
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.r("A==1 && op1 == #0x011 && B==0", () => Execute_Unhandled("LDRT on page A8-176"))
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@ -141,7 +141,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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return ExecuteCore_PUSH(Encoding.A2, registers, UnalignedAllowed);
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}
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uint ExecuteArm_LDR_literal_A1()
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uint Execute_LDR_literal_A1()
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{
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//A8.6.59
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//A8-122
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@ -182,7 +182,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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return ExecuteArm_DataProcessing_Immediate();
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if (op1 == _.b10000) return Execute_Unhandled("16-bit immediate load (MOV (immediate on page A8-193) //v6T2");
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if (op1 == _.b10100) return Execute_Unhandled("high halfword 16-bit immediate load (MOVT on page A8-200) //v6T2");
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if (CHK(op1, _.b11011, _.b10010)) return Execute_Unhandled("MSR (immediate), and hints on page A5-17");
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if (CHK(op1, _.b11011, _.b10010)) return ExecuteArm_MSR_immediate_and_hints();
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throw new InvalidOperationException("unexpected decoder fail");
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default:
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@ -190,6 +190,48 @@ namespace BizHawk.Emulation.CPUs.ARM
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}
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}
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uint ExecuteArm_MSR_immediate_and_hints()
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{
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Bit op = _.BIT22(instruction);
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uint op1 = (instruction >> 16) & 0xF;
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uint op2 = instruction & 0xFF;
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if (op == 0)
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{
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switch(op1)
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{
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case _.b0000:
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switch (op2)
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{
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case 0: return Execute_NOP_A1();
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case 1: return Execute_Unhandled("yield");
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case 2: return Execute_Unhandled("wfe");
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case 3: return Execute_Unhandled("wfi");
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case 4: return Execute_Unhandled("sev");
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default: return Execute_Unhandled("DBG");
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}
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case _.b0100:
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case _.b1000: case _.b1100:
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return Execute_Unhandled("MSR immediate");
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case _.b0001: case _.b0101:
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case _.b1001: case _.b1101:
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return Execute_Unhandled("MSR immediate");
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case _.b0010: case _.b0011:
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case _.b0110: case _.b0111:
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case _.b1010: case _.b1011:
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case _.b1110: case _.b1111:
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return Execute_Unhandled("MSR immediate");
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default: throw new InvalidOperationException("decode fail");
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}
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}
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else return Execute_Unhandled("MSR immediate");
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}
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uint Execute_NOP_A1()
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{
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//A8.6.110
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return ExecuteCore_NOP(Encoding.A1);
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}
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uint ExecuteArm_SynchronizationPrimitives()
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{
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uint op = (instruction >> 20) & 0xF;
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@ -562,7 +604,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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case _.b001:
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switch (op)
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{
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case _.b01: return ExecuteArm_BX_A1();
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case _.b01: return Execute_BX_A1();
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case _.b11: return Execute_Unhandled("ExecuteArm_CLZ");
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default:
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return Execute_Undefined();
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@ -588,16 +630,11 @@ namespace BizHawk.Emulation.CPUs.ARM
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} //switch(op2)
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}
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uint ExecuteArm_BX_A1()
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uint Execute_BX_A1()
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{
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//A8-62
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//A8.6.25
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uint Rm = Reg16(0);
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if (disassemble)
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return DIS("BX/c/", "/r0/", Rm);
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uint m = r[Rm];
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_BXWritePC(m);
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return 1;
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uint m = Reg16(0);
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return ExecuteCore_BX(Encoding.A1, m);
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}
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uint ExecuteArm_Media() { return Execute_Unhandled("ExecuteArm_Media"); }
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@ -720,7 +757,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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.r("op1==#00010x && coproc_special==#1", () => Execute_Unhandled("ExecuteArm_SIMD_VFP_64bit_xfer"))
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.r("op1==#000100 && coproc_special==#0", () => Execute_Unhandled("MCRR,MCRR2"))
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.r("op1==#000101 && coproc_special==#0", () => Execute_Unhandled("MRRC,MRRC2"))
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.r("op1==#10xxxx && op==0 && coproc_special==#1", () => Execute_Unhandled("VFP data-processing on page A7-24"))
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.r("op1==#10xxxx && op==0 && coproc_special==#1", () => ExecuteArm_VFP_DataProcessing())
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.r("op1==#10xxxx && op==0 && coproc_special==#0", () => Execute_Unhandled("CDP,CDP2 on page A8-68"))
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.r("op1==#10xxxx && op==1 && coproc_special==#1", () => ExecuteArm_ShortVFPTransfer())
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.r("op1==#10xxx0 && op==1 && coproc_special==#0", () => Execute_Unhandled("MCR,MCR2 on pageA8-186"))
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@ -739,6 +776,124 @@ namespace BizHawk.Emulation.CPUs.ARM
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return 1;
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}
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uint ExecuteArm_VFP_DataProcessing()
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{
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//A7.5
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uint opc1 = (instruction >> 20) & 0xF;
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uint opc2 = (instruction >> 16) & 0xF;
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uint opc3 = (instruction >> 6) & 3;
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if (opc1 == _.b0000 || opc1 == _.b0100) return Execute_Unhandled("VML, VMLS (floating point)");
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if (opc1 == _.b0001 || opc1 == _.b0101) return Execute_Unhandled("VNMLA, VNMLS, VNMUL");
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if (opc1 == _.b0010 || opc1 == _.b0110)
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if (opc3 == _.b01 || opc3 == _.b11) return Execute_Unhandled("VMUL (floating point)");
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else if (opc3 == _.b00 || opc3 == _.b10) return Execute_Unhandled("VMUL (floating point)");
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else throw new InvalidOperationException("decode fail");
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if (opc1 == _.b0011 || opc1 == _.b0111)
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if (opc3 == _.b00 || opc3 == _.b10) return Execute_VADD_floating_point_A2();
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else if (opc3 == _.b01 || opc3 == _.b11) return Execute_Unhandled("VSUB (floating point)");
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if (opc1 == _.b1000 || opc1 == _.b1100)
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if (opc3 == _.b00 || opc3 == _.b10) return Execute_Unhandled("VDIV");
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else throw new InvalidOperationException("unhandled opcode space..");
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if (opc1 == _.b1011 || opc1 == _.b1111)
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{
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if (opc3 == _.b00 || opc3 == _.b10) return Execute_Unhandled("VMOV (immediate)");
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if (opc2 == _.b0000 && opc3 == _.b01) return Execute_VMOV_register_A2();
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if (opc2 == _.b0000 && opc3 == _.b11) return Execute_Unhandled("VABS");
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if (opc2 == _.b0001 && opc3 == _.b01) return Execute_Unhandled("VNEG");
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if (opc2 == _.b0001 && opc3 == _.b11) return Execute_Unhandled("VSQRT");
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if (opc2 == _.b0010 || opc2 == _.b0011) return Execute_Unhandled("VCVTB, VCVTT (between half-precision and single precision)");
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if (opc2 == _.b0100 || opc2 == _.b0101) return Execute_Unhandled("VCMP, VCMPE");
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if (opc2 == _.b0111) return Execute_Unhandled("VCVT (between double precision and single precision)");
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if (opc2 == _.b1000) return Execute_Unhandled("VCVT, VCVTR (between floating point and integer)");
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if (opc2 == _.b1010 || opc2 == _.b1011) return Execute_Unhandled("VCVT (between floating point and fixed point)");
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if (opc2 == _.b1100 || opc2 == _.b1101) return Execute_Unhandled("VCVT, VCVTR (between floating point and integer)");
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if (opc2 == _.b1110 || opc2 == _.b1111) return Execute_Unhandled("VCVT (between floating point and fixed point)");
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}
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throw new InvalidOperationException("decoder fail");
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}
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uint Execute_VADD_floating_point_A2()
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{
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//A8.6.272
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if (_FPSCR_LEN() != _.b000 || _FPSCR_STRIDE() != _.b00) throw new NotImplementedException("see VFP vectors");
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const bool advsimd = false;
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Bit sz = _.BIT8(instruction);
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bool dp_operation = (sz == 1);
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uint D = _.BIT22(instruction);
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uint M = _.BIT5(instruction);
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uint N = _.BIT7(instruction);
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uint Vm = Reg16(0);
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uint Vd = Reg16(12);
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uint Vn = Reg16(16);
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uint d = dp_operation ? ((D << 4) | Vd) : ((Vd << 1) | D);
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uint n = dp_operation ? ((N << 4) | Vn) : ((Vn << 1) | N);
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uint m = dp_operation ? ((M << 4) | Vm) : ((Vm << 1) | M);
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return ExecuteCore_VADD_floating_point(Encoding.A2, dp_operation, advsimd, d, n, m);
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}
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uint Execute_VMOV_register_A2()
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{
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//A8.6.327
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if (_FPSCR_LEN() != _.b000 || _FPSCR_STRIDE() != _.b00) throw new NotImplementedException("see VFP vectors");
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Bit sz = _.BIT8(instruction);
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bool single_register = (sz == 0);
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const bool advsimd = false;
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uint d,m;
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uint Vd = Reg16(12);
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uint Vm = Reg16(0);
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uint D = _.BIT22(instruction);
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uint M = _.BIT5(instruction);
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uint regs = 0;
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if (single_register)
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{
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d = (Vd << 1) | D;
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m = (Vm << 1) | M;
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}
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else
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{
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d = (D << 4) | Vd;
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m = (M << 4) | Vm;
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regs = 1;
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}
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return ExecuteCore_VMOV_register(Encoding.A2, single_register, advsimd, d, m, regs);
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}
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uint Execute_VMOV_immediate_A2()
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{
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////A8.6.326
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//if (_FPSCR_LEN() != _.b000 || _FPSCR_STRIDE() != _.b00) throw new NotImplementedException("see VFP vectors");
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//Bit sz = _.BIT8(instruction);
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//bool single_register = (sz == 0);
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//const bool advsimd = false;
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//uint d;
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//uint Vd = Reg16(12);
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//uint D = _.BIT22(instruction);
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//uint imm32 = 0;
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//ulong imm64 = 0;
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//uint imm4H = (instruction>>16)&0xF;
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//uint imm4L = (instruction&0xF);
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//uint regs = 0;
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//if (single_register)
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//{
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// d = (Vd << 1) | D;
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// imm32 = _VFPExpandImm32((imm4H << 4) | imm4L);
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//}
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//else
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//{
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// d = (D << 4) | Vd;
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// imm64 = _VFPExpandImm64((imm4H << 4) | imm4L);
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// regs = 1;
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//}
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//return ExecuteCore_VMOV(Encoding.A2, single_register, advsimd, d, regs, imm32, imm64);
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return 1;
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}
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uint Execute_ExtensionRegister_LoadStore()
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{
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//A7.6 Extension register load/store instructions
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@ -781,7 +936,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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uint imm8 = instruction & 0xFF;
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uint imm32 = _ZeroExtend_32(imm8 << 2);
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uint Vd = Reg16(12);
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uint n = Reg16(0);
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uint n = Reg16(16);
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uint d = (Vd << 1) | D;
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return ExecuteCore_VLDR(Encoding.A1, single_reg, add, d, n, imm32);
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}
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@ -837,7 +992,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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Decoder_ExecuteArm_ShortVFPTransfer.Ensure(() => Decoder_ExecuteArm_ShortVFPTransfer
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.d("A", 3).d("L", 1).d("C", 1).d("B", 2)
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.r("L==0 && C==0 && A==#000", () => Execute_Unhandled("VMOV (between ARM core register and single-precision register) on page A8-648"))
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.r("L==0 && C==0 && A==#111", () => ExecuteArm_VMSR_A1())
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.r("L==0 && C==0 && A==#111", () => Execute_VMSR_A1())
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.r("L==0 && C==1 && A==#0xx", () => Execute_Unhandled("VMOV (ARM core register to scalar) on page A8-644"))
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.r("L==0 && C==1 && A==#1xx && B==#0x", () => Execute_Unhandled("VDUP (ARM core register) on page A8-594"))
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.r("L==1 && C==0 && A==#000", () => Execute_Unhandled("VMOV (between ARM core register and single-precision register) on page A8-648"))
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@ -854,7 +1009,7 @@ namespace BizHawk.Emulation.CPUs.ARM
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return 1;
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}
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uint ExecuteArm_VMSR_A1()
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uint Execute_VMSR_A1()
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{
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uint t = Reg16(12);
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if (t == 15 || (t == 13 && _CurrentInstrSet() != EInstrSet.ARM)) return _UNPREDICTABLE();
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@ -211,6 +211,17 @@ namespace BizHawk.Emulation.CPUs.ARM
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return 1;
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}
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//A8.6.25 BX
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uint ExecuteCore_BX(Encoding encoding, uint m)
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{
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if (disassemble)
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return DISNEW("BX<c>", "<rm>", m);
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_BXWritePC(r[m]);
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return 1;
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}
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//A8.6.35 CMP (immediate)
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uint ExecuteCore_CMP_immediate(Encoding encoding, uint n, uint imm32)
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{
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@ -588,6 +599,14 @@ namespace BizHawk.Emulation.CPUs.ARM
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return 0;
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}
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//A8.6.110 NOP
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uint ExecuteCore_NOP(Encoding encoding)
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{
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if (disassemble)
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return DISNEW("NOP<c>", "");
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return 1;
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}
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//A8.6.113 ORR (immediate)
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uint ExecuteCore_ORR_immediate(Encoding encoding, uint n, uint d, bool setflags, uint imm32, Bit carry)
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{
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@ -1007,10 +1026,73 @@ namespace BizHawk.Emulation.CPUs.ARM
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return 1;
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}
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//A8.6.272 VADD (floating point)
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uint ExecuteCore_VADD_floating_point(Encoding encoding, bool dp_operation, bool advsimd, uint d, uint n, uint m)
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{
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if (advsimd) throw new NotImplementedException("VMOV reg adv simd :(");
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if (disassemble)
|
||||
return DISNEW("VADD<c><.fpsize>", "<{SDd~SDn, }><SDn>, <SDm>", dp_operation ? 64 : 32, !dp_operation, d, n, !dp_operation, n, !dp_operation, m);
|
||||
|
||||
if (advsimd)
|
||||
{
|
||||
}
|
||||
else
|
||||
{
|
||||
if (dp_operation)
|
||||
D[d] = _FPAdd(D[n], D[m], true);
|
||||
else
|
||||
S[d] = _FPAdd(S[n], S[m], true);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
//A8.6.320 VLDR
|
||||
uint ExecuteCore_VLDR(Encoding encoding, bool single_reg, bool add, uint d, uint n, uint imm32)
|
||||
{
|
||||
throw new NotImplementedException("TODO");
|
||||
if (disassemble)
|
||||
return DISNEW("VLDR<c>", "<SDd>, [<rn!><{, #+/-imm}>]", single_reg, d, n, add, imm32);
|
||||
|
||||
_CheckVFPEnabled(true);
|
||||
_NullCheckIfThumbEE(n);
|
||||
uint @base = (n==15)?_Align(PC,4):r[n];
|
||||
uint address = add ? (@base + imm32) : (@base - imm32);
|
||||
if (single_reg)
|
||||
S[d] = MemA_ReadSingle(address);
|
||||
else
|
||||
D[d] = MemA_ReadDouble(address);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
//A8.6.326 VMOV (immediate)
|
||||
uint ExecuteCore_VMOV_immediate(Encoding encoding, bool single_register, bool advsimd, uint d, uint regs, float imm32, double imm64)
|
||||
{
|
||||
if (advsimd) throw new NotImplementedException("VMOV imm adv simd :(");
|
||||
throw new NotImplementedException("ExecuteCore_VMOV_immediate");
|
||||
|
||||
//if(disassemble)
|
||||
// return DISNEW("VMOV<c><.fpsize>", "<SDd>", single_register?32:64, single_register, d
|
||||
return 1;
|
||||
}
|
||||
|
||||
//A8.6.327 VMOV (register)
|
||||
uint ExecuteCore_VMOV_register(Encoding encoding, bool single_register, bool advsimd, uint d, uint m, uint regs)
|
||||
{
|
||||
if (advsimd) throw new NotImplementedException("VMOV reg adv simd :(");
|
||||
|
||||
if (disassemble)
|
||||
return DISNEW("VMOV<c><.fpsize>", "<SDd>, <SDm>", single_register ? 32 : 64, single_register, d, single_register, m);
|
||||
|
||||
_CheckAdvSIMDOrVFPEnabled(true, advsimd);
|
||||
|
||||
if (single_register)
|
||||
S[d] = S[m];
|
||||
else for (uint r = 0; r <= regs - 1; r++)
|
||||
D[d + r] = D[m + r];
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
//A8.6.336 VMSR
|
||||
|
|
@ -1027,7 +1109,7 @@ namespace BizHawk.Emulation.CPUs.ARM
|
|||
uint ExecuteCore_VPUSH(Encoding encoding, bool single_regs, uint d, uint regs, uint imm32)
|
||||
{
|
||||
if (disassemble)
|
||||
return DISNEW("VPUSH<c><{.size}>", "<list>", single_regs ? 32 : 64, single_regs, d, regs);
|
||||
return DISNEW("VPUSH<c><{.fpsize}>", "<list>", single_regs ? 32 : 64, single_regs, d, regs);
|
||||
|
||||
_CheckVFPEnabled(true);
|
||||
_NullCheckIfThumbEE(13);
|
||||
|
|
|
|||
|
|
@ -89,6 +89,13 @@ namespace BizHawk.Emulation.CPUs.ARM
|
|||
return bus.Read32(AT.READ, addr);
|
||||
}
|
||||
|
||||
ulong MemA_Read64(uint addr)
|
||||
{
|
||||
ulong ret = MemA_Read32(addr);
|
||||
ret |= (((ulong)MemA_Read32(addr + 4)) << 32);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void _SetExclusiveMonitors(uint address, int size)
|
||||
{
|
||||
//TODO!!! boring!!
|
||||
|
|
@ -106,6 +113,16 @@ namespace BizHawk.Emulation.CPUs.ARM
|
|||
MemA_Write32(addr,float_downcast(val));
|
||||
}
|
||||
|
||||
float MemA_ReadSingle(uint addr)
|
||||
{
|
||||
return float_upcast(MemA_Read32(addr));
|
||||
}
|
||||
|
||||
double MemA_ReadDouble(uint addr)
|
||||
{
|
||||
return double_upcast(MemA_Read64(addr));
|
||||
}
|
||||
|
||||
void MemA_WriteDouble(uint addr, double val)
|
||||
{
|
||||
ulong uval = double_downcast(val);
|
||||
|
|
@ -443,6 +460,78 @@ namespace BizHawk.Emulation.CPUs.ARM
|
|||
return result;
|
||||
}
|
||||
|
||||
float _FPAdd(float op1, float op2, bool fpscr_controlled)
|
||||
{
|
||||
//TODO
|
||||
return op1 + op2;
|
||||
}
|
||||
|
||||
double _FPAdd(double op1, double op2, bool fpscr_controlled)
|
||||
{
|
||||
//TODO
|
||||
return op1 + op2;
|
||||
}
|
||||
|
||||
bool _CheckAdvSIMDOrVFPEnabled(bool x, bool y)
|
||||
{
|
||||
//TODO
|
||||
return true;
|
||||
}
|
||||
|
||||
static uint[] __VFPExpandImm32_table;
|
||||
static uint __VFPExpandImm32_calc(uint imm8)
|
||||
{
|
||||
uint a = _.BIT7(imm8);
|
||||
uint B = _.BIT6(imm8)^1;
|
||||
uint b = _.BIT6(imm8);
|
||||
b |= (b << 1); //replicated to 2 bits
|
||||
b |= (b << 2); //replicated to 4 bits
|
||||
b |= (b << 1); //replicated to 5 bits
|
||||
uint cdefgh = imm8 & 0x3F;
|
||||
|
||||
return (a<<31)|(B<<30)|(b<<29)|(cdefgh<<24);
|
||||
}
|
||||
|
||||
static ulong[] __VFPExpandImm64_table;
|
||||
static ulong __VFPExpandImm64_calc(uint imm8)
|
||||
{
|
||||
uint a = _.BIT7(imm8);
|
||||
uint B = _.BIT6(imm8) ^ 1;
|
||||
uint b = _.BIT6(imm8);
|
||||
b |= (b << 1); //replicated to 2 bits
|
||||
b |= (b << 2); //replicated to 4 bits
|
||||
b |= (b << 4); //replicated to 8 bits
|
||||
uint cdefgh = imm8 & 0x3F;
|
||||
|
||||
uint uintret = (a << 31) | (B << 30) | (b << 29) | (cdefgh << 20);
|
||||
ulong ulongret = uintret << 32;
|
||||
return ulongret;
|
||||
}
|
||||
|
||||
uint _VFPExpandImm32(uint imm8)
|
||||
{
|
||||
if(__VFPExpandImm32_table == null)
|
||||
{
|
||||
__VFPExpandImm32_table = new uint[256];
|
||||
for(uint i=0;i<256;i++)
|
||||
__VFPExpandImm32_table[i] = __VFPExpandImm32_calc(i);
|
||||
}
|
||||
|
||||
return __VFPExpandImm32_table[imm8];
|
||||
}
|
||||
|
||||
ulong _VFPExpandImm64(uint imm8)
|
||||
{
|
||||
if (__VFPExpandImm64_table == null)
|
||||
{
|
||||
__VFPExpandImm64_table = new ulong[256];
|
||||
for (uint i = 0; i < 256; i++)
|
||||
__VFPExpandImm64_table[i] = __VFPExpandImm64_calc(i);
|
||||
}
|
||||
|
||||
return __VFPExpandImm64_table[imm8];
|
||||
}
|
||||
|
||||
uint _ARMExpandImm(uint imm12)
|
||||
{
|
||||
//A5-10
|
||||
|
|
|
|||
|
|
@ -113,18 +113,29 @@ namespace BizHawk.Emulation.CPUs.ARM
|
|||
float[] S = new float[32];
|
||||
double[] D = new double[16];
|
||||
|
||||
unsafe uint float_downcast(float f)
|
||||
unsafe static uint float_downcast(float f)
|
||||
{
|
||||
float* fp = &f;
|
||||
return *(uint*)fp;
|
||||
}
|
||||
|
||||
unsafe ulong double_downcast(double f)
|
||||
unsafe static float float_upcast(uint f)
|
||||
{
|
||||
uint* fp = &f;
|
||||
return *(float*)fp;
|
||||
}
|
||||
|
||||
unsafe static ulong double_downcast(double f)
|
||||
{
|
||||
double* fp = &f;
|
||||
return *(ulong*)fp;
|
||||
}
|
||||
|
||||
unsafe static double double_upcast(ulong f)
|
||||
{
|
||||
ulong* fp = &f;
|
||||
return *(double*)fp;
|
||||
}
|
||||
|
||||
public uint SP { get { return r[13]; } set { r[13] = value; } }
|
||||
public uint LR { get { return r[14]; } set { r[14] = value; } }
|
||||
|
|
@ -140,6 +151,8 @@ namespace BizHawk.Emulation.CPUs.ARM
|
|||
|
||||
|
||||
uint FPSCR;
|
||||
uint _FPSCR_LEN() { return 0; }
|
||||
uint _FPSCR_STRIDE() { return 0; }
|
||||
|
||||
public ARM(ARM_SYS sys, ARM_BUS bus)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue