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6,460 Commits 3 Branches 7 Tags 90 MiB
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4638 Commits

Author SHA1 Message Date
zilmar 87c732b65d Core: update CX86RecompilerOps::COP1_D_NEG 2024-03-21 17:14:00 +10:30
zilmar ece5e30a80 Core: create a function to handle .d recompiler opcodes that use fd and fs 2024-03-21 17:13:16 +10:30
zilmar 5133d47502 Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode 2024-03-14 18:12:58 +10:30
zilmar 98b1bddc64 Core: Get COP1_D_ADD, COP1_D_SUB, COP1_D_DIV, COP1_D_ABS, COP1_D_SQRT 2024-03-07 21:12:57 +10:30
zilmar 97ec1f533b Core: Make sure precision is set to 53bit 2024-03-07 20:52:24 +10:30
zilmar 190c408019 Core: Fix clang formatting in x86/x86RecompilerOps.cpp 2024-02-29 16:06:56 +10:30
zilmar f7aa6ef6cb Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions 2024-02-29 15:16:29 +10:30
zilmar 25dc3ed36f Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes 2024-02-29 15:13:14 +10:30
zilmar d2649f7a13 Core: Some clean up recompiler ops 2024-02-22 19:56:23 +10:30
zilmar fae0b81e21 Core: Have CX86RegInfo::Map_TempReg generate a BreakPoint if it mapping a protected register 2024-02-22 19:41:10 +10:30
zilmar e082cd55df Core: Get COP1_D_TRUNC_W to work in recompiler 2024-02-15 21:08:49 +10:30
zilmar 2559d23592 Core: Make sure CX86RecompilerOps::CompileInitFpuOperation clears flag for FE_INVALID 2024-02-15 21:02:27 +10:30
zilmar 46f6fae40f Core: get CompileCheckFPUInput to be able to handle 32bit and 64bit 2024-02-15 21:00:12 +10:30
zilmar 2014237ed6 Core: Update Round.w.s, trunc.w.s, ceil.w.s, floor.w.s to work with exceptions in the recompiler 2024-02-08 19:34:14 +10:30
zilmar ad1a2a2d9a Core: Update neg.s for the recompiler 2024-02-01 18:17:03 +10:30
zilmar b6671adf5d Core: Update abs.s for recompiler 2024-02-01 18:15:33 +10:30
zilmar bc3fe0fe16 Core: Handle FP Status Reg being mapped better 2024-01-25 18:46:39 +10:30
zilmar 7707f9c7b2 Core: Fix up mov.s and mov.d for correct behaviour in the recompiler 2024-01-25 16:25:06 +10:30
zilmar 272144dc37 Core: check timer on cop1 unusable 2024-01-25 16:23:03 +10:30
zilmar f0f44c67f4 Core: Make mov.s the same as mov.d 2024-01-25 15:32:56 +10:30
zilmar 7ed94b653e Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions 2024-01-18 17:09:27 +10:30
zilmar 2231e8d6c0 Core: Remove usage of fpclassify from R4300iOp::CheckFPUResult64 2024-01-18 16:53:14 +10:30
zilmar 71067ccdc4 Rsp: Change how SP_SEMAPHORE_REG to how it use to be before adding multithread RSP 2024-01-11 18:17:05 +10:30
zilmar 5c56f9df83 RSP: Update the size of the skip in the length for DMA 2024-01-11 17:50:23 +10:30
zilmar 4dc3e35bb4 Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions 2024-01-04 16:51:11 +10:30
zilmar f8089f565e Core: Unmap FPU_Float with writing to m_FPR_UDW 2024-01-04 14:40:42 +10:30
zilmar 552b8f744a Core: update Format_Name to match FPU_STATE 2024-01-04 13:11:21 +10:30
zilmar 6ca8333d39 Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions 2024-01-04 12:39:51 +10:30
zilmar c9d2bbd221 Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped 2024-01-04 12:37:06 +10:30
zilmar 0998f0ff0e Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer 2024-01-04 12:32:55 +10:30
zilmar 23cff4d7c5 Core: Add x86 asm opcode Jnp 2024-01-04 12:31:26 +10:30
zilmar 91a8a828d7 Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW 2024-01-04 12:01:21 +10:30
zilmar 320769d991 Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr 2024-01-04 10:33:07 +10:30
zilmar dafa1fb24d Core: Have COP1_W_CVT_S handle the initialization of exceptions 2023-12-28 11:19:06 +10:30
zilmar 17288c90c0 Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32 2023-12-28 10:23:18 +10:30
zilmar e2306e3541 Core: Get COP1_S_CVT_W to handle inexact 2023-12-28 09:21:53 +10:30
zilmar 8399fdb893 Core: Clear the Divide-by-zero flag 2023-12-21 21:24:33 +10:30
zilmar d14a639a62 Core: Implement COP1_S_DIV with fpu exceptions 2023-12-21 14:11:29 +10:30
zilmar 8e54ec8c8e Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis 2023-12-21 14:10:21 +10:30
zilmar b263ee10b0 Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0 2023-12-21 10:41:16 +10:30
zilmar 1810bfda5c Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops 2023-12-21 10:38:49 +10:30
zilmar 2c1610cfe2 Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode 2023-12-21 10:37:27 +10:30
zilmar 6610ae3058 Core: Have R4300iInstruction in CRecompilerOpsBase 2023-12-21 10:34:03 +10:30
zilmar 8e3fb3e302 Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference 2023-12-21 10:26:10 +10:30
zilmar c8e73ba18e Core: Handle unaligned SW exception in the recompiler 2023-12-14 23:04:26 +10:30
zilmar 972943cff7 Core: Allow LW to R0 be able to generate an exception 2023-12-14 17:21:52 +10:30
zilmar 89a6eaf9d1 Core: Add RecordLLAddress for 32bit register pointer 2023-12-14 13:52:15 +10:30
zilmar 67f5e4f854 Core: in LL for recompiler handle storing the address in COP[17] 2023-12-14 13:10:20 +10:30
zilmar d5a5f4cdac Core: Have Store Instruc rdb and user rdb matching 2023-12-14 12:21:03 +10:30
zilmar 5fec3f8d31 Core: remove the global of g_TLB 2023-12-14 12:09:24 +10:30
zilmar c67f3f0e97 Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it 2023-12-14 11:18:07 +10:30
zilmar 15175d3fe2 Core: Fix bug in not creating save state correctly 2023-12-07 17:43:48 +10:30
zilmar de1288bdca Core: remove try/catch around Interpreter cpu 2023-11-30 21:15:14 +10:30
zilmar df56964c96 Android: Remove unneeded log call 2023-11-30 21:13:27 +10:30
zilmar 5671f2b759 Android: Update how Addu cause android studio was not sign extending result 2023-11-30 21:12:53 +10:30
Derek "Turtle" Roe acbb8f85a8
Fix typo in support window code (#2395) 
* Fix typo in support window

* Fix the typo for real
 2023-11-23 22:54:19 +10:30
zilmar 01673dac8d Core: Change TriggerAddressException to SetVPN an R of entry hi in one call 2023-11-23 14:20:48 +10:30
zilmar d47b49d4b5 Core: Fix clang issue 2023-11-16 18:24:47 +10:30
zilmar 542afc4514 Core: remove some accidental added debug code 2023-11-16 18:16:35 +10:30
zilmar ee714e2462 Core: On unmap base addresses reset to the correct address 2023-11-16 18:14:15 +10:30
zilmar 8f4f434820 Core: Get Fast tlb to just be 32bit 2023-11-16 17:11:05 +10:30
zilmar dcb6969067 Core: Have entryHI use functions to set/get parts 2023-11-16 09:19:24 +10:30
zilmar a0130ff896 Core: Convert %I64U to %llx 2023-11-16 09:03:32 +10:30
zilmar e46ffde6b3 fix clang formatting 2023-11-09 12:59:40 +10:30
zilmar 296b7cf1cf Android: Force RSP to be interpret 2023-11-09 12:45:36 +10:30
zilmar 0c8b10bbc7 Android: Get RSP core to compile on android 2023-11-09 11:53:06 +10:30
zilmar 09cc3442a2 Android: fix compile bug 2023-11-02 20:27:38 +10:30
zilmar 6fbc5c0264 Android: Move hle audio code in to main rsp plugin 2023-11-02 20:06:58 +10:30
zilmar e6edbc6c82 Fix clang formatting 2023-10-27 10:14:21 +10:30
zilmar 4770d29ec0 Core: Get system events to be internal not global 2023-10-26 19:59:11 +10:30
zilmar d3f4132770 Android: When listing a rom not in rdb, use game file instead 2023-10-26 11:18:24 +10:30
zilmar b74e21d056 Android: Show base dir to splash logs when starting 2023-10-26 11:17:49 +10:30
zilmar bf480623bd [Android] Add Android/Bridge to clang checking 2023-10-26 11:05:20 +10:30
zilmar 8f062975c3 Core: improve DisplayControlRegHandler::Write32 2023-10-19 19:28:38 +10:30
zilmar d6a2ae80c1 Core: Remove SystemRegisters 2023-10-19 14:56:53 +10:30
zilmar d58168bcb9 Core: R4300iOp access the registers directly, not through CSystemRegisters 2023-10-19 12:52:33 +10:30
zilmar 4d78f56aa2 Core: In R4300iOp have a member variable for system, reg, mmu 2023-10-19 12:31:26 +10:30
zilmar ae0097550f Core: Make R4300iOp opcodes not static 2023-10-19 11:43:32 +10:30
zilmar 7f42f70283 Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static 2023-10-19 10:28:25 +10:30
zilmar d3edbf6dda Core: move CInterpreterCPU into R4300iOp 2023-10-19 09:32:42 +10:30
zilmar d4dbc5a3f4 Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio 2023-10-14 11:53:35 +10:30
zilmar 00c5057b17 Core: Make sure precision is correct for COP1_D_SQRT 2023-10-13 00:16:14 +10:30
zilmar 3a68d3d92a Core: LL/LLD store address 2023-10-12 19:55:29 +10:30
zilmar a6405cfa2d Core: Add masking around DPC_START_REG/DPC_END_REG 2023-10-12 17:50:58 +10:30
zilmar 4e71221147 Core: Fix up FPU mode register location 2023-10-12 14:53:44 +10:30
zilmar befa57924d Core: Fix clang compile issues 2023-10-05 15:01:09 +10:30
zilmar f73c3708a5 Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty 2023-10-05 14:45:17 +10:30
zilmar e74e8f6a23 Core: Have load/store ops be able to use 64bit addresses 2023-10-05 14:28:32 +10:30
zilmar 9f07fe2aac Core: Get tlb addresses to be 64bit 2023-10-05 13:42:31 +10:30
zilmar 4b844495b7 Core: Have save states handle COP0/TLB being 64bit now 
Core: Clean up tlb class
 2023-10-05 13:10:45 +10:30
zilmar 35105e814e Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss 2023-10-05 09:54:41 +10:30
zilmar b7311cc611 Core: Change Non memory load/store to not use tlb 2023-10-05 09:32:45 +10:30
zilmar a975af0e3c Rsp: only use alignas for Visual Studio 2023-09-28 16:18:39 +09:30
zilmar dd7ec63dd9 Rsp: Change usage of alignas to try and fix android build 2023-09-28 15:53:46 +09:30
zilmar 7e249d22b1 Try to fix android build 2023-09-28 15:25:34 +09:30
zilmar 46e6e54f24 RSP: improve running RSP multithreaded 2023-09-28 14:46:36 +09:30
zilmar 15e6e460d2 Rsp: Clean up VRCP, VRCPL, VRCPH, VRSQ, VRSQL, VRSQH 2023-09-28 13:39:23 +09:30
zilmar 3c52d8e2e3 RSP: use vt instead of rt when using RSP_Vect 2023-09-28 11:57:29 +09:30
zilmar 0bd6a96118 RSP: fix display of VRCP instruction 2023-09-28 11:54:50 +09:30
zilmar b1240072c6 RSP: move Enter_RSP_Register_Window & UpdateRSPRegistersScreen function definition out of RSP core 2023-09-28 11:53:57 +09:30
zilmar ac3e0f83d1 Rsp: Use RSP Register Handler 2023-09-28 11:52:06 +09:30
zilmar bd1ec4ff0f Core: Create a setting for RDRAM Size that plugins can read 2023-09-28 07:29:11 +09:30
zilmar 99417fc5d9 Core: reset run event in CRSP_Plugin after rom close 2023-09-28 07:19:20 +09:30
zilmar f817becf9c Core: Create a handler for RSP registers that is accessible to the core and the RSP 2023-09-28 07:03:01 +09:30
zilmar 03e13455f9 Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot 2023-09-28 06:39:39 +09:30
zilmar 2caa457d02 Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue 
Update counter before mfc0 x, count
 2023-09-22 11:01:46 +09:30
zilmar 10d2b77d7c Core: Try to fix android build 2023-09-21 20:13:41 +09:30
zilmar aadcca7528 Core: Fix clang issue 2023-09-21 18:40:27 +09:30
zilmar 6307888be4 Core: fix up exception generator functions 2023-09-21 18:07:56 +09:30
zilmar 32ff820a03 RSP: clean up vector compare ops (VLT, VEQ, VNE, VGE, VCH) 2023-09-21 15:51:16 +09:30
zilmar dc95d2f7a4 RSP: Clean up vector ops (VADD, VSUB, VABS, VSUBC, VMRG, VAND, VNAND, VOR, VNOR, VXOR, VNXOR) 2023-09-21 15:44:07 +09:30
zilmar 174e751a4a RSP: Fix up load ops (LUV, LHV, LFV, LTV) 2023-09-21 15:30:07 +09:30
zilmar bdaf8cf78c RSP: Clean up store vector ops (SHV, SFV, STV, SWV) 2023-09-21 15:25:45 +09:30
zilmar 5dcc7e200f Rsp: Move InitilizeRSPRegisters and InitilizeRSP into rsp-core 2023-09-21 15:16:26 +09:30
zilmar 42a944c660 RSP: Setup option to run in a thread 2023-09-21 14:25:07 +09:30
zilmar c4abebe201 Core: Update <Project64-plugin-spec\ to <Project64-plugin-spec/ 2023-09-21 14:13:08 +09:30
zilmar f3d6d3fc7c Core: for tlb miss only use special address when address is not defined 2023-09-14 18:39:15 +09:30
zilmar e0c125e837 Core: Fix clang issue 2023-09-14 16:33:20 +09:30
zilmar c02858c7a0 Core: Add LLD opcode 2023-09-14 16:31:37 +09:30
zilmar f559aed2ad Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function 2023-09-14 16:23:26 +09:30
zilmar ae4af8746b Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss 2023-09-14 13:09:11 +09:30
zilmar 8b14b6d7d1 Core: Move InitRegisters to register class 2023-09-14 12:01:16 +09:30
zilmar a5a4873e84 Core: Have CRegisters::DoAddressError to not directly modify program counter 2023-09-14 11:37:21 +09:30
zilmar 2d09178449 Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions 2023-09-14 11:15:42 +09:30
zilmar 5da5dab3c5 Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC 2023-09-14 11:09:28 +09:30
zilmar fcd7257adc Core: Change COP0 Status register to a struct breaking up the bits 2023-09-14 10:23:36 +09:30
zilmar 9ffd87168a Core: DisplayControlRegHandler::Read32 read more of the registers 2023-09-14 09:40:11 +09:30
zilmar 002f2e17c3 RSP: Clean up code for vector multiple ops 2023-09-07 11:54:36 +09:30
zilmar 4e9a692449 RSP: Add RSP_Vector_VRNDP 2023-09-07 11:41:17 +09:30
zilmar 0cadbe0f70 RSP: Add clamp16 2023-09-07 11:31:31 +09:30
zilmar af1c0c2b55 RSP: Add Vmulq 2023-09-07 11:30:15 +09:30
zilmar d468b863c2 Rsp: add vnop for vnull 2023-09-07 11:29:16 +09:30
zilmar 8b71ef3bc1 RSP: Add RSP_Vector_Reserved 2023-09-07 11:23:35 +09:30
zilmar ab67374c8a RSP: Update the display of RSP opcodes in debugger 2023-09-07 11:19:44 +09:30
zilmar 4f74dc4bb0 Rsp: Update display of vector in debugger 2023-09-07 11:17:08 +09:30
zilmar ab03916a70 Core: let the stack pointer equal end of rdram 2023-09-07 11:13:54 +09:30
zilmar 7199096748 Core: Merge CheckFPUException into CheckFPUResult64 2023-08-31 18:52:34 +09:30
zilmar 91d1c6e237 Core: Add fpu exceptions to COP1_S_MUL 2023-08-31 11:09:48 +09:30
zilmar 2f7a35613f Core: Add exception to COP1_S_SUB 2023-08-31 10:54:41 +09:30
zilmar c28c6bb4a1 Core: Add fpu exceptions to COP1_S_ADD 2023-08-31 10:08:49 +09:30
zilmar 416c85ecda Core: some code clean up of Load_FPR_ToTop 2023-08-31 09:30:05 +09:30
zilmar 2dcfcf250d Core: Do not force unmapping of fpr registers before CX86RegInfo::BeforeCallDirect(void) 2023-08-31 09:28:23 +09:30
zilmar e49438cdab Core: Add exit reason exception 2023-08-30 12:16:07 +09:30
zilmar 703ad4049a PluginRSP: declare windows.h before asset.h 2023-08-30 12:15:36 +09:30
zilmar 41fa1fd5dd Core: use m_TLB_WriteMap not m_TLB_ReadMap for NonMemory 2023-08-30 11:35:53 +09:30
zilmar 625f532d73 RSP: use __debugbreak not DebugBreak 2023-08-24 10:44:45 +09:30
zilmar 47f14016e6 RSP: Set RSP_JumpTo before register in JALR, BLTZAL, BGEZAL 2023-08-24 10:35:51 +09:30
zilmar ae9912b068 RSP: Clean up VCR 2023-08-24 10:31:26 +09:30
zilmar 7db5876927 RSP: Clean up VCL 2023-08-24 10:07:05 +09:30
zilmar 9dab3481ae RSP: Add class to wrap around RSP flag 2023-08-24 08:00:29 +09:30