Commit Graph

4638 Commits

Author SHA1 Message Date
zilmar 90c0beb01e RSP: Add Compile_Vector_Reserved 2024-06-20 17:34:37 +09:30
zilmar 35aeeb6285 RSP: Handle writing to r0 better in recompiler 2024-06-20 17:28:51 +09:30
zilmar bb042406be RSP: Add const to mmx and sse terms 2024-06-13 20:50:54 +09:30
zilmar 303af24bde RSP: Better handle delay slot at 0xFFC 2024-06-13 14:54:44 +09:30
zilmar c3d6ed1a0c RSP: Have the code be able to loop 2024-06-13 14:23:59 +09:30
zilmar 7161a6f591 RSP: Handle break in delay slot 2024-06-13 12:55:23 +09:30
zilmar d3411809f7 RSP: Get Recompiler to use LWU 2024-06-13 12:34:28 +09:30
zilmar 73c9174ce9 Core: Remove Memory exception filer 2024-06-13 11:50:06 +09:30
Summate 65a9097980
Allowing a paste into a number field to be trimmed automatically (#2414)
The specific issue I experienced is that Excel/LibreOffice Calc add a newline when you copy the contents of a single cell. This is bad behavior and they should provide a copy option that does not do that, but alas, it's much harder to get that into those applications. This behavior made it impossible to paste an otherwise-valid hex address into the Project64 fields without first putting it into Notepad, deleting the newline, recopying, and then doing the paste from there. If the field was simply text, you can go into the field edit and shift + home to select all and then do a copy, but that does not work for a formula. When you edit the file, it shows the formula instead. Therefore, you have absolutely no way of working around this except pasting it somewhere else and removing the newline manually.

In principle, there's no reason why you wouldn't trim the ends at least. Whitespace on either end is useless to you. However, content being after the newline should be rejected as it was before.

There were two secondary issues in the pasting code that are fixed here: One is that it only sort of collapsed single spaces. So if you had more than one space, spaces still would have ended up in the result. Actually I think the semantics were slightly more insidious, <space><number> would have turned into <number><same number> effectively. The only thing it did was remove the space by duplicating the number. If you had two spaces, then it would have ended up with e.g. <space><number><same number>. The only case where this wouldn't have happened is a space at the end which would have been preserved in the paste.

Secondly, it mutated the clipboard data directly. This would have lead to confusing results where multiple pastes would have had clipboard data in the clipboard itself move from, for example, two spaces to a single space to no spaces at all. The better solution is to preprocess to figure out how big we ultimately want our space-less result to be and stamp out the copy ourselves skipping anything we don't want. Leave the clipboard alone.

If it's desired to preserve single spaces only in the middle, the code will need to be modified a bit.

Co-authored-by: Summate <summate.ssbm@gmail.com>
2024-06-06 14:22:26 +09:30
MegaMech 0761ad4a83
Fix implementation of quad3d for f3dex 0.95 on pj64 video plugin (#2427)
* Update ucode01.cpp

* Fix quad3d implementation for f3dex 0.95

* Fix compile
2024-06-06 14:20:46 +09:30
zilmar 91f9cdaaa7 Core: Change the Program counter to be 64bit 2024-06-06 14:09:12 +09:30
zilmar 77ac4744a5 Core: Make sure fpu stack is being cleared 2024-05-23 11:52:58 +09:30
zilmar 0ff0d5234c Core: In R4300iOp::CheckFPUInput64 check values directly instead of using fpclassify 2024-05-23 11:43:19 +09:30
zilmar ec714cd90d Core: in CX86RecompilerOps::CompileCheckFPUResult64 protect RegPointer before Map_TempReg(asmjit::x86::eax) 2024-05-23 11:41:15 +09:30
zilmar 3baaa829de Core: Remove g_TLBLoadAddress, g_TLBStoreAddress global variables 2024-05-16 16:34:17 +09:30
zilmar ae21e10a8d Core: Increase the minimal amount of free space in recompiler memory 2024-05-16 16:15:28 +09:30
zilmar a1f46356fb Core: remove usage of g_RecompPos 2024-05-16 16:08:23 +09:30
zilmar 7f18773b5b Core: Add CX86RegInfo::GetFPStatusReg 2024-05-16 15:51:04 +09:30
zilmar 13bd420b2a Core: Sync FP status register in advanced block linking 2024-05-16 15:45:38 +09:30
zilmar 703a09d034 Core: Remove protecting memory option 2024-05-09 17:56:28 +09:30
zilmar f478f16269 Core: Clear FP Status flag in recompiler on BC1FL and BC1TL 2024-05-09 10:55:38 +09:30
zilmar 4c23e7af2c Core: Remove ChangeFPURegFormat, Load_FPR_ToTop 2024-05-02 17:21:01 +09:30
zilmar c786bc3251 Core: Force Fpu exception in recompiler 2024-05-02 16:34:13 +09:30
zilmar b3e8b760e6 Core: get COP1_S_TRUNC_L, COP1_S_CEIL_L, COP1_S_FLOOR_L, COP1_W_CVT_S, COP1_W_CVT_D, COP1_L_CVT_S, COP1_L_CVT_D to use COP1_S_CVT function 2024-05-02 15:48:43 +09:30
zilmar dd0f7ad776 Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword 2024-05-02 15:46:03 +09:30
zilmar 046f27ce98 Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT 2024-04-25 20:47:02 +09:30
zilmar 627b4d6103 Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv 2024-04-25 20:41:03 +09:30
zilmar b92e6bd752 Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT 2024-04-25 20:22:47 +09:30
zilmar d658477cf4 Core: get CX86RecompilerOps::Compile_Branch to clear status flags 2024-04-18 17:31:19 +09:30
zilmar b313640831 Core: In CX86RegInfo::Map_TempReg allow it to use FPStatusReg if it is unprotected 2024-04-18 17:28:23 +09:30
zilmar 1172b6e04d Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly 2024-04-18 17:21:39 +09:30
zilmar 38738b783d Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword 2024-04-18 17:11:45 +09:30
zilmar 7dc53e51cf Core: Get CompileCheckFPUInput to better handle 64bit value check 2024-04-18 17:00:29 +09:30
zilmar a9875b7d61 Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation 2024-04-18 16:58:18 +09:30
zilmar 3203322d8b Core: Get COP1_D_CVT_L to use COP1_S_CVT 2024-04-18 16:56:30 +09:30
zilmar 9e73771815 Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L 2024-04-18 16:51:53 +09:30
zilmar fe87142657 Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation 2024-04-18 16:42:48 +09:30
zilmar 4071b52810 Core: CX86RegInfo::UnMap_X86reg should fail on a protected register 2024-04-18 16:41:03 +09:30
zilmar 79f7aa9927 Core: CX86RegInfo::UnMap_FPStatusReg should unprotect register before trying to free it 2024-04-18 16:34:49 +09:30
zilmar 0cf4c7dc11 Core: get COP1_D_CMP to work in recompiler 2024-04-11 18:14:44 +09:30
zilmar 9272ac05f6 Core: refactor S opcodes to one central function 2024-04-11 18:09:30 +09:30
zilmar e7178dbdec Core: Fix CX86RecompilerOps::COP1_D_CVT_S 2024-03-28 20:05:27 +10:30
zilmar 8bb2445263 Core: Have CX86RecompilerOps::CompileCheckFPUResult32 write to the high word 2024-03-28 20:02:24 +10:30
François Berder 560c49ba2d
Core: Fix N64 disk IPL load address check (#2401)
The IPL load address check always evaluated to false due
to a wrong operator.

Signed-off-by: Francois Berder <fberder@outlook.fr>
2024-03-21 17:52:09 +10:30
zilmar 45fb2ad965 Core: In X86RecompilerOps::CompileCheckFPUResult64 make sure RegPointer is protected 2024-03-21 17:44:53 +10:30
zilmar 2811b63ff0 Core: Update CX86RecompilerOps::COP1_D_CVT_S and CX86RecompilerOps::COP1_D_CVT_W 2024-03-21 17:41:29 +10:30
zilmar 33d2722841 Core: fix up CX86RecompilerOps::COP1_D_FLOOR_W 2024-03-21 17:40:14 +10:30
zilmar 9a9c2e5439 Core: Update CX86RecompilerOps::COP1_D_CEIL_W 2024-03-21 17:32:12 +10:30
zilmar 401efae0d9 Core: fix up CX86RecompilerOps::COP1_D_ROUND_W 2024-03-21 17:28:16 +10:30
zilmar 772a20f07d Core: Update CX86RecompilerOps::COP1_D_SQRT 2024-03-21 17:15:10 +10:30
zilmar 87c732b65d Core: update CX86RecompilerOps::COP1_D_NEG 2024-03-21 17:14:00 +10:30
zilmar ece5e30a80 Core: create a function to handle .d recompiler opcodes that use fd and fs 2024-03-21 17:13:16 +10:30
zilmar 5133d47502 Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode 2024-03-14 18:12:58 +10:30
zilmar 98b1bddc64 Core: Get COP1_D_ADD, COP1_D_SUB, COP1_D_DIV, COP1_D_ABS, COP1_D_SQRT 2024-03-07 21:12:57 +10:30
zilmar 97ec1f533b Core: Make sure precision is set to 53bit 2024-03-07 20:52:24 +10:30
zilmar 190c408019 Core: Fix clang formatting in x86/x86RecompilerOps.cpp 2024-02-29 16:06:56 +10:30
zilmar f7aa6ef6cb Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions 2024-02-29 15:16:29 +10:30
zilmar 25dc3ed36f Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes 2024-02-29 15:13:14 +10:30
zilmar d2649f7a13 Core: Some clean up recompiler ops 2024-02-22 19:56:23 +10:30
zilmar fae0b81e21 Core: Have CX86RegInfo::Map_TempReg generate a BreakPoint if it mapping a protected register 2024-02-22 19:41:10 +10:30
zilmar e082cd55df Core: Get COP1_D_TRUNC_W to work in recompiler 2024-02-15 21:08:49 +10:30
zilmar 2559d23592 Core: Make sure CX86RecompilerOps::CompileInitFpuOperation clears flag for FE_INVALID 2024-02-15 21:02:27 +10:30
zilmar 46f6fae40f Core: get CompileCheckFPUInput to be able to handle 32bit and 64bit 2024-02-15 21:00:12 +10:30
zilmar 2014237ed6 Core: Update Round.w.s, trunc.w.s, ceil.w.s, floor.w.s to work with exceptions in the recompiler 2024-02-08 19:34:14 +10:30
zilmar ad1a2a2d9a Core: Update neg.s for the recompiler 2024-02-01 18:17:03 +10:30
zilmar b6671adf5d Core: Update abs.s for recompiler 2024-02-01 18:15:33 +10:30
zilmar bc3fe0fe16 Core: Handle FP Status Reg being mapped better 2024-01-25 18:46:39 +10:30
zilmar 7707f9c7b2 Core: Fix up mov.s and mov.d for correct behaviour in the recompiler 2024-01-25 16:25:06 +10:30
zilmar 272144dc37 Core: check timer on cop1 unusable 2024-01-25 16:23:03 +10:30
zilmar f0f44c67f4 Core: Make mov.s the same as mov.d 2024-01-25 15:32:56 +10:30
zilmar 7ed94b653e Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions 2024-01-18 17:09:27 +10:30
zilmar 2231e8d6c0 Core: Remove usage of fpclassify from R4300iOp::CheckFPUResult64 2024-01-18 16:53:14 +10:30
zilmar 71067ccdc4 Rsp: Change how SP_SEMAPHORE_REG to how it use to be before adding multithread RSP 2024-01-11 18:17:05 +10:30
zilmar 5c56f9df83 RSP: Update the size of the skip in the length for DMA 2024-01-11 17:50:23 +10:30
zilmar 4dc3e35bb4 Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions 2024-01-04 16:51:11 +10:30
zilmar f8089f565e Core: Unmap FPU_Float with writing to m_FPR_UDW 2024-01-04 14:40:42 +10:30
zilmar 552b8f744a Core: update Format_Name to match FPU_STATE 2024-01-04 13:11:21 +10:30
zilmar 6ca8333d39 Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions 2024-01-04 12:39:51 +10:30
zilmar c9d2bbd221 Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped 2024-01-04 12:37:06 +10:30
zilmar 0998f0ff0e Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer 2024-01-04 12:32:55 +10:30
zilmar 23cff4d7c5 Core: Add x86 asm opcode Jnp 2024-01-04 12:31:26 +10:30
zilmar 91a8a828d7 Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW 2024-01-04 12:01:21 +10:30
zilmar 320769d991 Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr 2024-01-04 10:33:07 +10:30
zilmar dafa1fb24d Core: Have COP1_W_CVT_S handle the initialization of exceptions 2023-12-28 11:19:06 +10:30
zilmar 17288c90c0 Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32 2023-12-28 10:23:18 +10:30
zilmar e2306e3541 Core: Get COP1_S_CVT_W to handle inexact 2023-12-28 09:21:53 +10:30
zilmar 8399fdb893 Core: Clear the Divide-by-zero flag 2023-12-21 21:24:33 +10:30
zilmar d14a639a62 Core: Implement COP1_S_DIV with fpu exceptions 2023-12-21 14:11:29 +10:30
zilmar 8e54ec8c8e Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis 2023-12-21 14:10:21 +10:30
zilmar b263ee10b0 Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0 2023-12-21 10:41:16 +10:30
zilmar 1810bfda5c Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops 2023-12-21 10:38:49 +10:30
zilmar 2c1610cfe2 Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode 2023-12-21 10:37:27 +10:30
zilmar 6610ae3058 Core: Have R4300iInstruction in CRecompilerOpsBase 2023-12-21 10:34:03 +10:30
zilmar 8e3fb3e302 Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference 2023-12-21 10:26:10 +10:30
zilmar c8e73ba18e Core: Handle unaligned SW exception in the recompiler 2023-12-14 23:04:26 +10:30
zilmar 972943cff7 Core: Allow LW to R0 be able to generate an exception 2023-12-14 17:21:52 +10:30
zilmar 89a6eaf9d1 Core: Add RecordLLAddress for 32bit register pointer 2023-12-14 13:52:15 +10:30
zilmar 67f5e4f854 Core: in LL for recompiler handle storing the address in COP[17] 2023-12-14 13:10:20 +10:30
zilmar d5a5f4cdac Core: Have Store Instruc rdb and user rdb matching 2023-12-14 12:21:03 +10:30
zilmar 5fec3f8d31 Core: remove the global of g_TLB 2023-12-14 12:09:24 +10:30