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x86/iR5900: Align LQC2/SQC2 to 16 bytes 

LQ/SQ were already 16 byte aligned.
This commit is contained in:
Connor McLaughlin 2022-11-13 17:57:23 +10:00 committed by refractionpcsx2
parent ffe669137b
commit a12accf3fa
1 changed files with 4 additions and 2 deletions
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6
pcsx2/x86/ix86-32/iR5900LoadStore.cpp
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@ -939,7 +939,7 @@ void recLQC2()
if (GPR_IS_CONST1(_Rs_))
{
int addr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
const u32 addr = (g_cpuConstRegs[_Rs_].UL[0] + _Imm_) & ~0xFu;
gpr = vtlb_DynGenReadQuad_Const(128, addr, -1);
}
@ -948,6 +948,7 @@ void recLQC2()
_eeMoveGPRtoR(arg1regd, _Rs_);
if (_Imm_ != 0)
xADD(arg1regd, _Imm_);
xAND(arg1regd, ~0xF);
iFlushCall(FLUSH_FULLVTLB);
@ -991,7 +992,7 @@ void recSQC2()
if (GPR_IS_CONST1(_Rs_))
{
int addr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
const u32 addr = (g_cpuConstRegs[_Rs_].UL[0] + _Imm_) & ~0xFu;
vtlb_DynGenWrite_Const(128, addr);
}
else
@ -999,6 +1000,7 @@ void recSQC2()
_eeMoveGPRtoR(arg1regd, _Rs_);
if (_Imm_ != 0)
xADD(arg1regd, _Imm_);
xAND(arg1regd, ~0xF);
iFlushCall(FLUSH_FULLVTLB);