1125ccedc3
z80: fix a bug
2018-06-04 07:52:48 -04:00
32ae549c70
z80: Add bus request timing array to work with zx spectrum
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Also some clean up
2018-06-03 19:14:30 -04:00
7220e9d394
z80: fix some instruction timings for IN/OUT
2018-06-01 15:21:05 -04:00
c0d6c02b2e
Z80: Recast core to cycle accurate memory accesses and wait state timing
2018-05-31 21:05:41 -04:00
d6a9d69f7e
GBHawk: Fix Pinball Fantasies
2018-05-25 15:00:16 -04:00
f3ea6fe025
Use generic interface type on MOS 6052X for talking to the emulator core ( #1189 )
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* Use generic interface type on MOS 6052X for talking to the emulator core
* Change CpuLink constructors to not use expression-bodies, to get the AppVeyor build to pass.
* Add comment explaining why IMOS6502XLink exists.
2018-05-20 23:18:53 +03:00
2144195bb8
GBHawk: Clean up some unused variables
2018-05-16 15:50:07 -04:00
1b991de966
GBHawk: More Hlat bug work
2018-05-15 14:26:48 -04:00
a185f33487
Z80A: Add a WAIT state that can puase the CPU on reads / writes
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NOTE: a wait state is added automatically to IN/OUT reads / writes, but I don't know if this is already accounted for in the cycle timings, TODO.
2018-05-15 09:44:39 -04:00
e8145af463
i hope this breaks something
2018-05-12 12:55:42 -04:00
678666ddf0
GBHawk: Fix a bug in I Flag check
2018-05-10 15:31:06 -04:00
32f78cd311
GBHawk: Cleanup ppus
2018-05-09 20:05:53 -04:00
828dbba1a5
GBHawk: Rework CPU to poll INT at the correct time.
2018-05-08 21:47:35 -04:00
b3647c6e05
GBCHawk: adjust PPU
2018-05-04 15:45:18 -04:00
e29b741bd4
GBCHawk: Halt test rom work, ppu still needs re-work
2018-05-03 21:26:33 -04:00
d4eb3da512
GBHawk: Restructure to pass all other tests (as before)
2018-05-03 19:07:51 -04:00
19c509e9c2
GBHawk: Attempt at some halt bugs
2018-05-01 21:53:20 -04:00
9c06ac02a2
Z80: Fix Flags for IN operations
2018-04-18 19:00:59 -04:00
6019073157
GBHawk: Fix some GBC Behaviours, start MBC7
2018-04-03 18:18:41 -04:00
d4ee8f480b
GBHawk: HDMA and GBC halt commits
2018-03-25 21:22:27 -04:00
380b9f085e
GBHawk : GBC Commits round 2
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-HDMA
-GBA setting
2018-03-25 17:58:21 -04:00
ca69e52229
GBHawk: GBC commits round 1
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-RAM banks
-Unify VRAM and add second Bank
-Speed Switch and associated reorg.
-Memory Map and Registers
-PPU seperation
2018-03-25 10:07:12 -04:00
e2eac983a1
Merge pull request #1149 from TASVideos/master
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Bringing ZXSpectrum branch up to date with master
2018-03-19 15:52:55 +00:00
81e80acf86
z80: make TotalExecutedCycles long and change related variables accordingly
2018-03-18 09:55:56 -04:00
dbb90a996d
z80: clean up
2018-03-16 17:50:51 -04:00
396f875ac2
z80 disassembler: handle address wrap
2018-03-15 20:58:08 -04:00
8ebcadbc58
z80: fix port addressing in some cases
2018-03-15 20:47:47 -04:00
09d765e853
make 6502 tracelog less bullshit
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- stop spamming ---
- stop acting like 6502 is able to execute the same pc twice in a row
- put as many raw bytes as 6502 fetches per instruction
- reorder some registers
- stop being called when there's nothing to disasm
2018-03-15 00:30:50 +03:00
47cfe9ceb6
Intellivision: TCI throw console warning instead of error, fixes popeye
2018-03-02 16:59:38 -05:00
7c82d6d526
Merge pull request #1106 from TASVideos/master
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Bring ZXSpectrum branch up to date with master
2018-02-06 08:45:48 +00:00
7ae43505ec
GBHawk: Clean up interrupt handling
2017-12-06 18:55:38 -05:00
b65c10afc7
GBHawk: CPU Update for new test
2017-12-06 08:12:41 -05:00
a9f8828063
z80: fix port access behaviour
2017-12-01 08:20:18 -05:00
d09e73b592
z80: implement data bus
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-needed for ZXspectrum mode 2 interrupts
-use with FetchDB function
2017-11-29 16:28:08 -05:00
cbd217d479
GBHawk: MBC3
2017-11-24 15:44:29 -05:00
d0bdfd3d68
Fixes disassembler for SMS
2017-11-24 02:56:21 -05:00
afe5a7cd11
GBHawk: Fix Amazing Penguin
2017-11-22 13:35:07 -05:00
69170fb110
Remove old GB CPU core
2017-11-19 10:22:05 -05:00
26b1a2dff0
GBHawk: Pass all sound tests
2017-11-19 09:30:18 -05:00
087586bc49
GBHawk: pass new IRQ test
2017-11-18 19:45:11 -05:00
b2d453441e
Merge pull request #1051 from TASVideos/master
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Sync Master to GBHawk
2017-11-09 08:50:48 -05:00
7cdffc25c3
Update Z80A.cs
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Properly reset instruction vector index
2017-11-03 08:39:02 -04:00
ebcd237858
Merge branch 'master' into domainedmemoryhooks
2017-10-29 12:38:29 -05:00
f94d3f58c6
Z80: Fix CDL
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Use FetchMemory for opcodes and ReadMemory for everything else
Also fix Dis-assembling
2017-10-25 19:21:30 -04:00
28cce355bf
Z80: Fix R register operation
2017-10-19 12:08:34 -04:00
be6aa52bc8
Z80: Remove JAM
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The relevent opcodes behave as NOPs
2017-10-19 10:55:17 -04:00
4f63cadb4a
Z80
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Corrections and Bug Fixes
2017-10-14 14:07:17 -04:00
0fda518cb7
Add files via upload
2017-10-13 17:58:36 -04:00
7984eecd99
Delete Z80A.cs
2017-10-13 17:52:53 -04:00
ac2c6a46e0
Delete Tables.cs
2017-10-13 17:52:45 -04:00
9776e65719
Delete Registers.cs
2017-10-13 17:52:36 -04:00
33079bed48
Delete Interrupts.cs
2017-10-13 17:52:27 -04:00
12e709e045
Delete Execute.cs
2017-10-13 17:52:17 -04:00
438b3893e3
Delete Disassembler.cs
2017-10-13 17:52:03 -04:00
3be21c583e
Add files via upload
2017-10-13 16:27:41 -04:00
258688ebdd
Add files via upload
2017-10-13 11:07:02 -04:00
12c46db790
Add files via upload
2017-10-12 20:20:13 -04:00
ff13009e97
Create ReadMe.txt
2017-10-12 20:19:42 -04:00
56d06b3357
LR35902 CPU commit
2017-08-29 09:13:56 -04:00
8ff899b731
Create ReadMe.txt
2017-08-29 09:12:31 -04:00
2ff7ae06ea
Z80: Fix interrupts again
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fixes #951
also made sure previous tricky IRQ games still work
2017-08-04 15:03:22 -04:00
cd289c474e
memorycallbacks with domains - Phase 2 - change api to Call methods and refactor accordingly, everything should behave as it was before the refactor at this point. No cores have yet to be implemented with domains other than the default bus they already had
2017-08-03 18:08:07 -05:00
803871daab
z80: Fix bit test flags
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-passes zexall bit test
-still some spurious cases to implement, but how to test them?
2017-07-30 17:35:48 -04:00
c2476f1d36
Z80: Actually upload the correct file >__>
2017-06-28 16:34:01 -04:00
0e0d3e4143
Update Execute.cs
2017-06-17 19:01:04 -04:00
8ad021c6fd
Intellivision - implement memory callbacks
2017-04-23 13:28:40 -05:00
7fbed8d3e5
Intellivision - convert DIsassembler to peeks instead of reads
2017-04-23 13:14:05 -05:00
d03577ade6
Intellivision - partially implement IDebuggable - flag/register getting and setting, and TotalExecutedCycles
2017-04-23 12:30:41 -05:00
3d6b1da94d
Whitespace only (indentation fixes/cleanup).
2017-04-19 20:34:30 -04:00
b53502eed8
Spaces -> tabs.
2017-04-15 16:37:30 -04:00
3ac053c33d
Update 6502 reset
2017-03-08 12:19:31 -05:00
2526f8c7b9
Update CP1610
2017-03-05 18:44:34 -05:00
a36b7093e3
Intellivision implement System Bus memory domain
2017-02-09 12:53:55 -05:00
eb1f477f9d
Intellivision - turn off logging
2017-02-08 17:26:30 -06:00
aa44cf6f02
Update CP1610.Execute.cs
2016-12-26 10:07:19 -05:00
46586a7df9
Update CP1610.Execute.cs
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FInally find the bug that Fixes Pac Man (and Ms Pac Man as well)
2016-12-24 22:28:58 -05:00
f5491bf86f
Update CP1610.Execute.cs
2016-12-24 15:01:00 -05:00
68c3d2abb1
Intellivision Fix overflow flag bug
2016-12-24 13:03:12 -05:00
f542a438ed
Update CP1610.Execute.cs
2016-12-24 10:53:30 -05:00
6f4c5bc135
Update CP1610.Execute.cs
2016-12-21 21:42:14 -05:00
eda79c2212
Make an interface for CodeDataLog, and move CodeDataLog to Base Implementations
2016-12-16 11:33:02 -06:00
206ea9887b
Text savestate fixes.
2016-12-14 18:35:03 -05:00
33843265f8
Update CP1610 to include Halts from SR2
2016-12-13 16:47:21 -05:00
ba149320c5
INtellivision fill out save states
2016-12-07 10:55:25 -05:00
e9d1af2b0c
Intellivision - stubs for savestate logic
2016-12-04 08:25:28 -06:00
af03ac3eb7
CP1610 Add registers to tracer
2016-11-14 21:17:24 -05:00
fbd630b594
Update CP1610.Execute.cs
2016-11-14 20:44:36 -05:00
c230609656
Cp1610 trace logger
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WIP
2016-11-12 12:58:10 -05:00
e44493d9fb
Intellivision - wire up trace logger to the core. Currently does nothing since the TraceCallback in CP1610 needs to be wired up in the object in the right places
2016-11-11 16:17:35 -06:00
9cb9941fb2
CP1610 updates for intellivision
2016-11-11 16:48:50 -05:00
c07e8b0a79
Z80 - instruction timing fixes
2016-11-09 14:06:56 +13:00
3fa2828d5b
Accuracy improvement to z80
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properly set interrupt enable after the NEXT instruction
2016-11-03 20:50:47 -04:00
9d594e013b
genesis disasm: snip implied regs for movem
2016-08-16 22:07:32 +03:00
76eaea3619
tracer unification for cores: spacing, headers, etc
2016-08-16 01:39:26 +03:00
888d7fed6a
tracer: set some padding
2016-08-14 22:59:07 +03:00
1c9d814e15
Add files via upload
2016-06-24 15:02:50 -04:00
d518db2d14
6502: RTS IncPc micro-op should perform a read at PC and discard the result.
2016-06-22 15:09:57 -05:00
55feae8bf6
clean up and minor fixes
2016-06-16 11:29:08 -04:00
b7c8755b14
Fill in some undocumented opcodes
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now passes instr_misc/instr_misc (the only test I could find that even concerned itself with these opcodes)
2016-06-15 22:33:15 -04:00
111648cf98
Break a bunch of memory domain stuff with pointless refactoring
2016-04-13 19:50:06 -04:00
alyosha-tas