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genesis disasm: snip implied regs for movem

This commit is contained in:
feos 2016-08-16 22:07:32 +03:00
parent 76eaea3619
commit 9d594e013b
2 changed files with 73 additions and 17 deletions
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88
BizHawk.Emulation.Cores/CPUs/68000/Instructions/DataMovement.cs
View File

@ -387,57 +387,113 @@ namespace BizHawk.Emulation.Cores.Components.M68000
}
}
static string DisassembleRegisterList0(ushort registers)
static string DisassembleRegisterList0(uint registers)
{
var str = new StringBuilder();
int count = 0;
bool snip = false;
for (int i = 0; i < 8; i++)
{
if ((registers & 0x8000) != 0)
if ((registers & 0x8000) != 0) // current bit
{
if (count > 0) str.Append(",");
str.Append("D" + i);
if ((registers & 0x10000) != 0 && // last bit
(registers & 0x4000) != 0) // next bit
{
if (!snip)
{
str.Append("-");
snip = true;
}
}
else
{
if (count > 0 && !snip) str.Append(",");
str.Append("D" + i);
snip = false;
}
count++;
}
registers <<= 1;
}
for (int i = 0; i < 8; i++)
{
if ((registers & 0x8000) != 0)
if ((registers & 0x8000) != 0) // current bit
{
if (count > 0) str.Append(",");
str.Append("A" + i);
if ((registers & 0x10000) != 0 && // last bit
(registers & 0x4000) != 0) // next bit
{
if (!snip)
{
str.Append("-");
snip = true;
}
}
else
{
if (count > 0 && !snip) str.Append(",");
str.Append("A" + i);
snip = false;
}
count++;
}
registers <<= 1;
}
//str.Append(string.Format("[{0:X4}]", registers >> 16));
return str.ToString();
}
static string DisassembleRegisterList1(ushort registers)
static string DisassembleRegisterList1(uint registers)
{
var str = new StringBuilder();
int count = 0;
bool snip = false;
for (int i = 0; i < 8; i++)
{
if ((registers & 1) != 0)
if ((registers & 0x10000) != 0)
{
if (count > 0) str.Append(",");
str.Append("D" + i);
if ((registers & 0x8000) != 0 && // last bit
(registers & 0x20000) != 0) // next bit
{
if (!snip)
{
str.Append("-");
snip = true;
}
}
else
{
if (count > 0 && !snip) str.Append(",");
str.Append("D" + i);
snip = false;
}
count++;
}
registers >>= 1;
}
for (int i = 0; i < 8; i++)
{
if ((registers & 1) != 0)
if ((registers & 0x10000) != 0)
{
if (count > 0) str.Append(",");
str.Append("A" + i);
if ((registers & 0x8000) != 0 && // last bit
(registers & 0x20000) != 0) // next bit
{
if (!snip)
{
str.Append("-");
snip = true;
}
}
else
{
if (count > 0 && !snip) str.Append(",");
str.Append("A" + i);
snip = false;
}
count++;
}
registers >>= 1;
}
//str.Append(string.Format("[{0:X4}]", registers & 0xFFFF));
return str.ToString();
}
@ -452,7 +508,7 @@ namespace BizHawk.Emulation.Cores.Components.M68000
string address = DisassembleAddress(mode, reg, ref pc);
info.Mnemonic = size == 0 ? "movem.w" : "movem.l";
info.Args = DisassembleRegisterList0(registers) + ", " + address;
info.Args = DisassembleRegisterList0((uint)registers) + ", " + address;
info.Length = pc - info.PC;
}
@ -467,7 +523,7 @@ namespace BizHawk.Emulation.Cores.Components.M68000
string address = DisassembleAddress(mode, reg, ref pc);
info.Mnemonic = size == 0 ? "movem.w" : "movem.l";
info.Args = address + ", " + DisassembleRegisterList1(registers);
info.Args = address + ", " + DisassembleRegisterList1((uint)registers << 16);
info.Length = pc - info.PC;
}

2
BizHawk.Emulation.Cores/CPUs/68000/Memory.cs
View File

@ -380,7 +380,7 @@ namespace BizHawk.Emulation.Cores.Components.M68000
case 2: return "(A" + reg + ")"; // (An)
case 3: return "(A" + reg + ")+"; // (An)+
case 4: return "-(A" + reg + ")"; // -(An)
case 5: addr = ReadWord(pc); pc += 2; return String.Format("({0},A{1})", addr, reg); // (d16,An)
case 5: addr = ReadWord(pc); pc += 2; return String.Format("(${0:X},A{1})", addr, reg); // (d16,An)
case 6: addr = ReadWord(pc); pc += 2; return DisassembleIndex("A" + reg, (short)addr); // (d8,An,Xn)
case 7:
switch (reg)