Create ReadMe.txt

2017-10-12 20:19:42 -04:00 · 2017-10-12 20:19:42 -04:00 · ff13009e97
parent 59fdb4a4c3
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+TODO: 
+
+Mode 0 and 2 interrupts
+Check T-cycle level memory access timing
+Check R register 
+new tests for WZ Registers
+Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this?
+Data Bus - For mode zero and 2 interrupts, need a system that uses it to test