Commit Graph

4630 Commits

Author SHA1 Message Date
zilmar 542afc4514 Core: remove some accidental added debug code 2023-11-16 18:16:35 +10:30
zilmar ee714e2462 Core: On unmap base addresses reset to the correct address 2023-11-16 18:14:15 +10:30
zilmar 8f4f434820 Core: Get Fast tlb to just be 32bit 2023-11-16 17:11:05 +10:30
zilmar dcb6969067 Core: Have entryHI use functions to set/get parts 2023-11-16 09:19:24 +10:30
zilmar a0130ff896 Core: Convert %I64U to %llx 2023-11-16 09:03:32 +10:30
zilmar e46ffde6b3 fix clang formatting 2023-11-09 12:59:40 +10:30
zilmar 296b7cf1cf Android: Force RSP to be interpret 2023-11-09 12:45:36 +10:30
zilmar 0c8b10bbc7 Android: Get RSP core to compile on android 2023-11-09 11:53:06 +10:30
zilmar 09cc3442a2 Android: fix compile bug 2023-11-02 20:27:38 +10:30
zilmar 6fbc5c0264 Android: Move hle audio code in to main rsp plugin 2023-11-02 20:06:58 +10:30
zilmar e6edbc6c82 Fix clang formatting 2023-10-27 10:14:21 +10:30
zilmar 4770d29ec0 Core: Get system events to be internal not global 2023-10-26 19:59:11 +10:30
zilmar d3f4132770 Android: When listing a rom not in rdb, use game file instead 2023-10-26 11:18:24 +10:30
zilmar b74e21d056 Android: Show base dir to splash logs when starting 2023-10-26 11:17:49 +10:30
zilmar bf480623bd [Android] Add Android/Bridge to clang checking 2023-10-26 11:05:20 +10:30
zilmar 8f062975c3 Core: improve DisplayControlRegHandler::Write32 2023-10-19 19:28:38 +10:30
zilmar d6a2ae80c1 Core: Remove SystemRegisters 2023-10-19 14:56:53 +10:30
zilmar d58168bcb9 Core: R4300iOp access the registers directly, not through CSystemRegisters 2023-10-19 12:52:33 +10:30
zilmar 4d78f56aa2 Core: In R4300iOp have a member variable for system, reg, mmu 2023-10-19 12:31:26 +10:30
zilmar ae0097550f Core: Make R4300iOp opcodes not static 2023-10-19 11:43:32 +10:30
zilmar 7f42f70283 Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static 2023-10-19 10:28:25 +10:30
zilmar d3edbf6dda Core: move CInterpreterCPU into R4300iOp 2023-10-19 09:32:42 +10:30
zilmar d4dbc5a3f4 Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio 2023-10-14 11:53:35 +10:30
zilmar 00c5057b17 Core: Make sure precision is correct for COP1_D_SQRT 2023-10-13 00:16:14 +10:30
zilmar 3a68d3d92a Core: LL/LLD store address 2023-10-12 19:55:29 +10:30
zilmar a6405cfa2d Core: Add masking around DPC_START_REG/DPC_END_REG 2023-10-12 17:50:58 +10:30
zilmar 4e71221147 Core: Fix up FPU mode register location 2023-10-12 14:53:44 +10:30
zilmar befa57924d Core: Fix clang compile issues 2023-10-05 15:01:09 +10:30
zilmar f73c3708a5 Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty 2023-10-05 14:45:17 +10:30
zilmar e74e8f6a23 Core: Have load/store ops be able to use 64bit addresses 2023-10-05 14:28:32 +10:30
zilmar 9f07fe2aac Core: Get tlb addresses to be 64bit 2023-10-05 13:42:31 +10:30
zilmar 4b844495b7 Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
2023-10-05 13:10:45 +10:30
zilmar 35105e814e Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss 2023-10-05 09:54:41 +10:30
zilmar b7311cc611 Core: Change Non memory load/store to not use tlb 2023-10-05 09:32:45 +10:30
zilmar a975af0e3c Rsp: only use alignas for Visual Studio 2023-09-28 16:18:39 +09:30
zilmar dd7ec63dd9 Rsp: Change usage of alignas to try and fix android build 2023-09-28 15:53:46 +09:30
zilmar 7e249d22b1 Try to fix android build 2023-09-28 15:25:34 +09:30
zilmar 46e6e54f24 RSP: improve running RSP multithreaded 2023-09-28 14:46:36 +09:30
zilmar 15e6e460d2 Rsp: Clean up VRCP, VRCPL, VRCPH, VRSQ, VRSQL, VRSQH 2023-09-28 13:39:23 +09:30
zilmar 3c52d8e2e3 RSP: use vt instead of rt when using RSP_Vect 2023-09-28 11:57:29 +09:30
zilmar 0bd6a96118 RSP: fix display of VRCP instruction 2023-09-28 11:54:50 +09:30
zilmar b1240072c6 RSP: move Enter_RSP_Register_Window & UpdateRSPRegistersScreen function definition out of RSP core 2023-09-28 11:53:57 +09:30
zilmar ac3e0f83d1 Rsp: Use RSP Register Handler 2023-09-28 11:52:06 +09:30
zilmar bd1ec4ff0f Core: Create a setting for RDRAM Size that plugins can read 2023-09-28 07:29:11 +09:30
zilmar 99417fc5d9 Core: reset run event in CRSP_Plugin after rom close 2023-09-28 07:19:20 +09:30
zilmar f817becf9c Core: Create a handler for RSP registers that is accessible to the core and the RSP 2023-09-28 07:03:01 +09:30
zilmar 03e13455f9 Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot 2023-09-28 06:39:39 +09:30
zilmar 2caa457d02 Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
2023-09-22 11:01:46 +09:30
zilmar 10d2b77d7c Core: Try to fix android build 2023-09-21 20:13:41 +09:30
zilmar aadcca7528 Core: Fix clang issue 2023-09-21 18:40:27 +09:30
zilmar 6307888be4 Core: fix up exception generator functions 2023-09-21 18:07:56 +09:30
zilmar 32ff820a03 RSP: clean up vector compare ops (VLT, VEQ, VNE, VGE, VCH) 2023-09-21 15:51:16 +09:30
zilmar dc95d2f7a4 RSP: Clean up vector ops (VADD, VSUB, VABS, VSUBC, VMRG, VAND, VNAND, VOR, VNOR, VXOR, VNXOR) 2023-09-21 15:44:07 +09:30
zilmar 174e751a4a RSP: Fix up load ops (LUV, LHV, LFV, LTV) 2023-09-21 15:30:07 +09:30
zilmar bdaf8cf78c RSP: Clean up store vector ops (SHV, SFV, STV, SWV) 2023-09-21 15:25:45 +09:30
zilmar 5dcc7e200f Rsp: Move InitilizeRSPRegisters and InitilizeRSP into rsp-core 2023-09-21 15:16:26 +09:30
zilmar 42a944c660 RSP: Setup option to run in a thread 2023-09-21 14:25:07 +09:30
zilmar c4abebe201 Core: Update <Project64-plugin-spec\ to <Project64-plugin-spec/ 2023-09-21 14:13:08 +09:30
zilmar f3d6d3fc7c Core: for tlb miss only use special address when address is not defined 2023-09-14 18:39:15 +09:30
zilmar e0c125e837 Core: Fix clang issue 2023-09-14 16:33:20 +09:30
zilmar c02858c7a0 Core: Add LLD opcode 2023-09-14 16:31:37 +09:30
zilmar f559aed2ad Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function 2023-09-14 16:23:26 +09:30
zilmar ae4af8746b Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss 2023-09-14 13:09:11 +09:30
zilmar 8b14b6d7d1 Core: Move InitRegisters to register class 2023-09-14 12:01:16 +09:30
zilmar a5a4873e84 Core: Have CRegisters::DoAddressError to not directly modify program counter 2023-09-14 11:37:21 +09:30
zilmar 2d09178449 Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions 2023-09-14 11:15:42 +09:30
zilmar 5da5dab3c5 Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC 2023-09-14 11:09:28 +09:30
zilmar fcd7257adc Core: Change COP0 Status register to a struct breaking up the bits 2023-09-14 10:23:36 +09:30
zilmar 9ffd87168a Core: DisplayControlRegHandler::Read32 read more of the registers 2023-09-14 09:40:11 +09:30
zilmar 002f2e17c3 RSP: Clean up code for vector multiple ops 2023-09-07 11:54:36 +09:30
zilmar 4e9a692449 RSP: Add RSP_Vector_VRNDP 2023-09-07 11:41:17 +09:30
zilmar 0cadbe0f70 RSP: Add clamp16 2023-09-07 11:31:31 +09:30
zilmar af1c0c2b55 RSP: Add Vmulq 2023-09-07 11:30:15 +09:30
zilmar d468b863c2 Rsp: add vnop for vnull 2023-09-07 11:29:16 +09:30
zilmar 8b71ef3bc1 RSP: Add RSP_Vector_Reserved 2023-09-07 11:23:35 +09:30
zilmar ab67374c8a RSP: Update the display of RSP opcodes in debugger 2023-09-07 11:19:44 +09:30
zilmar 4f74dc4bb0 Rsp: Update display of vector in debugger 2023-09-07 11:17:08 +09:30
zilmar ab03916a70 Core: let the stack pointer equal end of rdram 2023-09-07 11:13:54 +09:30
zilmar 7199096748 Core: Merge CheckFPUException into CheckFPUResult64 2023-08-31 18:52:34 +09:30
zilmar 91d1c6e237 Core: Add fpu exceptions to COP1_S_MUL 2023-08-31 11:09:48 +09:30
zilmar 2f7a35613f Core: Add exception to COP1_S_SUB 2023-08-31 10:54:41 +09:30
zilmar c28c6bb4a1 Core: Add fpu exceptions to COP1_S_ADD 2023-08-31 10:08:49 +09:30
zilmar 416c85ecda Core: some code clean up of Load_FPR_ToTop 2023-08-31 09:30:05 +09:30
zilmar 2dcfcf250d Core: Do not force unmapping of fpr registers before CX86RegInfo::BeforeCallDirect(void) 2023-08-31 09:28:23 +09:30
zilmar e49438cdab Core: Add exit reason exception 2023-08-30 12:16:07 +09:30
zilmar 703ad4049a PluginRSP: declare windows.h before asset.h 2023-08-30 12:15:36 +09:30
zilmar 41fa1fd5dd Core: use m_TLB_WriteMap not m_TLB_ReadMap for NonMemory 2023-08-30 11:35:53 +09:30
zilmar 625f532d73 RSP: use __debugbreak not DebugBreak 2023-08-24 10:44:45 +09:30
zilmar 47f14016e6 RSP: Set RSP_JumpTo before register in JALR, BLTZAL, BGEZAL 2023-08-24 10:35:51 +09:30
zilmar ae9912b068 RSP: Clean up VCR 2023-08-24 10:31:26 +09:30
zilmar 7db5876927 RSP: Clean up VCL 2023-08-24 10:07:05 +09:30
zilmar 9dab3481ae RSP: Add class to wrap around RSP flag 2023-08-24 08:00:29 +09:30
zilmar 0cb43e0c33 RSP: Remove flag to swap vector register endian 2023-08-24 07:04:35 +09:30
zilmar d300dc002a Core: remove exception catch around RSP 2023-08-17 15:27:18 +09:30
zilmar 6884c8d2c9 Core: fix up how recompiler handles rounding 2023-08-17 15:24:57 +09:30
zilmar a80860605d RSP: fix up usage of Indx in recompiler 2023-08-17 14:38:51 +09:30
zilmar 3394be733f RSP: Fix up AccurateEmulation for interpreter 2023-08-17 14:22:54 +09:30
zilmar 54be4d8135 Rsp: Add a rsp AccurateEmulation flag for new rsp work 2023-08-17 12:04:06 +09:30
zilmar 09ef426ac6 Rsp: Fix memory allocation of recompiler memory 2023-08-17 11:37:03 +09:30
zilmar 6b30c1ae6a Rsp: Move Recompiler in to rsp-core 2023-08-17 08:59:22 +09:30
zilmar 1f0151e067 RSP: fix up clang formatting 2023-08-10 21:50:01 +09:30
zilmar 6bdc898248 RSP: fix LPV 2023-08-10 20:52:50 +09:30
zilmar c6c0a4a6d2 RSP: fix LDV 2023-08-10 16:06:38 +09:30
zilmar 1d492262fd RSP: use std::min for length calculation 2023-08-10 14:24:33 +09:30
zilmar 60192a7f33 RSP: Move more functionality in to rsp-core 2023-08-10 14:16:57 +09:30
zilmar 25e48405c5 RSP: Start to split out RSP in to core and UI for plugin 2023-08-10 10:27:11 +09:30
zilmar bb5a16aaa2 RSP: Change RSP Registers to be an enum not define 2023-08-10 09:47:53 +09:30
zilmar 34d75780bf Rsp: Update the element order in LSV, LLV, LRV 2023-08-03 17:32:40 +09:30
zilmar a18f78679e Rsp: Change the order of EleSpec 2023-08-03 17:29:55 +09:30
zilmar 05cd3a846b Rsp: Update vmov 2023-08-03 17:27:58 +09:30
zilmar b5db44c12d Core: Get CheckFPUInput64Conv to return true on exception 2023-08-03 17:25:03 +09:30
zilmar 5ff45c43c4 Core: Get R4300iOp::CheckFPUInput64 to return true on exception 2023-08-03 17:11:56 +09:30
zilmar bc1b027c94 Core: get CheckFPUInput32Conv to return true on exception 2023-08-03 16:24:54 +09:30
zilmar 930e463bbc Core: Move TriggerException(EXC_FPE) into R4300iOp::CheckFPUInput32 2023-08-03 15:38:07 +09:30
Squall Leonhart 822b75c734
changes this callback back to BOOL so it works again. (#2378) 2023-07-28 06:57:31 +09:30
zilmar bbe603c758 RSP: fix up lbv 2023-07-27 16:01:03 +09:30
zilmar 52e77bc4e0 RSP: Some clean up to lqv 2023-07-27 15:11:31 +09:30
zilmar e1854e1589 RSP: Inline memory functions in to the opcodes 2023-07-27 13:23:53 +09:30
Squall Leonhart 562d4d4e56
Make the FPU Register Caching checkbox functional (#2377)
Adds missing line from SettingsPage-Game-Recompiler.h
Corrects entry in SettingsPage-Game-Recompiler.cpp to Game_FPURegCache
Removes : from Language file entry.
2023-07-27 09:07:14 +09:30
zilmar 5c65bebe9e RSP: Update VAdd code (SQV/LQV order changed as well) 2023-07-21 07:25:17 +09:30
zilmar 2cf740565e RSP: Add dummy vsut 2023-07-20 09:40:42 +09:30
zilmar e88e827d64 RSP Add dummy LWV 2023-07-20 08:59:36 +09:30
zilmar cf7628cc1d RSP: Update RSP_LRV_DMEM 2023-07-18 10:05:25 +09:30
zilmar 4265bdfb43 RSP: Add lwu 2023-07-18 10:04:54 +09:30
zilmar bd357c65b0 RSP: fix vmov 2023-07-18 09:56:31 +09:30
zilmar 6e03d6ad7b RSP: Add method to get element specifier index from the Vector 2023-07-18 07:55:06 +09:30
zilmar 97fccb1c36 RSP: Change EleSpec to be 16 and use .e instead of rs 2023-07-18 07:36:25 +09:30
zilmar 97fbbffee8 RSP: A little clean up of VABS 2023-07-18 07:27:49 +09:30
zilmar ee452143ff RSP: Change the name of the opcode that register ops use 2023-07-18 07:22:27 +09:30
zilmar b7d7884e22 RSP: Make a class for the RSP Vector 2023-07-13 21:09:18 +09:30
zilmar 353ef5ed89 RSP: When command window is entered, always step commands 2023-07-06 20:56:00 +09:30
zilmar 115881524b RSP: Better handling on unaligned SH and SW 2023-07-06 20:55:02 +09:30
zilmar fbb388fa0f Rsp: Fix capitalization in rsp_UnknownOpcode 2023-07-06 20:51:17 +09:30
zilmar 07cf94bde3 RSP: only look at SP_STATUS_HALT when seeing if the RSP should run 2023-07-06 20:49:14 +09:30
zilmar 7dc30b1d6d RSP: Update dissam of load/store vector ops 2023-07-06 17:49:15 +09:30
zilmar f8f9688386 RSP: get RSP_LH_DMEM and RSP_LW_DMEM to handle end of memory roll over 2023-06-29 14:52:46 +09:30
zilmar cfc63532dd RSP: move p_func from RspTypes.h to Cpu.h 2023-06-29 12:31:25 +09:30
zilmar 02da0ccad1 RSP: Use bool instead of Boolean 2023-06-29 12:29:07 +09:30
zilmar 2ce9eaa667 RSP: Rename Types.h to RspTypes.h 2023-06-29 11:03:55 +09:30
zilmar 1c61f15ea9 RSP: Update display of vector ops 2023-06-29 10:59:54 +09:30
zilmar 080a3b69ac RSP: Create a RSP instruction for decoding the RSP op 2023-06-15 21:09:44 +09:30
zilmar df215c1cc5 RSP: Fix up rename of filters file 2023-06-15 14:48:07 +09:30
zilmar ef24ec11d8 Rename RSP to Project64-rsp 2023-06-15 14:45:27 +09:30
zilmar 187bd64915 Core: Update how exceptions are handled with the recompiler 2023-06-08 16:25:05 +09:30
Nayla 18a712ce6a
Update Interface.cpp (#2367) 2023-06-03 07:11:57 +09:30
zilmar f4459fe143 RSP: Update RSP name in package_zip.cmd 2023-06-02 10:52:10 +09:30
zilmar 98b96a60cb RSP: Get the code to conform to clang-format 2023-06-01 21:16:23 +09:30
zilmar 90fefed579 RSP: Fix text when adding tab to registers 2023-06-01 19:40:53 +09:30
zilmar 1522f17b9c RSP: Convert base code to be compiled as c++ instead of C 2023-06-01 17:11:26 +09:30
zilmar a39ebe7d37 Core: Create InitFpuOperation 2023-05-27 10:01:19 +09:30
zilmar e2eebe566d Core: fix up for clang 2023-05-18 18:05:54 +09:30
zilmar b438fddf2e Core: Add CP2 handling 2023-05-18 18:04:41 +09:30
zilmar 3b8dfce64a Core: Convert DoBreakException to TriggerException 2023-05-18 11:47:00 +09:30
zilmar b2c2a03a2e Core: convert DoFloatingPointException to TriggerException 2023-05-18 11:41:20 +09:30
zilmar 0dfab78c88 Core: Convert DoCopUnusableException to TriggerException 2023-05-18 11:26:36 +09:30
zilmar 456f25eb6b Core: Get DoIntrException to use TriggerException 2023-05-18 11:19:26 +09:30
zilmar 252f629e14 Core: Convert DoIllegalInstructionException to TriggerException 2023-05-18 11:13:22 +09:30
zilmar 59a1277bed Core: Convert GenerateOverflowException to TriggerException 2023-05-18 11:05:27 +09:30
zilmar 69fd74ba56 Core: Convert DoSysCallException to TriggerException 2023-05-18 10:56:06 +09:30
zilmar 17df17805d Core: convert DoTrapException to TriggerException 2023-05-18 10:49:58 +09:30
zilmar 74912ca8c2 Core: handle jump to unaligned addresses 2023-05-18 10:33:57 +09:30
zilmar 6e58edb076 Core: Merge CheckFPUException into CheckFPUResult32 2023-05-15 23:16:54 +09:30
zilmar 62b29622ca Core: remove usage of fpclassify in CheckFPUInput32 and CheckFPUResult32 2023-05-15 22:57:13 +09:30
zilmar 0ddeb6b981 Core: remove exception out of R4300iOp::CheckFPUInput32 2023-05-15 20:56:56 +09:30
zilmar fdc637516f Core: remove Double_RoundToInteger64 2023-05-09 13:05:58 +09:30
zilmar 5a23f48629 Core: remove Double_RoundToInteger32 2023-05-09 12:57:08 +09:30
zilmar e5b1a9469a Core: remove Float_RoundToInteger64 2023-05-09 12:50:23 +09:30
zilmar 2c19c2c362 Core: Handle CPO1 unimplemented op 2023-05-09 11:28:59 +09:30
zilmar 85f4f147a1 Core: Remove Float_RoundToInteger32 2023-05-09 09:40:10 +09:30
zilmar 49a385e743 Core: Split CheckFPUException into CheckFPUException and CheckFPUInvalidException 2023-05-09 08:06:15 +09:30
zilmar fa25b6d2af Core: clear FPU StatusReg cause in CX86RecompilerOps::COP1_S_ADD 2023-05-02 11:12:13 +09:30
zilmar 02a48566c0 Core: Remove helper functions from x86 Recompiler Ops 2023-05-02 10:50:49 +09:30
zilmar 5cfb80fcfc Core: Improve R4300iOp::COP1_S_CVT_W 2023-04-24 19:02:00 +09:30
zilmar 71ef28fd55 Core: Add R4300iOp::COP1_W_CVT_W 2023-04-24 18:55:06 +09:30
zilmar ab8b004b71 Core: Add a setting for fpu reg caching 2023-04-17 18:47:33 +09:30
zilmar cba01b2063 Core: Improve R4300iOp::COP1_L_CVT_D 2023-04-17 18:08:51 +09:30
zilmar d9e69fee65 Core: Improve R4300iOp::COP1_D_CMP 2023-04-17 18:07:58 +09:30
zilmar 0cc6d21ad1 Core: Improve R4300iOp::COP1_S_CMP 2023-04-17 18:06:42 +09:30
zilmar 9297b1c4b8 Core: Improve COP1_S_CVT_D, COP1_W_CVT_D, COP1_D_CVT_S, COP1_W_CVT_S, COP1_L_CVT_S, 2023-04-11 16:20:24 +09:30
zilmar 9a04293a67 Update arm/arm64 to use asmjit 2023-04-05 10:16:21 +09:30
zilmar 2c40d47a34 Start to look at x64 recompiler 2023-04-04 17:44:42 +09:30
zilmar fe35d950f3 x64: Change MemoryStackPos to be a pointer 2023-04-03 09:08:43 +09:30
zilmar 422a42cae3 Core: More work improve the accuracy of cop1 2023-03-28 13:12:59 +10:30
zilmar ce69324dbe Core: Update R4300iOp::COP1_S_MUL to handle exceptions 2023-03-21 10:49:49 +10:30
zilmar cbf67cede4 Core: Update sub.d to handle exceptions 2023-03-20 17:17:31 +10:30
zilmar 96787690c7 Core: Fix CoprocessorUnitNumber on exception 2023-03-20 12:09:06 +10:30
zilmar 7f7aee7232 Core: remove FAKE_CAUSE_REGISTER 2023-03-14 12:14:10 +10:30
David Benepe 96792b18c8
Fixed DPI scaling issue in some debugger windows (#2353) 2023-03-12 16:58:32 +10:30
zilmar 9093b42d47 Core: improve the accuracy of COP1_S_SUB 2023-03-06 20:58:47 +10:30
zilmar 306f21b5fa Core: Improve accuracy of add.d 2023-03-06 18:28:32 +10:30
zilmar a25e5ca4c0 x64: Fix rom browser showing columns 2023-03-04 07:19:35 +10:30
Matando f048fb26e2
Fix MBC30 transferpak support in nrage input plugin (#2292) 2023-03-03 09:58:24 +10:30
zilmar ea70218d1c Clean up warnings 2023-02-28 10:09:08 +10:30
zilmar cb124b7009 x64: Get PluginRSP to build for x64 2023-02-27 11:25:22 +10:30
zilmar 0e5b6cd0e8 Common: update stdstr::Replace with the version of replace being used 2023-02-27 11:02:25 +10:30
zilmar 1864adcb35 Core: improve the accuracy of COP1_S_ADD 2023-02-21 14:54:22 +10:30
jarupxx 3aef396007
Add editbox to choose directory dialog (#2340) 2023-02-14 08:12:38 +10:30
zilmar 3acd56ae61 Core Fix up clang formatting 2023-02-14 08:05:40 +10:30
zilmar 2db5c81af5 Core: Change Project64.rdb so it use 1's and 0's instead of "Yes" or "No" 2023-02-13 21:05:57 +10:30
zilmar e14e10f4b0 Core: Fix handling of R4300iOp::COP1_S_CMP and R4300iOp::COP1_D_CMP 2023-02-13 16:22:50 +10:30