38599b79fe
RSP: Compile_Cop2_MF check for write to r0
2024-07-06 18:53:19 +09:30
1af8570315
RSP: Set max log size as 300mb
2024-07-06 18:51:55 +09:30
0e0f0f7618
RSP: JALR update rd after updating the PC
2024-06-27 16:57:31 +09:30
06eea03d7d
RSP: DelaySlotAffectBranch should clamp PC
2024-06-27 16:34:19 +09:30
661ec98bb3
RSP: User crc32 for crc of imem
2024-06-27 16:25:13 +09:30
96a4c2c926
RSP: Used the wrong reg for write to r0 check on some ops
2024-06-20 21:41:52 +09:30
abfb896142
RSP: Add Compile_Vector_VRNDP, Compile_Vector_VMULQ, Compile_Opcode_LWV
2024-06-20 19:22:57 +09:30
90c0beb01e
RSP: Add Compile_Vector_Reserved
2024-06-20 17:34:37 +09:30
35aeeb6285
RSP: Handle writing to r0 better in recompiler
2024-06-20 17:28:51 +09:30
bb042406be
RSP: Add const to mmx and sse terms
2024-06-13 20:50:54 +09:30
303af24bde
RSP: Better handle delay slot at 0xFFC
2024-06-13 14:54:44 +09:30
c3d6ed1a0c
RSP: Have the code be able to loop
2024-06-13 14:23:59 +09:30
7161a6f591
RSP: Handle break in delay slot
2024-06-13 12:55:23 +09:30
d3411809f7
RSP: Get Recompiler to use LWU
2024-06-13 12:34:28 +09:30
73c9174ce9
Core: Remove Memory exception filer
2024-06-13 11:50:06 +09:30
65a9097980
Allowing a paste into a number field to be trimmed automatically ( #2414 )
...
The specific issue I experienced is that Excel/LibreOffice Calc add a newline when you copy the contents of a single cell. This is bad behavior and they should provide a copy option that does not do that, but alas, it's much harder to get that into those applications. This behavior made it impossible to paste an otherwise-valid hex address into the Project64 fields without first putting it into Notepad, deleting the newline, recopying, and then doing the paste from there. If the field was simply text, you can go into the field edit and shift + home to select all and then do a copy, but that does not work for a formula. When you edit the file, it shows the formula instead. Therefore, you have absolutely no way of working around this except pasting it somewhere else and removing the newline manually.
In principle, there's no reason why you wouldn't trim the ends at least. Whitespace on either end is useless to you. However, content being after the newline should be rejected as it was before.
There were two secondary issues in the pasting code that are fixed here: One is that it only sort of collapsed single spaces. So if you had more than one space, spaces still would have ended up in the result. Actually I think the semantics were slightly more insidious, <space><number> would have turned into <number><same number> effectively. The only thing it did was remove the space by duplicating the number. If you had two spaces, then it would have ended up with e.g. <space><number><same number>. The only case where this wouldn't have happened is a space at the end which would have been preserved in the paste.
Secondly, it mutated the clipboard data directly. This would have lead to confusing results where multiple pastes would have had clipboard data in the clipboard itself move from, for example, two spaces to a single space to no spaces at all. The better solution is to preprocess to figure out how big we ultimately want our space-less result to be and stamp out the copy ourselves skipping anything we don't want. Leave the clipboard alone.
If it's desired to preserve single spaces only in the middle, the code will need to be modified a bit.
Co-authored-by: Summate <summate.ssbm@gmail.com>
2024-06-06 14:22:26 +09:30
0761ad4a83
Fix implementation of quad3d for f3dex 0.95 on pj64 video plugin ( #2427 )
...
* Update ucode01.cpp
* Fix quad3d implementation for f3dex 0.95
* Fix compile
2024-06-06 14:20:46 +09:30
91f9cdaaa7
Core: Change the Program counter to be 64bit
2024-06-06 14:09:12 +09:30
77ac4744a5
Core: Make sure fpu stack is being cleared
2024-05-23 11:52:58 +09:30
0ff0d5234c
Core: In R4300iOp::CheckFPUInput64 check values directly instead of using fpclassify
2024-05-23 11:43:19 +09:30
ec714cd90d
Core: in CX86RecompilerOps::CompileCheckFPUResult64 protect RegPointer before Map_TempReg(asmjit::x86::eax)
2024-05-23 11:41:15 +09:30
3baaa829de
Core: Remove g_TLBLoadAddress, g_TLBStoreAddress global variables
2024-05-16 16:34:17 +09:30
ae21e10a8d
Core: Increase the minimal amount of free space in recompiler memory
2024-05-16 16:15:28 +09:30
a1f46356fb
Core: remove usage of g_RecompPos
2024-05-16 16:08:23 +09:30
7f18773b5b
Core: Add CX86RegInfo::GetFPStatusReg
2024-05-16 15:51:04 +09:30
13bd420b2a
Core: Sync FP status register in advanced block linking
2024-05-16 15:45:38 +09:30
703a09d034
Core: Remove protecting memory option
2024-05-09 17:56:28 +09:30
f478f16269
Core: Clear FP Status flag in recompiler on BC1FL and BC1TL
2024-05-09 10:55:38 +09:30
4c23e7af2c
Core: Remove ChangeFPURegFormat, Load_FPR_ToTop
2024-05-02 17:21:01 +09:30
c786bc3251
Core: Force Fpu exception in recompiler
2024-05-02 16:34:13 +09:30
b3e8b760e6
Core: get COP1_S_TRUNC_L, COP1_S_CEIL_L, COP1_S_FLOOR_L, COP1_W_CVT_S, COP1_W_CVT_D, COP1_L_CVT_S, COP1_L_CVT_D to use COP1_S_CVT function
2024-05-02 15:48:43 +09:30
dd0f7ad776
Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword
2024-05-02 15:46:03 +09:30
046f27ce98
Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT
2024-04-25 20:47:02 +09:30
627b4d6103
Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv
2024-04-25 20:41:03 +09:30
b92e6bd752
Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT
2024-04-25 20:22:47 +09:30
d658477cf4
Core: get CX86RecompilerOps::Compile_Branch to clear status flags
2024-04-18 17:31:19 +09:30
b313640831
Core: In CX86RegInfo::Map_TempReg allow it to use FPStatusReg if it is unprotected
2024-04-18 17:28:23 +09:30
1172b6e04d
Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly
2024-04-18 17:21:39 +09:30
38738b783d
Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword
2024-04-18 17:11:45 +09:30
7dc53e51cf
Core: Get CompileCheckFPUInput to better handle 64bit value check
2024-04-18 17:00:29 +09:30
a9875b7d61
Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation
2024-04-18 16:58:18 +09:30
3203322d8b
Core: Get COP1_D_CVT_L to use COP1_S_CVT
2024-04-18 16:56:30 +09:30
9e73771815
Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L
2024-04-18 16:51:53 +09:30
fe87142657
Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation
2024-04-18 16:42:48 +09:30
4071b52810
Core: CX86RegInfo::UnMap_X86reg should fail on a protected register
2024-04-18 16:41:03 +09:30
79f7aa9927
Core: CX86RegInfo::UnMap_FPStatusReg should unprotect register before trying to free it
2024-04-18 16:34:49 +09:30
0cf4c7dc11
Core: get COP1_D_CMP to work in recompiler
2024-04-11 18:14:44 +09:30
9272ac05f6
Core: refactor S opcodes to one central function
2024-04-11 18:09:30 +09:30
e7178dbdec
Core: Fix CX86RecompilerOps::COP1_D_CVT_S
2024-03-28 20:05:27 +10:30
8bb2445263
Core: Have CX86RecompilerOps::CompileCheckFPUResult32 write to the high word
2024-03-28 20:02:24 +10:30
560c49ba2d
Core: Fix N64 disk IPL load address check ( #2401 )
...
The IPL load address check always evaluated to false due
to a wrong operator.
Signed-off-by: Francois Berder <fberder@outlook.fr>
2024-03-21 17:52:09 +10:30
45fb2ad965
Core: In X86RecompilerOps::CompileCheckFPUResult64 make sure RegPointer is protected
2024-03-21 17:44:53 +10:30
2811b63ff0
Core: Update CX86RecompilerOps::COP1_D_CVT_S and CX86RecompilerOps::COP1_D_CVT_W
2024-03-21 17:41:29 +10:30
33d2722841
Core: fix up CX86RecompilerOps::COP1_D_FLOOR_W
2024-03-21 17:40:14 +10:30
9a9c2e5439
Core: Update CX86RecompilerOps::COP1_D_CEIL_W
2024-03-21 17:32:12 +10:30
401efae0d9
Core: fix up CX86RecompilerOps::COP1_D_ROUND_W
2024-03-21 17:28:16 +10:30
772a20f07d
Core: Update CX86RecompilerOps::COP1_D_SQRT
2024-03-21 17:15:10 +10:30
87c732b65d
Core: update CX86RecompilerOps::COP1_D_NEG
2024-03-21 17:14:00 +10:30
ece5e30a80
Core: create a function to handle .d recompiler opcodes that use fd and fs
2024-03-21 17:13:16 +10:30
5133d47502
Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode
2024-03-14 18:12:58 +10:30
98b1bddc64
Core: Get COP1_D_ADD, COP1_D_SUB, COP1_D_DIV, COP1_D_ABS, COP1_D_SQRT
2024-03-07 21:12:57 +10:30
97ec1f533b
Core: Make sure precision is set to 53bit
2024-03-07 20:52:24 +10:30
190c408019
Core: Fix clang formatting in x86/x86RecompilerOps.cpp
2024-02-29 16:06:56 +10:30
f7aa6ef6cb
Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions
2024-02-29 15:16:29 +10:30
25dc3ed36f
Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes
2024-02-29 15:13:14 +10:30
d2649f7a13
Core: Some clean up recompiler ops
2024-02-22 19:56:23 +10:30
fae0b81e21
Core: Have CX86RegInfo::Map_TempReg generate a BreakPoint if it mapping a protected register
2024-02-22 19:41:10 +10:30
e082cd55df
Core: Get COP1_D_TRUNC_W to work in recompiler
2024-02-15 21:08:49 +10:30
2559d23592
Core: Make sure CX86RecompilerOps::CompileInitFpuOperation clears flag for FE_INVALID
2024-02-15 21:02:27 +10:30
46f6fae40f
Core: get CompileCheckFPUInput to be able to handle 32bit and 64bit
2024-02-15 21:00:12 +10:30
2014237ed6
Core: Update Round.w.s, trunc.w.s, ceil.w.s, floor.w.s to work with exceptions in the recompiler
2024-02-08 19:34:14 +10:30
ad1a2a2d9a
Core: Update neg.s for the recompiler
2024-02-01 18:17:03 +10:30
b6671adf5d
Core: Update abs.s for recompiler
2024-02-01 18:15:33 +10:30
bc3fe0fe16
Core: Handle FP Status Reg being mapped better
2024-01-25 18:46:39 +10:30
7707f9c7b2
Core: Fix up mov.s and mov.d for correct behaviour in the recompiler
2024-01-25 16:25:06 +10:30
272144dc37
Core: check timer on cop1 unusable
2024-01-25 16:23:03 +10:30
f0f44c67f4
Core: Make mov.s the same as mov.d
2024-01-25 15:32:56 +10:30
7ed94b653e
Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions
2024-01-18 17:09:27 +10:30
2231e8d6c0
Core: Remove usage of fpclassify from R4300iOp::CheckFPUResult64
2024-01-18 16:53:14 +10:30
71067ccdc4
Rsp: Change how SP_SEMAPHORE_REG to how it use to be before adding multithread RSP
2024-01-11 18:17:05 +10:30
5c56f9df83
RSP: Update the size of the skip in the length for DMA
2024-01-11 17:50:23 +10:30
4dc3e35bb4
Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions
2024-01-04 16:51:11 +10:30
f8089f565e
Core: Unmap FPU_Float with writing to m_FPR_UDW
2024-01-04 14:40:42 +10:30
552b8f744a
Core: update Format_Name to match FPU_STATE
2024-01-04 13:11:21 +10:30
6ca8333d39
Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions
2024-01-04 12:39:51 +10:30
c9d2bbd221
Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped
2024-01-04 12:37:06 +10:30
0998f0ff0e
Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer
2024-01-04 12:32:55 +10:30
23cff4d7c5
Core: Add x86 asm opcode Jnp
2024-01-04 12:31:26 +10:30
91a8a828d7
Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW
2024-01-04 12:01:21 +10:30
320769d991
Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr
2024-01-04 10:33:07 +10:30
dafa1fb24d
Core: Have COP1_W_CVT_S handle the initialization of exceptions
2023-12-28 11:19:06 +10:30
17288c90c0
Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32
2023-12-28 10:23:18 +10:30
e2306e3541
Core: Get COP1_S_CVT_W to handle inexact
2023-12-28 09:21:53 +10:30
8399fdb893
Core: Clear the Divide-by-zero flag
2023-12-21 21:24:33 +10:30
d14a639a62
Core: Implement COP1_S_DIV with fpu exceptions
2023-12-21 14:11:29 +10:30
8e54ec8c8e
Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis
2023-12-21 14:10:21 +10:30
b263ee10b0
Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0
2023-12-21 10:41:16 +10:30
1810bfda5c
Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops
2023-12-21 10:38:49 +10:30
2c1610cfe2
Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode
2023-12-21 10:37:27 +10:30
6610ae3058
Core: Have R4300iInstruction in CRecompilerOpsBase
2023-12-21 10:34:03 +10:30
8e3fb3e302
Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference
2023-12-21 10:26:10 +10:30
c8e73ba18e
Core: Handle unaligned SW exception in the recompiler
2023-12-14 23:04:26 +10:30
972943cff7
Core: Allow LW to R0 be able to generate an exception
2023-12-14 17:21:52 +10:30
89a6eaf9d1
Core: Add RecordLLAddress for 32bit register pointer
2023-12-14 13:52:15 +10:30
67f5e4f854
Core: in LL for recompiler handle storing the address in COP[17]
2023-12-14 13:10:20 +10:30
d5a5f4cdac
Core: Have Store Instruc rdb and user rdb matching
2023-12-14 12:21:03 +10:30
5fec3f8d31
Core: remove the global of g_TLB
2023-12-14 12:09:24 +10:30
c67f3f0e97
Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it
2023-12-14 11:18:07 +10:30
15175d3fe2
Core: Fix bug in not creating save state correctly
2023-12-07 17:43:48 +10:30
de1288bdca
Core: remove try/catch around Interpreter cpu
2023-11-30 21:15:14 +10:30
df56964c96
Android: Remove unneeded log call
2023-11-30 21:13:27 +10:30
5671f2b759
Android: Update how Addu cause android studio was not sign extending result
2023-11-30 21:12:53 +10:30
acbb8f85a8
Fix typo in support window code ( #2395 )
...
* Fix typo in support window
* Fix the typo for real
2023-11-23 22:54:19 +10:30
01673dac8d
Core: Change TriggerAddressException to SetVPN an R of entry hi in one call
2023-11-23 14:20:48 +10:30
d47b49d4b5
Core: Fix clang issue
2023-11-16 18:24:47 +10:30
542afc4514
Core: remove some accidental added debug code
2023-11-16 18:16:35 +10:30
ee714e2462
Core: On unmap base addresses reset to the correct address
2023-11-16 18:14:15 +10:30
8f4f434820
Core: Get Fast tlb to just be 32bit
2023-11-16 17:11:05 +10:30
dcb6969067
Core: Have entryHI use functions to set/get parts
2023-11-16 09:19:24 +10:30
a0130ff896
Core: Convert %I64U to %llx
2023-11-16 09:03:32 +10:30
e46ffde6b3
fix clang formatting
2023-11-09 12:59:40 +10:30
296b7cf1cf
Android: Force RSP to be interpret
2023-11-09 12:45:36 +10:30
0c8b10bbc7
Android: Get RSP core to compile on android
2023-11-09 11:53:06 +10:30
09cc3442a2
Android: fix compile bug
2023-11-02 20:27:38 +10:30
6fbc5c0264
Android: Move hle audio code in to main rsp plugin
2023-11-02 20:06:58 +10:30
e6edbc6c82
Fix clang formatting
2023-10-27 10:14:21 +10:30
4770d29ec0
Core: Get system events to be internal not global
2023-10-26 19:59:11 +10:30
d3f4132770
Android: When listing a rom not in rdb, use game file instead
2023-10-26 11:18:24 +10:30
b74e21d056
Android: Show base dir to splash logs when starting
2023-10-26 11:17:49 +10:30
bf480623bd
[Android] Add Android/Bridge to clang checking
2023-10-26 11:05:20 +10:30
8f062975c3
Core: improve DisplayControlRegHandler::Write32
2023-10-19 19:28:38 +10:30
d6a2ae80c1
Core: Remove SystemRegisters
2023-10-19 14:56:53 +10:30
d58168bcb9
Core: R4300iOp access the registers directly, not through CSystemRegisters
2023-10-19 12:52:33 +10:30
4d78f56aa2
Core: In R4300iOp have a member variable for system, reg, mmu
2023-10-19 12:31:26 +10:30
ae0097550f
Core: Make R4300iOp opcodes not static
2023-10-19 11:43:32 +10:30
7f42f70283
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
2023-10-19 10:28:25 +10:30
d3edbf6dda
Core: move CInterpreterCPU into R4300iOp
2023-10-19 09:32:42 +10:30
d4dbc5a3f4
Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio
2023-10-14 11:53:35 +10:30
00c5057b17
Core: Make sure precision is correct for COP1_D_SQRT
2023-10-13 00:16:14 +10:30
3a68d3d92a
Core: LL/LLD store address
2023-10-12 19:55:29 +10:30
a6405cfa2d
Core: Add masking around DPC_START_REG/DPC_END_REG
2023-10-12 17:50:58 +10:30
4e71221147
Core: Fix up FPU mode register location
2023-10-12 14:53:44 +10:30
befa57924d
Core: Fix clang compile issues
2023-10-05 15:01:09 +10:30
f73c3708a5
Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
2023-10-05 14:45:17 +10:30
e74e8f6a23
Core: Have load/store ops be able to use 64bit addresses
2023-10-05 14:28:32 +10:30
9f07fe2aac
Core: Get tlb addresses to be 64bit
2023-10-05 13:42:31 +10:30
4b844495b7
Core: Have save states handle COP0/TLB being 64bit now
...
Core: Clean up tlb class
2023-10-05 13:10:45 +10:30
35105e814e
Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
2023-10-05 09:54:41 +10:30
b7311cc611
Core: Change Non memory load/store to not use tlb
2023-10-05 09:32:45 +10:30
a975af0e3c
Rsp: only use alignas for Visual Studio
2023-09-28 16:18:39 +09:30
zilmar