zilmar
|
bfa3788562
|
Core: CX86RecompilerOps::COP1_D_Opcode fix return type of floating point register
|
2024-12-26 14:29:52 +10:30 |
|
zilmar
|
3c7e71adca
|
Core: Fix up CX86RecompilerOps::COP1_D_Opcode for the registers it is using
|
2024-12-26 14:16:26 +10:30 |
|
zilmar
|
fc79cb0344
|
Core: Add DwordLower for cvt.w
|
2024-12-26 09:35:07 +10:30 |
|
zilmar
|
7e74b98d5b
|
Core: Fix up labels in CX86RecompilerOps::COP1_S_CVT
|
2024-12-19 21:59:42 +10:30 |
|
zilmar
|
57f278416e
|
core: better handling of fpu registers with COP1_S_Opcode
|
2024-12-19 19:09:31 +10:30 |
|
zilmar
|
13a974e687
|
Core: in CX86RecompilerOps::COP1_CT ignore write to other registers
|
2024-12-19 09:58:30 +10:30 |
|
zilmar
|
fba1c4bc3b
|
Core: Fix up bug in CX86RecompilerOps::SPECIAL_AND
|
2024-12-19 09:57:25 +10:30 |
|
zilmar
|
473aeba2cf
|
Core: Fix order of value in call to CMipsMemoryVM::SD_VAddr32 in recompiler
|
2024-12-12 21:22:32 +10:30 |
|
zilmar
|
5d64b3d920
|
Core: Better handling of Storing non 32bit values to non memory
|
2024-12-12 16:50:36 +10:30 |
|
zilmar
|
b8ee9f8728
|
RSP: Add #include <intrin.h> to RSPInfo.cpp for 64bit
|
2024-12-12 14:17:07 +10:30 |
|
zilmar
|
3164caf2d0
|
Core: allow Store/load ops be forced to 32bit version
|
2024-12-08 11:15:39 +10:30 |
|
zilmar
|
5a5ea92f3f
|
fix resource issues
|
2024-12-07 08:52:01 +10:30 |
|
zilmar
|
b9fe8e3657
|
Fix compile issues
|
2024-12-07 07:04:22 +10:30 |
|
zilmar
|
8392ea5c0f
|
Core fix up load states
|
2024-12-06 21:50:31 +10:30 |
|
zilmar
|
a045a4fcd4
|
Core: fix accidental changes to UIResources.rc
|
2024-12-06 11:37:42 +10:30 |
|
zilmar
|
c6b41da926
|
Add Overclock modifier to Defaults panel
|
2024-12-05 17:30:59 +10:30 |
|
zilmar
|
77cd679756
|
Core: Fix a bug in CX86RecompilerOps::SPECIAL_DIV
|
2024-12-05 17:05:52 +10:30 |
|
zilmar
|
fc1210aac5
|
Core: Do not allow CX86RecompilerOps::SPECIAL_DSRL32 and CX86RecompilerOps::SPECIAL_DSRA32 to write to R0
|
2024-12-05 11:25:20 +10:30 |
|
zilmar
|
1e4ab04121
|
Core: Fix up CX86RecompilerOps::SPECIAL_DSUB when rd == rt
|
2024-12-05 11:06:42 +10:30 |
|
zilmar
|
04c1c3d024
|
Core: Fix up CX86RecompilerOps::SPECIAL_DADD
|
2024-12-05 10:03:45 +10:30 |
|
zilmar
|
1f3ef6d505
|
Core: CX86RecompilerOps::SPECIAL_NOR Ignore write to r0
|
2024-11-28 15:54:36 +10:30 |
|
zilmar
|
95015302d6
|
Core: Have CX86RecompilerOps::SPECIAL_XOR treat R0 as 64bit constant
|
2024-11-28 15:38:54 +10:30 |
|
zilmar
|
a3c777ed84
|
Core: Have CX86RecompilerOps::SPECIAL_AND unmap the register on const write
|
2024-11-28 15:14:26 +10:30 |
|
zilmar
|
0de0bea07a
|
Core: Ignore write in CX86RecompilerOps::SPECIAL_OR
|
2024-11-28 12:37:42 +10:30 |
|
zilmar
|
8d69671e93
|
Core: CX86RecompilerOps::ADDIU should not ignore when not 32bit mapped
|
2024-11-28 12:29:35 +10:30 |
|
zilmar
|
52d904702f
|
Core: With CONST64 CX86RegInfo::WriteBackRegisters might not write the high 32bit correct
|
2024-11-28 11:39:41 +10:30 |
|
zilmar
|
d5367d9291
|
Core: Better handling of SW with address not sign extended
|
2024-11-28 11:02:38 +10:30 |
|
zilmar
|
fd05d9f42f
|
core: if lwl or lwr, in CX86RecompilerOps::CompileLoadMemoryValue, make sure that we are loading rt
|
2024-11-21 21:33:42 +10:30 |
|
zilmar
|
315d5b9e66
|
Core: When running as recompiler in 32bit mode, if LW/SW are in delay slots on block boundaries use 32bit interpter functions
|
2024-11-21 19:13:56 +10:30 |
|
zilmar
|
5e1a40fffb
|
Core: fix CX86RecompilerOps::CompileLoadMemoryValue Map_GPR_32bit when called from LWC1
|
2024-11-21 11:10:01 +10:30 |
|
zilmar
|
48b3e5a9a2
|
Core: Zip load in CN64System::LoadState uses utf16 path
|
2024-11-21 10:48:16 +10:30 |
|
zilmar
|
58a13b8e28
|
Core: Get Zip files to use utf16 paths
|
2024-11-21 10:43:56 +10:30 |
|
zilmar
|
2ec9ed08a4
|
Core: Improve LW with address not sign extended test in recompiler
|
2024-11-14 17:02:18 +10:30 |
|
zilmar
|
944dd0917a
|
Core: Fix up logging id for label symbols
|
2024-11-14 09:31:45 +10:30 |
|
zilmar
|
61aa53f1a5
|
Core: In jump ops, Only add label symbol if logging
|
2024-11-14 07:30:39 +10:30 |
|
zilmar
|
97b2579b4b
|
Core: Have the recompiler just deal with the Program Counter as 32bit
|
2024-11-07 17:05:16 +10:30 |
|
zilmar
|
f63244cfa4
|
Core: Handle duplicate symbols in AddLabelSymbol
|
2024-11-07 13:37:10 +10:30 |
|
zilmar
|
72e6ee1a2b
|
Core: Normalize RomDatabase, VideoRDB, AudioRdb file paths
|
2024-11-07 13:24:45 +10:30 |
|
zilmar
|
e419508c2b
|
Core: On ExitReason_CheckPCAlignment make sure CompileSystemCheck is called
|
2024-11-07 12:13:28 +10:30 |
|
zilmar
|
a46ac9f38d
|
Core: in CX86Ops::_log better handle label symbols
|
2024-11-07 12:12:44 +10:30 |
|
zilmar
|
d06212e766
|
Core: CX86RecompilerOps::JAL stop double call to UpdateCounters
|
2024-11-07 11:05:55 +10:30 |
|
zilmar
|
bfd181f33e
|
Core: Fix up recompiler log including 0x in number symbols
|
2024-11-07 09:22:56 +10:30 |
|
zilmar
|
f3a3d56c13
|
Gliden64: Fix up x64 build with including UI
|
2024-10-31 08:12:52 +10:30 |
|
zilmar
|
24d5a6bd65
|
Core: fix up clang formatting
|
2024-10-31 07:01:32 +10:30 |
|
zilmar
|
905254615d
|
Core: Change the handling of symbols inside asmjit usage
|
2024-10-31 06:50:17 +10:30 |
|
zilmar
|
17c501fa08
|
Core: clean up some code related to CompileStoreMemoryValue, like the exit method being an exception
|
2024-10-24 13:32:02 +10:30 |
|
zilmar
|
a8c8e751fc
|
Core: log the block code to the asm log file
|
2024-10-24 12:11:15 +10:30 |
|
zilmar
|
885d31f275
|
Core: Update Map_MemoryStack to pass gp by reference
|
2024-10-24 12:01:14 +10:30 |
|
zilmar
|
440894992a
|
Core: remove the BreakPoint in handling ExitReason_CheckPCAlignment
|
2024-10-24 11:58:53 +10:30 |
|
zilmar
|
65ede5e3e8
|
Core: If jumping to an unaligned address then generate an exception
|
2024-10-24 10:31:48 +10:30 |
|
zilmar
|
4a42466559
|
Core: In compiling a block be able to trace the time to compile
|
2024-10-24 10:04:45 +10:30 |
|
zilmar
|
5750d3df80
|
Core: Have only one function to do what R4300iOp::ExecuteOps and R4300iOp::ExecuteCPU was doing
|
2024-10-24 09:59:41 +10:30 |
|
zilmar
|
c39582b9ed
|
Core: Make sure CX86RecompilerOps::SPECIAL_AND can not write to R0
|
2024-10-17 18:42:45 +10:30 |
|
zilmar
|
a38467cc19
|
Core: Reset Memory Stack Pos In recompiler after running interpter code at non rdram location
|
2024-10-17 18:40:37 +10:30 |
|
zilmar
|
f708e5c0b2
|
Core: Check recompiler memory based on the function size
|
2024-10-17 15:05:48 +10:30 |
|
zilmar
|
45e52e1d2a
|
Core: in SPECIAL_SYSCALL, SPECIAL_BREAK only exit the block is the stage is PIPELINE_STAGE_NORMAL
|
2024-10-17 14:12:46 +10:30 |
|
zilmar
|
ccf708751f
|
Core: Fix up clang error
|
2024-10-11 07:09:03 +10:30 |
|
Squall Leonhart
|
0d95a0cd7f
|
quick dirty possible fix for MBC5 roms of 4 and 8MB size. (#2442)
|
2024-10-10 18:04:31 +10:30 |
|
zilmar
|
a2e479a705
|
Core: Handle paths with non-ASCII characters
|
2024-10-10 18:01:10 +10:30 |
|
zilmar
|
c176f61aac
|
Core: Normalize Plugin dir
|
2024-10-10 10:12:53 +10:30 |
|
zilmar
|
30090e5db7
|
Core: in CX86Ops::CX86Ops set setLogger to nullptr if not logging
|
2024-10-03 16:22:42 +09:30 |
|
zilmar
|
9e53b161a4
|
Cote Update PeripheralInterfaceHandler::PI_DMA_WRITE to handle misaligned, end of page test
|
2024-10-03 14:38:04 +09:30 |
|
zilmar
|
08e1b3b39b
|
fix up clang formatting
|
2024-09-26 18:54:54 +09:30 |
|
zilmar
|
62bf10e505
|
Core: Have fpu ops check the input of fs and ft at the same time
|
2024-09-26 16:38:25 +09:30 |
|
zilmar
|
dc4fa211b0
|
Core: Clean up RDRAM/RI Registers
|
2024-09-26 12:59:32 +09:30 |
|
zilmar
|
544d6ba1b9
|
Core: Normalize Path for RomList_RomListCache
|
2024-09-26 07:30:26 +09:30 |
|
zilmar
|
cd9fc5984a
|
RSP: Make sure m_SyncSystem is valid before checking m_SyncSystem->m_BaseSystem on shutdown
|
2024-09-26 06:50:48 +09:30 |
|
zilmar
|
7cb0c258a1
|
GLideN64: Slight clean up of project file
|
2024-09-19 12:16:46 +09:30 |
|
zilmar
|
c098a6a464
|
RSP: Be able to compile sections based off tasks
|
2024-09-19 12:15:11 +09:30 |
|
zilmar
|
3340c032c3
|
RSP: Move CompilePC into RspRecompilerCPU
|
2024-09-19 08:31:28 +09:30 |
|
zilmar
|
df9b04bb5b
|
RSP: Change RunInterpreterCPU to ExecuteOps
|
2024-09-12 15:13:45 +09:30 |
|
zilmar
|
07e8f8b830
|
Gliden64: Get the new GlideN64 submodule to build as part of the normal build process
|
2024-09-12 09:44:38 +09:30 |
|
zilmar
|
02e816b9d4
|
Update package_zip.cmd to deal with platform in path
|
2024-09-05 19:22:25 +09:30 |
|
zilmar
|
ea199c5546
|
Update installer to have new binary path
|
2024-09-05 18:50:47 +09:30 |
|
zilmar
|
aaa6fc8082
|
Core: Add $(Platform) to the output directory
|
2024-09-05 17:54:58 +09:30 |
|
zilmar
|
00a92871c0
|
Gliden64: Add as a submodule
|
2024-09-05 11:17:26 +09:30 |
|
zilmar
|
eb985de132
|
RSP: Start to add CPU style HLE
|
2024-08-29 15:37:52 +09:30 |
|
zilmar
|
5eac210197
|
RSP: Start to have a RSP Settings class
|
2024-08-29 11:26:53 +09:30 |
|
zilmar
|
96080bfdd2
|
RSP: change CRSPSystem::m_Recompiler from a pointer to a member and initialize it at creation of system
|
2024-08-29 07:49:40 +09:30 |
|
zilmar
|
2b7975280e
|
RSP: Have NextInstruction and JumpTo members of RSP System instead of a global variable
|
2024-08-22 19:44:07 +09:30 |
|
zilmar
|
29c49a2063
|
RSP: Remove PrgCount as a global
|
2024-08-22 17:32:05 +09:30 |
|
zilmar
|
d9ae43b69d
|
RSP: have RSPRegisterHandlerPlugin as part of RSP System instead of a global
|
2024-08-22 16:30:20 +09:30 |
|
zilmar
|
4681f07bf8
|
RSP: Move rdp logging in to it's own class
|
2024-08-15 13:43:56 +09:30 |
|
zilmar
|
6ed1c3edfb
|
RSP: internalize RSP information in to interpter ops
|
2024-08-15 07:36:53 +09:30 |
|
zilmar
|
9f98f4d4cd
|
Rsp: Change RSPOpC to be a class member
|
2024-08-08 12:55:54 +09:30 |
|
zilmar
|
762d1b1566
|
RSP: Create CRSPRecompiler
|
2024-08-08 09:39:45 +09:30 |
|
zilmar
|
f7ab608976
|
RSP: Create CRSPRegisters
|
2024-08-08 07:26:15 +09:30 |
|
zilmar
|
1924030266
|
RSP: Move compile functions into CRSPRecompilerOps
|
2024-08-02 22:00:01 +09:30 |
|
zilmar
|
2904d3641d
|
RSP: Create RSP system class and move all interpter ops in to RSPOp class
|
2024-08-02 09:00:38 +09:30 |
|
zilmar
|
dab432e7bd
|
RSP: clean up LDV
|
2024-07-20 19:10:36 +09:30 |
|
zilmar
|
9d7b391487
|
RSP: Fix up LSV in the recompiler
|
2024-07-20 17:09:41 +09:30 |
|
zilmar
|
7c2655c544
|
RSP: Remove some unused functions and turn Reordering and Sections off by default
|
2024-07-20 17:08:20 +09:30 |
|
zilmar
|
6816ff4435
|
RSP: Disable a lot of ops that are not functioning correctly in the recompiler
|
2024-07-20 17:05:11 +09:30 |
|
zilmar
|
13fb8cd2da
|
RSP: In Compile_Opcode_SQV Cheat the op instead of causing an unknown opcode
|
2024-07-12 15:23:59 +09:30 |
|
zilmar
|
564926163c
|
RSP: in Compile_Opcode_SSV cheat the op instead of generating an unknown opcode
|
2024-07-12 15:07:23 +09:30 |
|
zilmar
|
8c6856f1c8
|
RSP: Have Compile_SW handle DMEM overflow better
|
2024-07-12 15:04:18 +09:30 |
|
zilmar
|
6e4852fc78
|
RSP: have Compile_LW handle DMEM overflow better
|
2024-07-12 15:02:46 +09:30 |
|
zilmar
|
e43d697476
|
RSP: Handle lwu inside IsRegisterConstant
|
2024-07-12 15:01:05 +09:30 |
|
zilmar
|
7b013c3deb
|
RSP: Reset secondary buffer to start on ResetJumpTables
|
2024-07-12 14:59:16 +09:30 |
|
zilmar
|
e2243fe8eb
|
RSP: Make sure RSP block ends with a ret
|
2024-07-06 19:36:10 +09:30 |