a38467cc19
Core: Reset Memory Stack Pos In recompiler after running interpter code at non rdram location
2024-10-17 18:40:37 +10:30
f708e5c0b2
Core: Check recompiler memory based on the function size
2024-10-17 15:05:48 +10:30
45e52e1d2a
Core: in SPECIAL_SYSCALL, SPECIAL_BREAK only exit the block is the stage is PIPELINE_STAGE_NORMAL
2024-10-17 14:12:46 +10:30
ccf708751f
Core: Fix up clang error
2024-10-11 07:09:03 +10:30
0d95a0cd7f
quick dirty possible fix for MBC5 roms of 4 and 8MB size. ( #2442 )
2024-10-10 18:04:31 +10:30
a2e479a705
Core: Handle paths with non-ASCII characters
2024-10-10 18:01:10 +10:30
c176f61aac
Core: Normalize Plugin dir
2024-10-10 10:12:53 +10:30
30090e5db7
Core: in CX86Ops::CX86Ops set setLogger to nullptr if not logging
2024-10-03 16:22:42 +09:30
9e53b161a4
Cote Update PeripheralInterfaceHandler::PI_DMA_WRITE to handle misaligned, end of page test
2024-10-03 14:38:04 +09:30
08e1b3b39b
fix up clang formatting
2024-09-26 18:54:54 +09:30
62bf10e505
Core: Have fpu ops check the input of fs and ft at the same time
2024-09-26 16:38:25 +09:30
dc4fa211b0
Core: Clean up RDRAM/RI Registers
2024-09-26 12:59:32 +09:30
544d6ba1b9
Core: Normalize Path for RomList_RomListCache
2024-09-26 07:30:26 +09:30
cd9fc5984a
RSP: Make sure m_SyncSystem is valid before checking m_SyncSystem->m_BaseSystem on shutdown
2024-09-26 06:50:48 +09:30
7cb0c258a1
GLideN64: Slight clean up of project file
2024-09-19 12:16:46 +09:30
c098a6a464
RSP: Be able to compile sections based off tasks
2024-09-19 12:15:11 +09:30
3340c032c3
RSP: Move CompilePC into RspRecompilerCPU
2024-09-19 08:31:28 +09:30
df9b04bb5b
RSP: Change RunInterpreterCPU to ExecuteOps
2024-09-12 15:13:45 +09:30
07e8f8b830
Gliden64: Get the new GlideN64 submodule to build as part of the normal build process
2024-09-12 09:44:38 +09:30
02e816b9d4
Update package_zip.cmd to deal with platform in path
2024-09-05 19:22:25 +09:30
ea199c5546
Update installer to have new binary path
2024-09-05 18:50:47 +09:30
aaa6fc8082
Core: Add $(Platform) to the output directory
2024-09-05 17:54:58 +09:30
00a92871c0
Gliden64: Add as a submodule
2024-09-05 11:17:26 +09:30
eb985de132
RSP: Start to add CPU style HLE
2024-08-29 15:37:52 +09:30
5eac210197
RSP: Start to have a RSP Settings class
2024-08-29 11:26:53 +09:30
96080bfdd2
RSP: change CRSPSystem::m_Recompiler from a pointer to a member and initialize it at creation of system
2024-08-29 07:49:40 +09:30
2b7975280e
RSP: Have NextInstruction and JumpTo members of RSP System instead of a global variable
2024-08-22 19:44:07 +09:30
29c49a2063
RSP: Remove PrgCount as a global
2024-08-22 17:32:05 +09:30
d9ae43b69d
RSP: have RSPRegisterHandlerPlugin as part of RSP System instead of a global
2024-08-22 16:30:20 +09:30
4681f07bf8
RSP: Move rdp logging in to it's own class
2024-08-15 13:43:56 +09:30
6ed1c3edfb
RSP: internalize RSP information in to interpter ops
2024-08-15 07:36:53 +09:30
9f98f4d4cd
Rsp: Change RSPOpC to be a class member
2024-08-08 12:55:54 +09:30
762d1b1566
RSP: Create CRSPRecompiler
2024-08-08 09:39:45 +09:30
f7ab608976
RSP: Create CRSPRegisters
2024-08-08 07:26:15 +09:30
1924030266
RSP: Move compile functions into CRSPRecompilerOps
2024-08-02 22:00:01 +09:30
2904d3641d
RSP: Create RSP system class and move all interpter ops in to RSPOp class
2024-08-02 09:00:38 +09:30
dab432e7bd
RSP: clean up LDV
2024-07-20 19:10:36 +09:30
9d7b391487
RSP: Fix up LSV in the recompiler
2024-07-20 17:09:41 +09:30
7c2655c544
RSP: Remove some unused functions and turn Reordering and Sections off by default
2024-07-20 17:08:20 +09:30
6816ff4435
RSP: Disable a lot of ops that are not functioning correctly in the recompiler
2024-07-20 17:05:11 +09:30
13fb8cd2da
RSP: In Compile_Opcode_SQV Cheat the op instead of causing an unknown opcode
2024-07-12 15:23:59 +09:30
564926163c
RSP: in Compile_Opcode_SSV cheat the op instead of generating an unknown opcode
2024-07-12 15:07:23 +09:30
8c6856f1c8
RSP: Have Compile_SW handle DMEM overflow better
2024-07-12 15:04:18 +09:30
6e4852fc78
RSP: have Compile_LW handle DMEM overflow better
2024-07-12 15:02:46 +09:30
e43d697476
RSP: Handle lwu inside IsRegisterConstant
2024-07-12 15:01:05 +09:30
7b013c3deb
RSP: Reset secondary buffer to start on ResetJumpTables
2024-07-12 14:59:16 +09:30
e2243fe8eb
RSP: Make sure RSP block ends with a ret
2024-07-06 19:36:10 +09:30
9b38977b31
RSP: Fix up recompiler jumps JAL, BLTZAL, BGEZAL
2024-07-06 19:33:10 +09:30
4125774be8
RSP: Add Vector_VRNDN and fix up compile jump table
2024-07-06 19:08:20 +09:30
2a149beb69
RSP: Clean up #ifdef in Recompiler
2024-07-06 19:04:50 +09:30
38599b79fe
RSP: Compile_Cop2_MF check for write to r0
2024-07-06 18:53:19 +09:30
1af8570315
RSP: Set max log size as 300mb
2024-07-06 18:51:55 +09:30
0e0f0f7618
RSP: JALR update rd after updating the PC
2024-06-27 16:57:31 +09:30
06eea03d7d
RSP: DelaySlotAffectBranch should clamp PC
2024-06-27 16:34:19 +09:30
661ec98bb3
RSP: User crc32 for crc of imem
2024-06-27 16:25:13 +09:30
96a4c2c926
RSP: Used the wrong reg for write to r0 check on some ops
2024-06-20 21:41:52 +09:30
abfb896142
RSP: Add Compile_Vector_VRNDP, Compile_Vector_VMULQ, Compile_Opcode_LWV
2024-06-20 19:22:57 +09:30
90c0beb01e
RSP: Add Compile_Vector_Reserved
2024-06-20 17:34:37 +09:30
35aeeb6285
RSP: Handle writing to r0 better in recompiler
2024-06-20 17:28:51 +09:30
bb042406be
RSP: Add const to mmx and sse terms
2024-06-13 20:50:54 +09:30
303af24bde
RSP: Better handle delay slot at 0xFFC
2024-06-13 14:54:44 +09:30
c3d6ed1a0c
RSP: Have the code be able to loop
2024-06-13 14:23:59 +09:30
7161a6f591
RSP: Handle break in delay slot
2024-06-13 12:55:23 +09:30
d3411809f7
RSP: Get Recompiler to use LWU
2024-06-13 12:34:28 +09:30
73c9174ce9
Core: Remove Memory exception filer
2024-06-13 11:50:06 +09:30
65a9097980
Allowing a paste into a number field to be trimmed automatically ( #2414 )
...
The specific issue I experienced is that Excel/LibreOffice Calc add a newline when you copy the contents of a single cell. This is bad behavior and they should provide a copy option that does not do that, but alas, it's much harder to get that into those applications. This behavior made it impossible to paste an otherwise-valid hex address into the Project64 fields without first putting it into Notepad, deleting the newline, recopying, and then doing the paste from there. If the field was simply text, you can go into the field edit and shift + home to select all and then do a copy, but that does not work for a formula. When you edit the file, it shows the formula instead. Therefore, you have absolutely no way of working around this except pasting it somewhere else and removing the newline manually.
In principle, there's no reason why you wouldn't trim the ends at least. Whitespace on either end is useless to you. However, content being after the newline should be rejected as it was before.
There were two secondary issues in the pasting code that are fixed here: One is that it only sort of collapsed single spaces. So if you had more than one space, spaces still would have ended up in the result. Actually I think the semantics were slightly more insidious, <space><number> would have turned into <number><same number> effectively. The only thing it did was remove the space by duplicating the number. If you had two spaces, then it would have ended up with e.g. <space><number><same number>. The only case where this wouldn't have happened is a space at the end which would have been preserved in the paste.
Secondly, it mutated the clipboard data directly. This would have lead to confusing results where multiple pastes would have had clipboard data in the clipboard itself move from, for example, two spaces to a single space to no spaces at all. The better solution is to preprocess to figure out how big we ultimately want our space-less result to be and stamp out the copy ourselves skipping anything we don't want. Leave the clipboard alone.
If it's desired to preserve single spaces only in the middle, the code will need to be modified a bit.
Co-authored-by: Summate <summate.ssbm@gmail.com>
2024-06-06 14:22:26 +09:30
0761ad4a83
Fix implementation of quad3d for f3dex 0.95 on pj64 video plugin ( #2427 )
...
* Update ucode01.cpp
* Fix quad3d implementation for f3dex 0.95
* Fix compile
2024-06-06 14:20:46 +09:30
91f9cdaaa7
Core: Change the Program counter to be 64bit
2024-06-06 14:09:12 +09:30
77ac4744a5
Core: Make sure fpu stack is being cleared
2024-05-23 11:52:58 +09:30
0ff0d5234c
Core: In R4300iOp::CheckFPUInput64 check values directly instead of using fpclassify
2024-05-23 11:43:19 +09:30
ec714cd90d
Core: in CX86RecompilerOps::CompileCheckFPUResult64 protect RegPointer before Map_TempReg(asmjit::x86::eax)
2024-05-23 11:41:15 +09:30
3baaa829de
Core: Remove g_TLBLoadAddress, g_TLBStoreAddress global variables
2024-05-16 16:34:17 +09:30
ae21e10a8d
Core: Increase the minimal amount of free space in recompiler memory
2024-05-16 16:15:28 +09:30
a1f46356fb
Core: remove usage of g_RecompPos
2024-05-16 16:08:23 +09:30
7f18773b5b
Core: Add CX86RegInfo::GetFPStatusReg
2024-05-16 15:51:04 +09:30
13bd420b2a
Core: Sync FP status register in advanced block linking
2024-05-16 15:45:38 +09:30
703a09d034
Core: Remove protecting memory option
2024-05-09 17:56:28 +09:30
f478f16269
Core: Clear FP Status flag in recompiler on BC1FL and BC1TL
2024-05-09 10:55:38 +09:30
4c23e7af2c
Core: Remove ChangeFPURegFormat, Load_FPR_ToTop
2024-05-02 17:21:01 +09:30
c786bc3251
Core: Force Fpu exception in recompiler
2024-05-02 16:34:13 +09:30
b3e8b760e6
Core: get COP1_S_TRUNC_L, COP1_S_CEIL_L, COP1_S_FLOOR_L, COP1_W_CVT_S, COP1_W_CVT_D, COP1_L_CVT_S, COP1_L_CVT_D to use COP1_S_CVT function
2024-05-02 15:48:43 +09:30
dd0f7ad776
Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword
2024-05-02 15:46:03 +09:30
046f27ce98
Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT
2024-04-25 20:47:02 +09:30
627b4d6103
Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv
2024-04-25 20:41:03 +09:30
b92e6bd752
Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT
2024-04-25 20:22:47 +09:30
d658477cf4
Core: get CX86RecompilerOps::Compile_Branch to clear status flags
2024-04-18 17:31:19 +09:30
b313640831
Core: In CX86RegInfo::Map_TempReg allow it to use FPStatusReg if it is unprotected
2024-04-18 17:28:23 +09:30
1172b6e04d
Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly
2024-04-18 17:21:39 +09:30
38738b783d
Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword
2024-04-18 17:11:45 +09:30
7dc53e51cf
Core: Get CompileCheckFPUInput to better handle 64bit value check
2024-04-18 17:00:29 +09:30
a9875b7d61
Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation
2024-04-18 16:58:18 +09:30
3203322d8b
Core: Get COP1_D_CVT_L to use COP1_S_CVT
2024-04-18 16:56:30 +09:30
9e73771815
Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L
2024-04-18 16:51:53 +09:30
fe87142657
Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation
2024-04-18 16:42:48 +09:30
4071b52810
Core: CX86RegInfo::UnMap_X86reg should fail on a protected register
2024-04-18 16:41:03 +09:30
79f7aa9927
Core: CX86RegInfo::UnMap_FPStatusReg should unprotect register before trying to free it
2024-04-18 16:34:49 +09:30
0cf4c7dc11
Core: get COP1_D_CMP to work in recompiler
2024-04-11 18:14:44 +09:30
9272ac05f6
Core: refactor S opcodes to one central function
2024-04-11 18:09:30 +09:30
e7178dbdec
Core: Fix CX86RecompilerOps::COP1_D_CVT_S
2024-03-28 20:05:27 +10:30
8bb2445263
Core: Have CX86RecompilerOps::CompileCheckFPUResult32 write to the high word
2024-03-28 20:02:24 +10:30
zilmar