zilmar
|
5d64b3d920
|
Core: Better handling of Storing non 32bit values to non memory
|
2024-12-12 16:50:36 +10:30 |
|
zilmar
|
5e1a40fffb
|
Core: fix CX86RecompilerOps::CompileLoadMemoryValue Map_GPR_32bit when called from LWC1
|
2024-11-21 11:10:01 +10:30 |
|
zilmar
|
97b2579b4b
|
Core: Have the recompiler just deal with the Program Counter as 32bit
|
2024-11-07 17:05:16 +10:30 |
|
zilmar
|
dc4fa211b0
|
Core: Clean up RDRAM/RI Registers
|
2024-09-26 12:59:32 +09:30 |
|
zilmar
|
73c9174ce9
|
Core: Remove Memory exception filer
|
2024-06-13 11:50:06 +09:30 |
|
zilmar
|
91f9cdaaa7
|
Core: Change the Program counter to be 64bit
|
2024-06-06 14:09:12 +09:30 |
|
zilmar
|
703a09d034
|
Core: Remove protecting memory option
|
2024-05-09 17:56:28 +09:30 |
|
zilmar
|
25dc3ed36f
|
Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes
|
2024-02-29 15:13:14 +10:30 |
|
zilmar
|
6610ae3058
|
Core: Have R4300iInstruction in CRecompilerOpsBase
|
2023-12-21 10:34:03 +10:30 |
|
zilmar
|
8e3fb3e302
|
Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference
|
2023-12-21 10:26:10 +10:30 |
|
zilmar
|
5fec3f8d31
|
Core: remove the global of g_TLB
|
2023-12-14 12:09:24 +10:30 |
|
zilmar
|
01673dac8d
|
Core: Change TriggerAddressException to SetVPN an R of entry hi in one call
|
2023-11-23 14:20:48 +10:30 |
|
zilmar
|
d47b49d4b5
|
Core: Fix clang issue
|
2023-11-16 18:24:47 +10:30 |
|
zilmar
|
542afc4514
|
Core: remove some accidental added debug code
|
2023-11-16 18:16:35 +10:30 |
|
zilmar
|
ee714e2462
|
Core: On unmap base addresses reset to the correct address
|
2023-11-16 18:14:15 +10:30 |
|
zilmar
|
8f4f434820
|
Core: Get Fast tlb to just be 32bit
|
2023-11-16 17:11:05 +10:30 |
|
zilmar
|
dcb6969067
|
Core: Have entryHI use functions to set/get parts
|
2023-11-16 09:19:24 +10:30 |
|
zilmar
|
a0130ff896
|
Core: Convert %I64U to %llx
|
2023-11-16 09:03:32 +10:30 |
|
zilmar
|
4770d29ec0
|
Core: Get system events to be internal not global
|
2023-10-26 19:59:11 +10:30 |
|
zilmar
|
d6a2ae80c1
|
Core: Remove SystemRegisters
|
2023-10-19 14:56:53 +10:30 |
|
zilmar
|
7f42f70283
|
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
|
2023-10-19 10:28:25 +10:30 |
|
zilmar
|
3a68d3d92a
|
Core: LL/LLD store address
|
2023-10-12 19:55:29 +10:30 |
|
zilmar
|
4e71221147
|
Core: Fix up FPU mode register location
|
2023-10-12 14:53:44 +10:30 |
|
zilmar
|
befa57924d
|
Core: Fix clang compile issues
|
2023-10-05 15:01:09 +10:30 |
|
zilmar
|
f73c3708a5
|
Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
|
2023-10-05 14:45:17 +10:30 |
|
zilmar
|
e74e8f6a23
|
Core: Have load/store ops be able to use 64bit addresses
|
2023-10-05 14:28:32 +10:30 |
|
zilmar
|
9f07fe2aac
|
Core: Get tlb addresses to be 64bit
|
2023-10-05 13:42:31 +10:30 |
|
zilmar
|
4b844495b7
|
Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
|
2023-10-05 13:10:45 +10:30 |
|
zilmar
|
35105e814e
|
Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
|
2023-10-05 09:54:41 +10:30 |
|
zilmar
|
b7311cc611
|
Core: Change Non memory load/store to not use tlb
|
2023-10-05 09:32:45 +10:30 |
|
zilmar
|
bd1ec4ff0f
|
Core: Create a setting for RDRAM Size that plugins can read
|
2023-09-28 07:29:11 +09:30 |
|
zilmar
|
f817becf9c
|
Core: Create a handler for RSP registers that is accessible to the core and the RSP
|
2023-09-28 07:03:01 +09:30 |
|
zilmar
|
6307888be4
|
Core: fix up exception generator functions
|
2023-09-21 18:07:56 +09:30 |
|
zilmar
|
42a944c660
|
RSP: Setup option to run in a thread
|
2023-09-21 14:25:07 +09:30 |
|
zilmar
|
f3d6d3fc7c
|
Core: for tlb miss only use special address when address is not defined
|
2023-09-14 18:39:15 +09:30 |
|
zilmar
|
c02858c7a0
|
Core: Add LLD opcode
|
2023-09-14 16:31:37 +09:30 |
|
zilmar
|
f559aed2ad
|
Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function
|
2023-09-14 16:23:26 +09:30 |
|
zilmar
|
ae4af8746b
|
Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
|
2023-09-14 13:09:11 +09:30 |
|
zilmar
|
8b14b6d7d1
|
Core: Move InitRegisters to register class
|
2023-09-14 12:01:16 +09:30 |
|
zilmar
|
a5a4873e84
|
Core: Have CRegisters::DoAddressError to not directly modify program counter
|
2023-09-14 11:37:21 +09:30 |
|
zilmar
|
5da5dab3c5
|
Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC
|
2023-09-14 11:09:28 +09:30 |
|
zilmar
|
fcd7257adc
|
Core: Change COP0 Status register to a struct breaking up the bits
|
2023-09-14 10:23:36 +09:30 |
|
zilmar
|
41fa1fd5dd
|
Core: use m_TLB_WriteMap not m_TLB_ReadMap for NonMemory
|
2023-08-30 11:35:53 +09:30 |
|
zilmar
|
6884c8d2c9
|
Core: fix up how recompiler handles rounding
|
2023-08-17 15:24:57 +09:30 |
|
zilmar
|
187bd64915
|
Core: Update how exceptions are handled with the recompiler
|
2023-06-08 16:25:05 +09:30 |
|
zilmar
|
b438fddf2e
|
Core: Add CP2 handling
|
2023-05-18 18:04:41 +09:30 |
|
zilmar
|
3b8dfce64a
|
Core: Convert DoBreakException to TriggerException
|
2023-05-18 11:47:00 +09:30 |
|
zilmar
|
b2c2a03a2e
|
Core: convert DoFloatingPointException to TriggerException
|
2023-05-18 11:41:20 +09:30 |
|
zilmar
|
0dfab78c88
|
Core: Convert DoCopUnusableException to TriggerException
|
2023-05-18 11:26:36 +09:30 |
|
zilmar
|
456f25eb6b
|
Core: Get DoIntrException to use TriggerException
|
2023-05-18 11:19:26 +09:30 |