alyosha-tas
|
c27bea3272
|
MSXHawk: Finish trace logger and add some memory domains
|
2020-01-16 20:08:50 -05:00 |
alyosha-tas
|
6637510379
|
MSXHawk: More trace logger and bug fixes
|
2020-01-16 18:53:11 -05:00 |
alyosha-tas
|
ce7d6cdcf5
|
MSXHawk: Tracer Support
|
2020-01-15 20:47:50 -05:00 |
alyosha-tas
|
1e195243be
|
MSXHawk: frameadvance, no video or sound yet
|
2020-01-15 14:25:24 -05:00 |
alyosha-tas
|
5521f0cf19
|
MSXHawk: properly load roms and memory map
|
2020-01-13 22:08:36 -05:00 |
YoshiRulz
|
c38fb09d3c
|
Fix typos in strings and comments (from #971)
|
2020-01-13 00:22:01 +10:00 |
adelikat
|
f83261c116
|
misc cleanups in emulator core service logic
|
2020-01-11 13:19:51 -06:00 |
alyosha-tas
|
46d0818f09
|
MSXHawk: Core interface stuff
|
2020-01-10 15:51:56 -05:00 |
alyosha-tas
|
3e0fd4a2d9
|
MSXHawk: Blank core
|
2020-01-09 17:21:58 -05:00 |
Asnivor
|
91008590cf
|
ZXHawk: Implement more faithful AY port decoding (fixes #1767)
|
2019-12-29 22:23:20 +00:00 |
adelikat
|
85be6af3d3
|
Convert spaces to tabs in ZX Spectrum and AmstradCPC cores
|
2019-12-06 17:47:59 -06:00 |
adelikat
|
fef746dffa
|
properly dispose of IDisposables in core savestate code, and a few other places
|
2019-12-06 17:33:17 -06:00 |
J.D. Purcell
|
fec63fb66a
|
Spaces -> tabs, fix mixed newlines.
|
2019-11-03 20:58:36 -05:00 |
J.D. Purcell
|
c956b5993b
|
Small FFT change I had stashed.
|
2019-10-21 00:10:28 -04:00 |
James Groom
|
90b0574bc3
|
Remove unnecessary calls to ToList (e.g. in foreach)
squashed PR #1591
|
2019-10-13 15:50:57 +00:00 |
SaxxonPike
|
1e5fe55f30
|
C64: Don't reallocate the SID filter buffer every time (purely perf)
|
2019-07-19 19:09:08 -05:00 |
SaxxonPike
|
a119420c79
|
C64: VC count enable seems to need to be delayed by 1 cycle after badline
- which doesn't affect normal operation
- which DOES affect VSP
|
2019-07-14 20:22:07 -05:00 |
SaxxonPike
|
4d6ed8d6c8
|
C64: Savestate should include the new variables
|
2019-07-14 16:32:53 -05:00 |
SaxxonPike
|
8e8d3a6a1b
|
C64: Writes to some registers on the VIC in phase 2 by the CPU should only take effect on the following cycle
|
2019-07-14 10:44:56 -05:00 |
SaxxonPike
|
e8902b829a
|
C64: Apparently the 6502X core needs interrupts delayed by a cycle, do that with IRQ and NMI
|
2019-07-14 10:43:52 -05:00 |
SaxxonPike
|
3bbfb98fc2
|
C64: Split out VIC IRQ delays
|
2019-07-13 19:28:44 -05:00 |
SaxxonPike
|
154eefd2ad
|
C64: Give BA/IRQ counting another go, seems to resolve many issues
|
2019-07-13 16:51:30 -05:00 |
SaxxonPike
|
db38d5e65b
|
C64: Try counting IRQ and BA correctly
|
2019-07-13 15:28:57 -05:00 |
SaxxonPike
|
f22c9b7abd
|
C64: CPU reads open bus when !AEC is asserted
|
2019-07-13 15:25:40 -05:00 |
SaxxonPike
|
894adbb610
|
C64: Remove an unused variable
|
2019-07-13 15:02:18 -05:00 |
SaxxonPike
|
76679bc8bc
|
C64: Use the correct background color in bitmapped modes for 0
|
2019-07-13 15:01:11 -05:00 |
SaxxonPike
|
bd20b355f0
|
C64: Writing to CPU port writes open bus data to 00/01
|
2019-07-13 14:06:23 -05:00 |
SaxxonPike
|
f18e7c8833
|
C64: Make the system debuggable for once
|
2019-07-13 13:15:50 -05:00 |
SaxxonPike
|
cae3340946
|
C64: No need to expose these with the CPU link in place
|
2019-07-13 12:53:34 -05:00 |
SaxxonPike
|
3369dbf43f
|
C64: IRQ is implemented as a delay line; no delay added (yet)
|
2019-07-13 12:51:39 -05:00 |
SaxxonPike
|
d39f3e2e61
|
6502X: pending IRQs are not delayed when !RDY is asserted
|
2019-07-13 12:31:09 -05:00 |
SaxxonPike
|
d62f2ac3fe
|
C64: 0F7 is a badline eligible raster (fixes 26-line text demo in Frodo test suite)
|
2019-07-13 01:41:58 -05:00 |
SaxxonPike
|
e6871b2cc3
|
C64: Move VIC raster IRQ to phase 1
|
2019-07-13 00:27:08 -05:00 |
SaxxonPike
|
dbf6b39e7f
|
C64: Split out VIC phase1/phase2
|
2019-07-12 23:51:55 -05:00 |
SaxxonPike
|
85bc92b688
|
Merge remote-tracking branch 'origin/c64-refactor' into c64-refactor
# Conflicts:
# BizHawk.Emulation.Cores/Computers/Commodore64/MOS/Chip6510.cs
|
2019-07-12 22:10:08 -05:00 |
SaxxonPike
|
0a7dc52aa0
|
C64: BA and raster IRQ cleanup
|
2019-07-09 22:41:12 -05:00 |
SaxxonPike
|
3a135c7c26
|
C64: Raster interrupt bit can be set even if not enabled, just won't actually assert IRQ
|
2019-07-09 21:40:03 -05:00 |
SaxxonPike
|
e63d10b608
|
C64: Interrupts generated in phase 2 by the VIC won't trigger for the CPU until next cycle, also buffer BA
|
2019-07-09 20:55:14 -05:00 |
SaxxonPike
|
b471fdc692
|
C64: The CPU can trigger VIC badlines on its own (needed for VSP)
|
2019-07-09 20:53:54 -05:00 |
SaxxonPike
|
2abe832289
|
C64: AEC does not prohibit the CPU from functioning, only BA (RDY) does
|
2019-07-09 20:52:51 -05:00 |
SaxxonPike
|
a8fd85157c
|
VIC: Use correct color mapping for non-multicolor bitmap mode
|
2019-07-09 08:02:55 -05:00 |
SaxxonPike
|
83b6553749
|
VIC: Respect idle state background color registers, plus black in undocumented gfx mode
|
2019-07-09 06:58:13 -05:00 |
SaxxonPike
|
89fa153477
|
VIC: Resolve background color registers separately to color matrix memory
|
2019-07-09 06:55:55 -05:00 |
SaxxonPike
|
9f733d3e7a
|
VIC: More accurate pixel pipeline
|
2019-07-09 05:26:26 -05:00 |
SaxxonPike
|
d36e02045b
|
C64: Optimize the RNG for 1541 flux transitions. (same output)
|
2019-07-06 16:32:21 -05:00 |
SaxxonPike
|
3bf37f1c17
|
C64: No need for LagCycles anymore.
|
2019-07-06 16:29:14 -05:00 |
SaxxonPike
|
6ed11de85b
|
C64: Soft/Hard reset: it's about time
|
2019-07-06 01:19:58 -05:00 |
SaxxonPike
|
400b04b690
|
C64: CIA was sometimes delaying too long to fire interrupts by 1 cycle.
- This could have implications for existing TASes (!)
|
2019-07-05 23:59:01 -05:00 |
SaxxonPike
|
69f8b143a3
|
C64: Foreground pixels are black when VIC is in idle state.
|
2019-07-05 21:05:38 -05:00 |
SaxxonPike
|
49b613962e
|
C64: Fix a typo disabling voice 3 when high pass filter is set
|
2019-07-04 17:32:35 -05:00 |
SaxxonPike
|
f45e934fec
|
C64: Reset the SID filter on hard reset.
|
2019-07-04 17:24:22 -05:00 |
SaxxonPike
|
579ffe5c25
|
C64: Had the flag with the wrong polarity. Thanks, C64Anabalt.
|
2019-07-04 14:20:12 -05:00 |
SaxxonPike
|
691577499f
|
C64: When a sprite is eligible for display, initialize it with the correct crunch state based on Y expansion
|
2019-07-04 14:12:46 -05:00 |
SaxxonPike
|
36ac592193
|
C64: Individual IRQ flags for S/S or S/D collisions are always set even if not eligible to assert IRQ externally
|
2019-07-04 13:59:41 -05:00 |
SaxxonPike
|
5c9445fb96
|
C64: Reuse some local memory in the sprite renderer.
|
2019-07-04 12:47:09 -05:00 |
SaxxonPike
|
55145ff7ba
|
C64: The T64 format was never supported, but at least make the core aware of it
|
2019-07-04 12:46:28 -05:00 |
SaxxonPike
|
2c804cab34
|
C64: Fix a function ambiguity in the CIA class.
|
2019-07-04 00:51:19 -05:00 |
SaxxonPike
|
2dd80eb0f4
|
C64: Implement more CIA features and CIA/VIA defaults.
|
2019-07-04 00:31:48 -05:00 |
SaxxonPike
|
32d59e8514
|
C64: Implement more VIA features.
|
2019-07-04 00:23:11 -05:00 |
SaxxonPike
|
7fbccb7a46
|
C64: Use write protection on G64 images (which are often copy protected), and disable it on D64 images.
|
2019-07-04 00:14:21 -05:00 |
SaxxonPike
|
4e1892d094
|
C64: Allow writing to disk.
|
2019-07-04 00:11:03 -05:00 |
SaxxonPike
|
0cdb28fc8f
|
C64: Format D64 sector headers with directory ID instead of A0/A0.
|
2019-07-04 00:03:50 -05:00 |
SaxxonPike
|
ceb1338459
|
C64: Use proper sector gaps based on density when converting from D64.
|
2019-07-04 00:02:28 -05:00 |
SaxxonPike
|
e74dfe15a8
|
C64: VIA PB7 output timing adjusted to match datasheet.
|
2019-07-04 00:00:05 -05:00 |
YoshiRulz
|
f6bd34c7ef
|
Realign tables in comments w/ only spaces
*Without* moving them, that point was contentious
|
2019-06-15 13:02:10 +00:00 |
YoshiRulz
|
4dd40305bc
|
Merge branch 'master' into interp_cores
|
2019-06-15 02:11:24 +10:00 |
James Groom
|
067477ce18
|
Merge branch 'master' into clean_docs
|
2019-06-14 13:28:39 +00:00 |
Brian Armstrong
|
2c6ecb68bd
|
Merge branch 'master' into brian/mem_callback_addr_value
|
2019-06-06 02:11:04 -07:00 |
Brian Armstrong
|
d41bd867b8
|
flags
|
2019-06-06 02:04:47 -07:00 |
YoshiRulz
|
2642ef4049
|
Remove empty docs
|
2019-06-06 16:41:10 +10:00 |
YoshiRulz
|
ceb490828f
|
Fix docs "not placed on a valid language element"
|
2019-05-29 21:04:12 +10:00 |
YoshiRulz
|
268ed1a69d
|
Fix malformed docs
|
2019-05-29 20:58:01 +10:00 |
Asnivor
|
47a5ce2798
|
ChannelF: some more changes
|
2019-05-07 14:43:36 +01:00 |
Asnivor
|
b2584145d7
|
SyncSoundMixer: improved and moved out of ZXSpectrum into Cores.Sound (as the CPC will use this and future cores may find it useful)
|
2019-04-04 12:16:16 +01:00 |
YoshiRulz
|
9af93be0d3
|
Use string interpolation
|
2019-04-04 02:41:18 +10:00 |
Asnivor
|
ae7bea226c
|
ZXHawk: move the beeper implementation out of the core into Cores.Sound. The CPC core will also use this and we may have other cores in the future that want to make use of a nice 1-bit buzzer/implementation (tape loading, onboard speaker etc..)
|
2019-04-03 17:01:35 +01:00 |
James Groom
|
59ad94f9b9
|
Merge branch 'master' into appleii_fixattempt
|
2019-03-28 20:25:11 +11:00 |
James Groom
|
4e91f88af3
|
Use nameof in cores
|
2019-03-28 14:18:58 +11:00 |
alyosha-tas
|
6d0973ca7e
|
Merge pull request #1429 from YoshiRulz/master
Inconsequential changes (no whitespace)
looks good to me
|
2019-03-09 17:32:10 -06:00 |
Asnivor
|
76070cd89d
|
OCD: Fix non-critial compiler warnings in my code
|
2019-01-25 15:45:15 +00:00 |
Brian Armstrong
|
a8f293eec8
|
Call mem callbacks with addr, value
|
2019-01-24 03:23:21 -08:00 |
alyosha-tas
|
c19c7cd5c3
|
SubNESHawk
also Input register shift fix
# Conflicts:
# BizHawk.Client.EmuHawk/MainForm.Designer.cs
# BizHawk.Client.EmuHawk/MainForm.Events.cs
# BizHawk.Emulation.Cores/Computers/AmstradCPC/AmstradCPC.IEmulator.cs
# BizHawk.Emulation.Cores/Computers/SinclairSpectrum/ZXSpectrum.IEmulator.cs
# BizHawk.Emulation.Cores/Consoles/Nintendo/NES/PPU.run.cs
|
2019-01-10 18:25:59 +03:00 |
YoshiRulz
|
c0a28a320b
|
Inconsequential changes (no whitespace)
Remove useless semicolon, remove useless `? true : false`, move period to next
line
|
2019-01-07 22:02:02 +10:00 |
Asnivor
|
2b7014f8b8
|
ZXHawk: Some comment and group structure cleanup
|
2019-01-02 14:02:09 +00:00 |
Asnivor
|
3766e2380c
|
ZXHawk: Fix exception thrown randomly by tape player subsystem
|
2019-01-02 12:38:32 +00:00 |
Asnivor
|
6f7a26e803
|
Virtu: enable apple white and black keys
|
2018-12-07 15:03:19 +00:00 |
Asnivor
|
6621827b8f
|
C64Hawk - reenable full border - #1341
|
2018-12-06 13:42:00 +00:00 |
Asnivor
|
0411be40fe
|
ZXHawk: readme update
|
2018-12-06 13:15:24 +00:00 |
Asnivor
|
1ffeb7cf7e
|
ZXHawk: pentagon initialisation
|
2018-12-06 12:58:52 +00:00 |
alyosha-tas
|
bf9796f1e8
|
z80: rewrite interrupt handling
|
2018-09-29 22:04:37 -05:00 |
Asnivor
|
805d3abd9d
|
CPCHawk: more work on new CRTC chip emulation
|
2018-09-27 14:27:11 +01:00 |
Asnivor
|
e0b6c67b70
|
CPCHawk: Menu and GUI fixes
|
2018-09-19 17:46:58 +01:00 |
Asnivor
|
43f401a193
|
CPCHawk: Update readme
|
2018-09-19 17:03:57 +01:00 |
Asnivor
|
2565f49c89
|
Merge branch 'AmstradCPC' into master
|
2018-09-19 14:56:41 +01:00 |
Asnivor
|
95e565c545
|
CPCHawk: Start of new CRCT and Gatearray implementations
|
2018-09-19 14:35:22 +01:00 |
Asnivor
|
f62ab685a9
|
ZXHawk: Fix core GUI windows monospace weirdness
|
2018-09-18 10:50:15 +01:00 |
Asnivor
|
c76e2f35a0
|
ZXHawk: Starting on UDI and IPF disk image support (although neither are fully working or hooked up yet)
|
2018-09-13 10:44:48 +01:00 |
Asnivor
|
faaf4d2f18
|
ZXHawk: Support double-sided *.dsk images and throw an exception if the images are not 42 track disks
|
2018-09-11 11:21:59 +01:00 |
Asnivor
|
bd26f73516
|
Merge branch 'master' of https://github.com/TASVideos/BizHawk.git
|
2018-09-10 10:08:45 +01:00 |
Asnivor
|
16d68ea813
|
ZXHawk: debug only zx-state snapshot export
|
2018-09-10 10:05:49 +01:00 |