zilmar
|
dd0f7ad776
|
Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword
|
2024-05-02 15:46:03 +09:30 |
|
zilmar
|
046f27ce98
|
Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT
|
2024-04-25 20:47:02 +09:30 |
|
zilmar
|
627b4d6103
|
Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv
|
2024-04-25 20:41:03 +09:30 |
|
zilmar
|
b92e6bd752
|
Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT
|
2024-04-25 20:22:47 +09:30 |
|
zilmar
|
d658477cf4
|
Core: get CX86RecompilerOps::Compile_Branch to clear status flags
|
2024-04-18 17:31:19 +09:30 |
|
zilmar
|
b313640831
|
Core: In CX86RegInfo::Map_TempReg allow it to use FPStatusReg if it is unprotected
|
2024-04-18 17:28:23 +09:30 |
|
zilmar
|
1172b6e04d
|
Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly
|
2024-04-18 17:21:39 +09:30 |
|
zilmar
|
38738b783d
|
Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword
|
2024-04-18 17:11:45 +09:30 |
|
zilmar
|
7dc53e51cf
|
Core: Get CompileCheckFPUInput to better handle 64bit value check
|
2024-04-18 17:00:29 +09:30 |
|
zilmar
|
a9875b7d61
|
Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation
|
2024-04-18 16:58:18 +09:30 |
|
zilmar
|
3203322d8b
|
Core: Get COP1_D_CVT_L to use COP1_S_CVT
|
2024-04-18 16:56:30 +09:30 |
|
zilmar
|
9e73771815
|
Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L
|
2024-04-18 16:51:53 +09:30 |
|
zilmar
|
fe87142657
|
Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation
|
2024-04-18 16:42:48 +09:30 |
|
zilmar
|
4071b52810
|
Core: CX86RegInfo::UnMap_X86reg should fail on a protected register
|
2024-04-18 16:41:03 +09:30 |
|
zilmar
|
79f7aa9927
|
Core: CX86RegInfo::UnMap_FPStatusReg should unprotect register before trying to free it
|
2024-04-18 16:34:49 +09:30 |
|
zilmar
|
0cf4c7dc11
|
Core: get COP1_D_CMP to work in recompiler
|
2024-04-11 18:14:44 +09:30 |
|
zilmar
|
9272ac05f6
|
Core: refactor S opcodes to one central function
|
2024-04-11 18:09:30 +09:30 |
|
zilmar
|
e7178dbdec
|
Core: Fix CX86RecompilerOps::COP1_D_CVT_S
|
2024-03-28 20:05:27 +10:30 |
|
zilmar
|
8bb2445263
|
Core: Have CX86RecompilerOps::CompileCheckFPUResult32 write to the high word
|
2024-03-28 20:02:24 +10:30 |
|
François Berder
|
560c49ba2d
|
Core: Fix N64 disk IPL load address check (#2401)
The IPL load address check always evaluated to false due
to a wrong operator.
Signed-off-by: Francois Berder <fberder@outlook.fr>
|
2024-03-21 17:52:09 +10:30 |
|
zilmar
|
45fb2ad965
|
Core: In X86RecompilerOps::CompileCheckFPUResult64 make sure RegPointer is protected
|
2024-03-21 17:44:53 +10:30 |
|
zilmar
|
2811b63ff0
|
Core: Update CX86RecompilerOps::COP1_D_CVT_S and CX86RecompilerOps::COP1_D_CVT_W
|
2024-03-21 17:41:29 +10:30 |
|
zilmar
|
33d2722841
|
Core: fix up CX86RecompilerOps::COP1_D_FLOOR_W
|
2024-03-21 17:40:14 +10:30 |
|
zilmar
|
9a9c2e5439
|
Core: Update CX86RecompilerOps::COP1_D_CEIL_W
|
2024-03-21 17:32:12 +10:30 |
|
zilmar
|
401efae0d9
|
Core: fix up CX86RecompilerOps::COP1_D_ROUND_W
|
2024-03-21 17:28:16 +10:30 |
|
zilmar
|
772a20f07d
|
Core: Update CX86RecompilerOps::COP1_D_SQRT
|
2024-03-21 17:15:10 +10:30 |
|
zilmar
|
87c732b65d
|
Core: update CX86RecompilerOps::COP1_D_NEG
|
2024-03-21 17:14:00 +10:30 |
|
zilmar
|
ece5e30a80
|
Core: create a function to handle .d recompiler opcodes that use fd and fs
|
2024-03-21 17:13:16 +10:30 |
|
zilmar
|
5133d47502
|
Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode
|
2024-03-14 18:12:58 +10:30 |
|
zilmar
|
98b1bddc64
|
Core: Get COP1_D_ADD, COP1_D_SUB, COP1_D_DIV, COP1_D_ABS, COP1_D_SQRT
|
2024-03-07 21:12:57 +10:30 |
|
zilmar
|
97ec1f533b
|
Core: Make sure precision is set to 53bit
|
2024-03-07 20:52:24 +10:30 |
|
zilmar
|
190c408019
|
Core: Fix clang formatting in x86/x86RecompilerOps.cpp
|
2024-02-29 16:06:56 +10:30 |
|
zilmar
|
f7aa6ef6cb
|
Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions
|
2024-02-29 15:16:29 +10:30 |
|
zilmar
|
25dc3ed36f
|
Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes
|
2024-02-29 15:13:14 +10:30 |
|
zilmar
|
d2649f7a13
|
Core: Some clean up recompiler ops
|
2024-02-22 19:56:23 +10:30 |
|
zilmar
|
fae0b81e21
|
Core: Have CX86RegInfo::Map_TempReg generate a BreakPoint if it mapping a protected register
|
2024-02-22 19:41:10 +10:30 |
|
zilmar
|
e082cd55df
|
Core: Get COP1_D_TRUNC_W to work in recompiler
|
2024-02-15 21:08:49 +10:30 |
|
zilmar
|
2559d23592
|
Core: Make sure CX86RecompilerOps::CompileInitFpuOperation clears flag for FE_INVALID
|
2024-02-15 21:02:27 +10:30 |
|
zilmar
|
46f6fae40f
|
Core: get CompileCheckFPUInput to be able to handle 32bit and 64bit
|
2024-02-15 21:00:12 +10:30 |
|
zilmar
|
2014237ed6
|
Core: Update Round.w.s, trunc.w.s, ceil.w.s, floor.w.s to work with exceptions in the recompiler
|
2024-02-08 19:34:14 +10:30 |
|
zilmar
|
ad1a2a2d9a
|
Core: Update neg.s for the recompiler
|
2024-02-01 18:17:03 +10:30 |
|
zilmar
|
b6671adf5d
|
Core: Update abs.s for recompiler
|
2024-02-01 18:15:33 +10:30 |
|
zilmar
|
bc3fe0fe16
|
Core: Handle FP Status Reg being mapped better
|
2024-01-25 18:46:39 +10:30 |
|
zilmar
|
7707f9c7b2
|
Core: Fix up mov.s and mov.d for correct behaviour in the recompiler
|
2024-01-25 16:25:06 +10:30 |
|
zilmar
|
272144dc37
|
Core: check timer on cop1 unusable
|
2024-01-25 16:23:03 +10:30 |
|
zilmar
|
f0f44c67f4
|
Core: Make mov.s the same as mov.d
|
2024-01-25 15:32:56 +10:30 |
|
zilmar
|
7ed94b653e
|
Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions
|
2024-01-18 17:09:27 +10:30 |
|
zilmar
|
2231e8d6c0
|
Core: Remove usage of fpclassify from R4300iOp::CheckFPUResult64
|
2024-01-18 16:53:14 +10:30 |
|
zilmar
|
5c56f9df83
|
RSP: Update the size of the skip in the length for DMA
|
2024-01-11 17:50:23 +10:30 |
|
zilmar
|
4dc3e35bb4
|
Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions
|
2024-01-04 16:51:11 +10:30 |
|
zilmar
|
f8089f565e
|
Core: Unmap FPU_Float with writing to m_FPR_UDW
|
2024-01-04 14:40:42 +10:30 |
|
zilmar
|
552b8f744a
|
Core: update Format_Name to match FPU_STATE
|
2024-01-04 13:11:21 +10:30 |
|
zilmar
|
6ca8333d39
|
Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions
|
2024-01-04 12:39:51 +10:30 |
|
zilmar
|
c9d2bbd221
|
Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped
|
2024-01-04 12:37:06 +10:30 |
|
zilmar
|
0998f0ff0e
|
Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer
|
2024-01-04 12:32:55 +10:30 |
|
zilmar
|
23cff4d7c5
|
Core: Add x86 asm opcode Jnp
|
2024-01-04 12:31:26 +10:30 |
|
zilmar
|
91a8a828d7
|
Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW
|
2024-01-04 12:01:21 +10:30 |
|
zilmar
|
320769d991
|
Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr
|
2024-01-04 10:33:07 +10:30 |
|
zilmar
|
dafa1fb24d
|
Core: Have COP1_W_CVT_S handle the initialization of exceptions
|
2023-12-28 11:19:06 +10:30 |
|
zilmar
|
17288c90c0
|
Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32
|
2023-12-28 10:23:18 +10:30 |
|
zilmar
|
e2306e3541
|
Core: Get COP1_S_CVT_W to handle inexact
|
2023-12-28 09:21:53 +10:30 |
|
zilmar
|
8399fdb893
|
Core: Clear the Divide-by-zero flag
|
2023-12-21 21:24:33 +10:30 |
|
zilmar
|
d14a639a62
|
Core: Implement COP1_S_DIV with fpu exceptions
|
2023-12-21 14:11:29 +10:30 |
|
zilmar
|
8e54ec8c8e
|
Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis
|
2023-12-21 14:10:21 +10:30 |
|
zilmar
|
b263ee10b0
|
Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0
|
2023-12-21 10:41:16 +10:30 |
|
zilmar
|
1810bfda5c
|
Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops
|
2023-12-21 10:38:49 +10:30 |
|
zilmar
|
2c1610cfe2
|
Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode
|
2023-12-21 10:37:27 +10:30 |
|
zilmar
|
6610ae3058
|
Core: Have R4300iInstruction in CRecompilerOpsBase
|
2023-12-21 10:34:03 +10:30 |
|
zilmar
|
8e3fb3e302
|
Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference
|
2023-12-21 10:26:10 +10:30 |
|
zilmar
|
c8e73ba18e
|
Core: Handle unaligned SW exception in the recompiler
|
2023-12-14 23:04:26 +10:30 |
|
zilmar
|
972943cff7
|
Core: Allow LW to R0 be able to generate an exception
|
2023-12-14 17:21:52 +10:30 |
|
zilmar
|
89a6eaf9d1
|
Core: Add RecordLLAddress for 32bit register pointer
|
2023-12-14 13:52:15 +10:30 |
|
zilmar
|
67f5e4f854
|
Core: in LL for recompiler handle storing the address in COP[17]
|
2023-12-14 13:10:20 +10:30 |
|
zilmar
|
5fec3f8d31
|
Core: remove the global of g_TLB
|
2023-12-14 12:09:24 +10:30 |
|
zilmar
|
c67f3f0e97
|
Core: Have UpdateSyncCPU use its Sync cpu instead of passing a cpu to it
|
2023-12-14 11:18:07 +10:30 |
|
zilmar
|
15175d3fe2
|
Core: Fix bug in not creating save state correctly
|
2023-12-07 17:43:48 +10:30 |
|
zilmar
|
de1288bdca
|
Core: remove try/catch around Interpreter cpu
|
2023-11-30 21:15:14 +10:30 |
|
zilmar
|
df56964c96
|
Android: Remove unneeded log call
|
2023-11-30 21:13:27 +10:30 |
|
zilmar
|
5671f2b759
|
Android: Update how Addu cause android studio was not sign extending result
|
2023-11-30 21:12:53 +10:30 |
|
zilmar
|
01673dac8d
|
Core: Change TriggerAddressException to SetVPN an R of entry hi in one call
|
2023-11-23 14:20:48 +10:30 |
|
zilmar
|
d47b49d4b5
|
Core: Fix clang issue
|
2023-11-16 18:24:47 +10:30 |
|
zilmar
|
542afc4514
|
Core: remove some accidental added debug code
|
2023-11-16 18:16:35 +10:30 |
|
zilmar
|
ee714e2462
|
Core: On unmap base addresses reset to the correct address
|
2023-11-16 18:14:15 +10:30 |
|
zilmar
|
8f4f434820
|
Core: Get Fast tlb to just be 32bit
|
2023-11-16 17:11:05 +10:30 |
|
zilmar
|
dcb6969067
|
Core: Have entryHI use functions to set/get parts
|
2023-11-16 09:19:24 +10:30 |
|
zilmar
|
a0130ff896
|
Core: Convert %I64U to %llx
|
2023-11-16 09:03:32 +10:30 |
|
zilmar
|
e6edbc6c82
|
Fix clang formatting
|
2023-10-27 10:14:21 +10:30 |
|
zilmar
|
4770d29ec0
|
Core: Get system events to be internal not global
|
2023-10-26 19:59:11 +10:30 |
|
zilmar
|
8f062975c3
|
Core: improve DisplayControlRegHandler::Write32
|
2023-10-19 19:28:38 +10:30 |
|
zilmar
|
d6a2ae80c1
|
Core: Remove SystemRegisters
|
2023-10-19 14:56:53 +10:30 |
|
zilmar
|
d58168bcb9
|
Core: R4300iOp access the registers directly, not through CSystemRegisters
|
2023-10-19 12:52:33 +10:30 |
|
zilmar
|
4d78f56aa2
|
Core: In R4300iOp have a member variable for system, reg, mmu
|
2023-10-19 12:31:26 +10:30 |
|
zilmar
|
ae0097550f
|
Core: Make R4300iOp opcodes not static
|
2023-10-19 11:43:32 +10:30 |
|
zilmar
|
7f42f70283
|
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
|
2023-10-19 10:28:25 +10:30 |
|
zilmar
|
d3edbf6dda
|
Core: move CInterpreterCPU into R4300iOp
|
2023-10-19 09:32:42 +10:30 |
|
zilmar
|
d4dbc5a3f4
|
Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio
|
2023-10-14 11:53:35 +10:30 |
|
zilmar
|
00c5057b17
|
Core: Make sure precision is correct for COP1_D_SQRT
|
2023-10-13 00:16:14 +10:30 |
|
zilmar
|
3a68d3d92a
|
Core: LL/LLD store address
|
2023-10-12 19:55:29 +10:30 |
|
zilmar
|
a6405cfa2d
|
Core: Add masking around DPC_START_REG/DPC_END_REG
|
2023-10-12 17:50:58 +10:30 |
|
zilmar
|
4e71221147
|
Core: Fix up FPU mode register location
|
2023-10-12 14:53:44 +10:30 |