d6a2ae80c1
Core: Remove SystemRegisters
2023-10-19 14:56:53 +10:30
7f42f70283
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
2023-10-19 10:28:25 +10:30
3a68d3d92a
Core: LL/LLD store address
2023-10-12 19:55:29 +10:30
4e71221147
Core: Fix up FPU mode register location
2023-10-12 14:53:44 +10:30
befa57924d
Core: Fix clang compile issues
2023-10-05 15:01:09 +10:30
f73c3708a5
Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
2023-10-05 14:45:17 +10:30
e74e8f6a23
Core: Have load/store ops be able to use 64bit addresses
2023-10-05 14:28:32 +10:30
9f07fe2aac
Core: Get tlb addresses to be 64bit
2023-10-05 13:42:31 +10:30
4b844495b7
Core: Have save states handle COP0/TLB being 64bit now
...
Core: Clean up tlb class
2023-10-05 13:10:45 +10:30
35105e814e
Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
2023-10-05 09:54:41 +10:30
b7311cc611
Core: Change Non memory load/store to not use tlb
2023-10-05 09:32:45 +10:30
bd1ec4ff0f
Core: Create a setting for RDRAM Size that plugins can read
2023-09-28 07:29:11 +09:30
f817becf9c
Core: Create a handler for RSP registers that is accessible to the core and the RSP
2023-09-28 07:03:01 +09:30
6307888be4
Core: fix up exception generator functions
2023-09-21 18:07:56 +09:30
42a944c660
RSP: Setup option to run in a thread
2023-09-21 14:25:07 +09:30
f3d6d3fc7c
Core: for tlb miss only use special address when address is not defined
2023-09-14 18:39:15 +09:30
c02858c7a0
Core: Add LLD opcode
2023-09-14 16:31:37 +09:30
f559aed2ad
Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function
2023-09-14 16:23:26 +09:30
ae4af8746b
Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
2023-09-14 13:09:11 +09:30
8b14b6d7d1
Core: Move InitRegisters to register class
2023-09-14 12:01:16 +09:30
a5a4873e84
Core: Have CRegisters::DoAddressError to not directly modify program counter
2023-09-14 11:37:21 +09:30
5da5dab3c5
Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC
2023-09-14 11:09:28 +09:30
fcd7257adc
Core: Change COP0 Status register to a struct breaking up the bits
2023-09-14 10:23:36 +09:30
41fa1fd5dd
Core: use m_TLB_WriteMap not m_TLB_ReadMap for NonMemory
2023-08-30 11:35:53 +09:30
6884c8d2c9
Core: fix up how recompiler handles rounding
2023-08-17 15:24:57 +09:30
187bd64915
Core: Update how exceptions are handled with the recompiler
2023-06-08 16:25:05 +09:30
b438fddf2e
Core: Add CP2 handling
2023-05-18 18:04:41 +09:30
3b8dfce64a
Core: Convert DoBreakException to TriggerException
2023-05-18 11:47:00 +09:30
b2c2a03a2e
Core: convert DoFloatingPointException to TriggerException
2023-05-18 11:41:20 +09:30
0dfab78c88
Core: Convert DoCopUnusableException to TriggerException
2023-05-18 11:26:36 +09:30
456f25eb6b
Core: Get DoIntrException to use TriggerException
2023-05-18 11:19:26 +09:30
252f629e14
Core: Convert DoIllegalInstructionException to TriggerException
2023-05-18 11:13:22 +09:30
59a1277bed
Core: Convert GenerateOverflowException to TriggerException
2023-05-18 11:05:27 +09:30
69fd74ba56
Core: Convert DoSysCallException to TriggerException
2023-05-18 10:56:06 +09:30
17df17805d
Core: convert DoTrapException to TriggerException
2023-05-18 10:49:58 +09:30
ce69324dbe
Core: Update R4300iOp::COP1_S_MUL to handle exceptions
2023-03-21 10:49:49 +10:30
96787690c7
Core: Fix CoprocessorUnitNumber on exception
2023-03-20 12:09:06 +10:30
7f7aee7232
Core: remove FAKE_CAUSE_REGISTER
2023-03-14 12:14:10 +10:30
1864adcb35
Core: improve the accuracy of COP1_S_ADD
2023-02-21 14:54:22 +10:30
f802b18cdc
Core: Change to using fenv.h instead of including the code directly
2023-01-30 10:07:51 +10:30
0e52bfb185
Core: Fix the allocation of rdram size if set in the rdb
2023-01-23 08:30:13 +10:30
210ebd42de
Core: have an option for rdram to be different between known and unknown roms
2023-01-16 20:53:48 +10:30
531a7df959
Core: Improve StoreInstruc
2023-01-09 14:26:35 +10:30
80aecdc5e3
Core: Improve R4300iOp::COP1_CT
2023-01-02 19:49:19 +10:30
c0341bb759
Core: Code clean up for clang
2022-12-19 15:35:17 +10:30
6c154f6547
Core: Add Cop2/Cop3 handling exception
2022-12-12 21:29:16 +10:30
d3afe97d38
Core: Initialize FPR_Ctrl[Revision] to 0xA00
2022-12-12 15:27:07 +10:30
d35d2e6abe
Core: Move ReadsGPR, WritesGPR, ReadsHI(), ReadsLO(), WritesHI(), WritesLO() out of OpInfo and into R4300iInstruction
2022-12-05 12:23:09 +10:30
8eecb0c823
Extend mempak Index Table to the intended 256 bytes, so that the default checksum is actually correct, and include the backup of that data. ( #2304 )
...
* just a test to see what happens
* duplicate the full 256 bytes.
* Didn't need to duplicate it after all.
The index table wasn't actually 256 bytes as intended, so the checksum was invalid.
Cruis'n'USA 1.0 didn't like this one bit.
* fully duplicate it after all just in case of a rare case
where a game breaks without the backup of the checksum and table.
* this looks properly duplicated now.
perhaps
2022-11-24 07:49:48 +10:30
989827cb77
Core: Do not set m_MemoryReadMap/m_MemoryWriteMap if tlb mapping is outside rdram
2022-11-14 21:20:28 +10:30
zilmar