zilmar
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5671f2b759
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Android: Update how Addu cause android studio was not sign extending result
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2023-11-30 21:12:53 +10:30 |
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zilmar
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01673dac8d
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Core: Change TriggerAddressException to SetVPN an R of entry hi in one call
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2023-11-23 14:20:48 +10:30 |
|
zilmar
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d47b49d4b5
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Core: Fix clang issue
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2023-11-16 18:24:47 +10:30 |
|
zilmar
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542afc4514
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Core: remove some accidental added debug code
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2023-11-16 18:16:35 +10:30 |
|
zilmar
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ee714e2462
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Core: On unmap base addresses reset to the correct address
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2023-11-16 18:14:15 +10:30 |
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zilmar
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8f4f434820
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Core: Get Fast tlb to just be 32bit
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2023-11-16 17:11:05 +10:30 |
|
zilmar
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dcb6969067
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Core: Have entryHI use functions to set/get parts
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2023-11-16 09:19:24 +10:30 |
|
zilmar
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a0130ff896
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Core: Convert %I64U to %llx
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2023-11-16 09:03:32 +10:30 |
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zilmar
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296b7cf1cf
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Android: Force RSP to be interpret
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2023-11-09 12:45:36 +10:30 |
|
zilmar
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e6edbc6c82
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Fix clang formatting
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2023-10-27 10:14:21 +10:30 |
|
zilmar
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4770d29ec0
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Core: Get system events to be internal not global
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2023-10-26 19:59:11 +10:30 |
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zilmar
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8f062975c3
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Core: improve DisplayControlRegHandler::Write32
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2023-10-19 19:28:38 +10:30 |
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zilmar
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d6a2ae80c1
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Core: Remove SystemRegisters
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2023-10-19 14:56:53 +10:30 |
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zilmar
|
d58168bcb9
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Core: R4300iOp access the registers directly, not through CSystemRegisters
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2023-10-19 12:52:33 +10:30 |
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zilmar
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4d78f56aa2
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Core: In R4300iOp have a member variable for system, reg, mmu
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2023-10-19 12:31:26 +10:30 |
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zilmar
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ae0097550f
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Core: Make R4300iOp opcodes not static
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2023-10-19 11:43:32 +10:30 |
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zilmar
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7f42f70283
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Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
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2023-10-19 10:28:25 +10:30 |
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zilmar
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d3edbf6dda
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Core: move CInterpreterCPU into R4300iOp
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2023-10-19 09:32:42 +10:30 |
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zilmar
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d4dbc5a3f4
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Core: Have R4300iOp::COP1_D_SQRT inline asm version to only compile in Visual Studio
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2023-10-14 11:53:35 +10:30 |
|
zilmar
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00c5057b17
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Core: Make sure precision is correct for COP1_D_SQRT
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2023-10-13 00:16:14 +10:30 |
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zilmar
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3a68d3d92a
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Core: LL/LLD store address
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2023-10-12 19:55:29 +10:30 |
|
zilmar
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a6405cfa2d
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Core: Add masking around DPC_START_REG/DPC_END_REG
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2023-10-12 17:50:58 +10:30 |
|
zilmar
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4e71221147
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Core: Fix up FPU mode register location
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2023-10-12 14:53:44 +10:30 |
|
zilmar
|
befa57924d
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Core: Fix clang compile issues
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2023-10-05 15:01:09 +10:30 |
|
zilmar
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f73c3708a5
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Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
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2023-10-05 14:45:17 +10:30 |
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zilmar
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e74e8f6a23
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Core: Have load/store ops be able to use 64bit addresses
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2023-10-05 14:28:32 +10:30 |
|
zilmar
|
9f07fe2aac
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Core: Get tlb addresses to be 64bit
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2023-10-05 13:42:31 +10:30 |
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zilmar
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4b844495b7
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Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
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2023-10-05 13:10:45 +10:30 |
|
zilmar
|
35105e814e
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Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
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2023-10-05 09:54:41 +10:30 |
|
zilmar
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b7311cc611
|
Core: Change Non memory load/store to not use tlb
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2023-10-05 09:32:45 +10:30 |
|
zilmar
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46e6e54f24
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RSP: improve running RSP multithreaded
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2023-09-28 14:46:36 +09:30 |
|
zilmar
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ac3e0f83d1
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Rsp: Use RSP Register Handler
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2023-09-28 11:52:06 +09:30 |
|
zilmar
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bd1ec4ff0f
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Core: Create a setting for RDRAM Size that plugins can read
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2023-09-28 07:29:11 +09:30 |
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zilmar
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99417fc5d9
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Core: reset run event in CRSP_Plugin after rom close
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2023-09-28 07:19:20 +09:30 |
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zilmar
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f817becf9c
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Core: Create a handler for RSP registers that is accessible to the core and the RSP
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2023-09-28 07:03:01 +09:30 |
|
zilmar
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03e13455f9
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Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot
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2023-09-28 06:39:39 +09:30 |
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zilmar
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2caa457d02
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Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
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2023-09-22 11:01:46 +09:30 |
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zilmar
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10d2b77d7c
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Core: Try to fix android build
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2023-09-21 20:13:41 +09:30 |
|
zilmar
|
aadcca7528
|
Core: Fix clang issue
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2023-09-21 18:40:27 +09:30 |
|
zilmar
|
6307888be4
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Core: fix up exception generator functions
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2023-09-21 18:07:56 +09:30 |
|
zilmar
|
42a944c660
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RSP: Setup option to run in a thread
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2023-09-21 14:25:07 +09:30 |
|
zilmar
|
f3d6d3fc7c
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Core: for tlb miss only use special address when address is not defined
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2023-09-14 18:39:15 +09:30 |
|
zilmar
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e0c125e837
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Core: Fix clang issue
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2023-09-14 16:33:20 +09:30 |
|
zilmar
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c02858c7a0
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Core: Add LLD opcode
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2023-09-14 16:31:37 +09:30 |
|
zilmar
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f559aed2ad
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Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function
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2023-09-14 16:23:26 +09:30 |
|
zilmar
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ae4af8746b
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Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
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2023-09-14 13:09:11 +09:30 |
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zilmar
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8b14b6d7d1
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Core: Move InitRegisters to register class
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2023-09-14 12:01:16 +09:30 |
|
zilmar
|
a5a4873e84
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Core: Have CRegisters::DoAddressError to not directly modify program counter
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2023-09-14 11:37:21 +09:30 |
|
zilmar
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2d09178449
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Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions
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2023-09-14 11:15:42 +09:30 |
|
zilmar
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5da5dab3c5
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Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC
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2023-09-14 11:09:28 +09:30 |
|
zilmar
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fcd7257adc
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Core: Change COP0 Status register to a struct breaking up the bits
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2023-09-14 10:23:36 +09:30 |
|
zilmar
|
9ffd87168a
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Core: DisplayControlRegHandler::Read32 read more of the registers
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2023-09-14 09:40:11 +09:30 |
|
zilmar
|
ab03916a70
|
Core: let the stack pointer equal end of rdram
|
2023-09-07 11:13:54 +09:30 |
|
zilmar
|
7199096748
|
Core: Merge CheckFPUException into CheckFPUResult64
|
2023-08-31 18:52:34 +09:30 |
|
zilmar
|
91d1c6e237
|
Core: Add fpu exceptions to COP1_S_MUL
|
2023-08-31 11:09:48 +09:30 |
|
zilmar
|
2f7a35613f
|
Core: Add exception to COP1_S_SUB
|
2023-08-31 10:54:41 +09:30 |
|
zilmar
|
c28c6bb4a1
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Core: Add fpu exceptions to COP1_S_ADD
|
2023-08-31 10:08:49 +09:30 |
|
zilmar
|
416c85ecda
|
Core: some code clean up of Load_FPR_ToTop
|
2023-08-31 09:30:05 +09:30 |
|
zilmar
|
2dcfcf250d
|
Core: Do not force unmapping of fpr registers before CX86RegInfo::BeforeCallDirect(void)
|
2023-08-31 09:28:23 +09:30 |
|
zilmar
|
e49438cdab
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Core: Add exit reason exception
|
2023-08-30 12:16:07 +09:30 |
|
zilmar
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41fa1fd5dd
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Core: use m_TLB_WriteMap not m_TLB_ReadMap for NonMemory
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2023-08-30 11:35:53 +09:30 |
|
zilmar
|
d300dc002a
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Core: remove exception catch around RSP
|
2023-08-17 15:27:18 +09:30 |
|
zilmar
|
6884c8d2c9
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Core: fix up how recompiler handles rounding
|
2023-08-17 15:24:57 +09:30 |
|
zilmar
|
b5db44c12d
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Core: Get CheckFPUInput64Conv to return true on exception
|
2023-08-03 17:25:03 +09:30 |
|
zilmar
|
5ff45c43c4
|
Core: Get R4300iOp::CheckFPUInput64 to return true on exception
|
2023-08-03 17:11:56 +09:30 |
|
zilmar
|
bc1b027c94
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Core: get CheckFPUInput32Conv to return true on exception
|
2023-08-03 16:24:54 +09:30 |
|
zilmar
|
930e463bbc
|
Core: Move TriggerException(EXC_FPE) into R4300iOp::CheckFPUInput32
|
2023-08-03 15:38:07 +09:30 |
|
zilmar
|
07cf94bde3
|
RSP: only look at SP_STATUS_HALT when seeing if the RSP should run
|
2023-07-06 20:49:14 +09:30 |
|
zilmar
|
187bd64915
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Core: Update how exceptions are handled with the recompiler
|
2023-06-08 16:25:05 +09:30 |
|
zilmar
|
1522f17b9c
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RSP: Convert base code to be compiled as c++ instead of C
|
2023-06-01 17:11:26 +09:30 |
|
zilmar
|
a39ebe7d37
|
Core: Create InitFpuOperation
|
2023-05-27 10:01:19 +09:30 |
|
zilmar
|
e2eebe566d
|
Core: fix up for clang
|
2023-05-18 18:05:54 +09:30 |
|
zilmar
|
b438fddf2e
|
Core: Add CP2 handling
|
2023-05-18 18:04:41 +09:30 |
|
zilmar
|
3b8dfce64a
|
Core: Convert DoBreakException to TriggerException
|
2023-05-18 11:47:00 +09:30 |
|
zilmar
|
b2c2a03a2e
|
Core: convert DoFloatingPointException to TriggerException
|
2023-05-18 11:41:20 +09:30 |
|
zilmar
|
0dfab78c88
|
Core: Convert DoCopUnusableException to TriggerException
|
2023-05-18 11:26:36 +09:30 |
|
zilmar
|
456f25eb6b
|
Core: Get DoIntrException to use TriggerException
|
2023-05-18 11:19:26 +09:30 |
|
zilmar
|
252f629e14
|
Core: Convert DoIllegalInstructionException to TriggerException
|
2023-05-18 11:13:22 +09:30 |
|
zilmar
|
59a1277bed
|
Core: Convert GenerateOverflowException to TriggerException
|
2023-05-18 11:05:27 +09:30 |
|
zilmar
|
69fd74ba56
|
Core: Convert DoSysCallException to TriggerException
|
2023-05-18 10:56:06 +09:30 |
|
zilmar
|
17df17805d
|
Core: convert DoTrapException to TriggerException
|
2023-05-18 10:49:58 +09:30 |
|
zilmar
|
74912ca8c2
|
Core: handle jump to unaligned addresses
|
2023-05-18 10:33:57 +09:30 |
|
zilmar
|
6e58edb076
|
Core: Merge CheckFPUException into CheckFPUResult32
|
2023-05-15 23:16:54 +09:30 |
|
zilmar
|
62b29622ca
|
Core: remove usage of fpclassify in CheckFPUInput32 and CheckFPUResult32
|
2023-05-15 22:57:13 +09:30 |
|
zilmar
|
0ddeb6b981
|
Core: remove exception out of R4300iOp::CheckFPUInput32
|
2023-05-15 20:56:56 +09:30 |
|
zilmar
|
fdc637516f
|
Core: remove Double_RoundToInteger64
|
2023-05-09 13:05:58 +09:30 |
|
zilmar
|
5a23f48629
|
Core: remove Double_RoundToInteger32
|
2023-05-09 12:57:08 +09:30 |
|
zilmar
|
e5b1a9469a
|
Core: remove Float_RoundToInteger64
|
2023-05-09 12:50:23 +09:30 |
|
zilmar
|
2c19c2c362
|
Core: Handle CPO1 unimplemented op
|
2023-05-09 11:28:59 +09:30 |
|
zilmar
|
85f4f147a1
|
Core: Remove Float_RoundToInteger32
|
2023-05-09 09:40:10 +09:30 |
|
zilmar
|
49a385e743
|
Core: Split CheckFPUException into CheckFPUException and CheckFPUInvalidException
|
2023-05-09 08:06:15 +09:30 |
|
zilmar
|
fa25b6d2af
|
Core: clear FPU StatusReg cause in CX86RecompilerOps::COP1_S_ADD
|
2023-05-02 11:12:13 +09:30 |
|
zilmar
|
02a48566c0
|
Core: Remove helper functions from x86 Recompiler Ops
|
2023-05-02 10:50:49 +09:30 |
|
zilmar
|
5cfb80fcfc
|
Core: Improve R4300iOp::COP1_S_CVT_W
|
2023-04-24 19:02:00 +09:30 |
|
zilmar
|
71ef28fd55
|
Core: Add R4300iOp::COP1_W_CVT_W
|
2023-04-24 18:55:06 +09:30 |
|
zilmar
|
ab8b004b71
|
Core: Add a setting for fpu reg caching
|
2023-04-17 18:47:33 +09:30 |
|
zilmar
|
cba01b2063
|
Core: Improve R4300iOp::COP1_L_CVT_D
|
2023-04-17 18:08:51 +09:30 |
|
zilmar
|
d9e69fee65
|
Core: Improve R4300iOp::COP1_D_CMP
|
2023-04-17 18:07:58 +09:30 |
|
zilmar
|
0cc6d21ad1
|
Core: Improve R4300iOp::COP1_S_CMP
|
2023-04-17 18:06:42 +09:30 |
|
zilmar
|
9297b1c4b8
|
Core: Improve COP1_S_CVT_D, COP1_W_CVT_D, COP1_D_CVT_S, COP1_W_CVT_S, COP1_L_CVT_S,
|
2023-04-11 16:20:24 +09:30 |