Core: Add DwordLower for cvt.w
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@ -8140,12 +8140,12 @@ void CX86RecompilerOps::COP1_D_CMP()
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// COP1: W functions
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void CX86RecompilerOps::COP1_W_CVT_S()
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{
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COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_Dword, CRegInfo::FPU_Float);
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COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_DwordLow, CRegInfo::FPU_Float);
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}
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void CX86RecompilerOps::COP1_W_CVT_D()
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{
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COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_Dword, CRegInfo::FPU_Double);
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COP1_S_CVT(CRegInfo::RoundDefault, CRegInfo::FPU_DwordLow, CRegInfo::FPU_Double);
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}
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// COP1: L functions
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@ -11581,7 +11581,7 @@ void CX86RecompilerOps::COP1_S_CVT(CRegBase::FPU_ROUND RoundMethod, CRegInfo::FP
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CompileCheckFPUInput(fsRegPointer, FpuOpSize_64bit, (NewFormat == CRegInfo::FPU_Dword || NewFormat == CRegInfo::FPU_Qword));
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m_Assembler.fpuLoadQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), fsRegPointer);
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}
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else if (OldFormat == CRegInfo::FPU_Dword)
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else if (OldFormat == CRegInfo::FPU_Dword || OldFormat == CRegInfo::FPU_DwordLow)
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{
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m_Assembler.fpuLoadIntegerDwordFromX86Reg(m_RegWorkingSet.StackTopPos(), fsRegPointer);
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}
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@ -350,6 +350,7 @@ asmjit::x86::Gp CX86RegInfo::FPRValuePointer(int32_t Reg, FPU_STATE Format)
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case FPU_UnsignedDoubleWord:
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m_Assembler.MoveVariableToX86reg(TempReg, &g_Reg->m_FPR_UDW[Reg], stdstr_f("m_FPR_UDW[%d]", Reg).c_str());
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break;
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case FPU_DwordLow:
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case FPU_FloatLow:
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m_Assembler.MoveVariableToX86reg(TempReg, &g_Reg->m_FPR_S_L[Reg], stdstr_f("m_FPR_S_L[%d]", Reg).c_str());
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break;
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@ -59,11 +59,12 @@ public:
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FPU_Any = -1,
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FPU_Unknown = 0,
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FPU_Dword = 1,
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FPU_Qword = 2,
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FPU_Float = 3,
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FPU_FloatLow = 4,
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FPU_Double = 5,
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FPU_UnsignedDoubleWord = 6,
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FPU_DwordLow = 2,
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FPU_Qword = 3,
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FPU_Float = 4,
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FPU_FloatLow = 5,
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FPU_Double = 6,
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FPU_UnsignedDoubleWord = 7,
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};
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CX86RegInfo(CCodeBlock & CodeBlock, CX86Ops & Assembler);
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