zilmar
|
7f42f70283
|
Core: Make R4300iOp::ExecuteCPU() and R4300iOp::ExecuteOps(int32_t Cycles) non static
|
2023-10-19 10:28:25 +10:30 |
|
zilmar
|
e74e8f6a23
|
Core: Have load/store ops be able to use 64bit addresses
|
2023-10-05 14:28:32 +10:30 |
|
zilmar
|
9f07fe2aac
|
Core: Get tlb addresses to be 64bit
|
2023-10-05 13:42:31 +10:30 |
|
zilmar
|
35105e814e
|
Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
|
2023-10-05 09:54:41 +10:30 |
|
zilmar
|
b7311cc611
|
Core: Change Non memory load/store to not use tlb
|
2023-10-05 09:32:45 +10:30 |
|
zilmar
|
bd1ec4ff0f
|
Core: Create a setting for RDRAM Size that plugins can read
|
2023-09-28 07:29:11 +09:30 |
|
zilmar
|
f817becf9c
|
Core: Create a handler for RSP registers that is accessible to the core and the RSP
|
2023-09-28 07:03:01 +09:30 |
|
zilmar
|
42a944c660
|
RSP: Setup option to run in a thread
|
2023-09-21 14:25:07 +09:30 |
|
zilmar
|
ae4af8746b
|
Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
|
2023-09-14 13:09:11 +09:30 |
|
zilmar
|
41fa1fd5dd
|
Core: use m_TLB_WriteMap not m_TLB_ReadMap for NonMemory
|
2023-08-30 11:35:53 +09:30 |
|
zilmar
|
0e52bfb185
|
Core: Fix the allocation of rdram size if set in the rdb
|
2023-01-23 08:30:13 +10:30 |
|
zilmar
|
210ebd42de
|
Core: have an option for rdram to be different between known and unknown roms
|
2023-01-16 20:53:48 +10:30 |
|
zilmar
|
531a7df959
|
Core: Improve StoreInstruc
|
2023-01-09 14:26:35 +10:30 |
|
zilmar
|
989827cb77
|
Core: Do not set m_MemoryReadMap/m_MemoryWriteMap if tlb mapping is outside rdram
|
2022-11-14 21:20:28 +10:30 |
|
zilmar
|
48da86bea1
|
Core: if Rom is larger than ISViewerHandler, then use rom handler
|
2022-11-08 10:54:01 +10:30 |
|
zilmar
|
4525e8b6f3
|
Core: Move IMEM/DMEM into SPRegistersHandler
|
2022-10-17 17:29:05 +10:30 |
|
zilmar
|
96244cd6fd
|
Core: Update NonMemory Access to pifram
|
2022-10-17 11:31:54 +10:30 |
|
zilmar
|
9186dcab39
|
Core: Allow reading from ISViewerHandler
|
2022-10-17 08:59:26 +10:30 |
|
zilmar
|
c16307ec0f
|
Core: Move Pifram code into PifRamHandler
|
2022-10-17 08:27:52 +10:30 |
|
zilmar
|
761a1ee52a
|
Code clean up
|
2022-10-10 10:52:17 +10:30 |
|
zilmar
|
0d7f25138c
|
Core: Do not check sign extension in 32bit core
|
2022-10-04 09:47:45 +10:30 |
|
zilmar
|
da138bf38b
|
Project64: Exception when address not sign extended
|
2022-10-03 18:35:50 +10:30 |
|
zilmar
|
a2981ff4d8
|
Core: Make Load/Store use 64bit vaddr
|
2022-09-19 21:36:36 +09:30 |
|
zilmar
|
21b193152a
|
Core: Fix CMipsMemoryVM::MemoryValue64 for sdl/sdr
|
2022-09-19 12:13:19 +09:30 |
|
zilmar
|
a640ecfbc0
|
Core: CMipsMemoryVM::SB_NonMemory should return false just on exception
|
2022-09-05 21:20:07 +09:30 |
|
zilmar
|
0371c20d32
|
Core: Use BreakOnUnhandledMemory in SPRegistersHandler when breaking
|
2022-09-05 11:00:15 +09:30 |
|
zilmar
|
51c9867e76
|
Core: Get the recompiler to be use globals less
|
2022-08-08 20:22:51 +09:30 |
|
zilmar
|
5ea06d958e
|
Core: have SB/SH be able to write to rom handler
|
2022-08-08 19:33:16 +09:30 |
|
zilmar
|
18870634a5
|
Core: Clean up some 64bit warnings
|
2022-08-01 13:15:52 +09:30 |
|
zilmar
|
cffeceef70
|
Core: Handle rom written to better
|
2022-08-01 10:15:56 +09:30 |
|
zilmar
|
7b851e6b6e
|
Core: Break on unhandled memory
|
2022-08-01 10:00:07 +09:30 |
|
zilmar
|
63051df71e
|
Core: Another fix at 64dd
|
2022-07-25 22:00:41 +09:30 |
|
zilmar
|
15466b6a9b
|
Core: Fix unaligned rom access with LH/LB
|
2022-07-25 14:08:09 +09:30 |
|
zilmar
|
acd5f8ecd5
|
Core: Add ISViewerHandler
|
2022-07-18 19:06:34 +09:30 |
|
zilmar
|
7f3b8e3601
|
Core: Start to add R4300iInstruction to do analysis of an opcode
|
2022-07-18 18:01:00 +09:30 |
|
zilmar
|
079e493728
|
Core: Improve PI Dma
|
2022-07-04 17:14:27 +09:30 |
|
zilmar
|
837e93d775
|
Core: Move PI_DMA_READ & PI_DMA_WRITE into PeripheralInterfaceHandler
|
2022-06-20 09:10:01 +09:30 |
|
zilmar
|
86aa483a38
|
Core: Move memory exceptions out of interrupter ops and in to Memory Manager
|
2022-06-13 11:24:36 +09:30 |
|
zilmar
|
dc106c0df8
|
Core: Start to add store instruction self mod
|
2022-06-06 11:41:09 +09:30 |
|
zilmar
|
603ed853bc
|
Core: Some code clean up for load/store non memory
|
2022-05-30 20:20:25 +09:30 |
|
zilmar
|
cc0c139f7e
|
Core: modularize store memory values using CompileStoreMemoryValue
|
2022-05-23 06:24:56 +09:30 |
|
zilmar
|
f95c0f7ef1
|
Core: Fix bug in SDC1
|
2022-05-20 10:32:15 +09:30 |
|
zilmar
|
1617e63b84
|
Core: make memory reads/write to go through new CMipsMemoryVM::MemoryPtr
|
2022-05-16 15:26:20 +09:30 |
|
zilmar
|
1fe8fd1299
|
Core: have MemoryValue32 be able to read from rom
|
2022-05-16 11:00:20 +09:30 |
|
zilmar
|
718d7e0359
|
[Core] Clean up load/store usage in MemoryVirtualMem
|
2022-05-09 10:06:10 +09:30 |
|
zilmar
|
de366db6c1
|
[Core] Clean up some warnings
|
2022-05-03 22:46:12 +09:30 |
|
zilmar
|
5a49331c0b
|
Core: Direct tlb method to read and write to memory
|
2022-05-02 20:22:31 +09:30 |
|
zilmar
|
bac3517c86
|
[Core] Change tlb empty to be -1 and remove rdram from tlb value
|
2022-05-02 19:10:35 +09:30 |
|
zilmar
|
b74a2dc69f
|
[Core] Change TranslateVaddr to VAddrToPAddr
|
2022-05-02 07:36:50 +09:30 |
|
zilmar
|
2f1074a287
|
Core: Add handler for cartridge domains
|
2022-04-25 17:12:07 +09:30 |