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Core: Fix unaligned rom access with LH/LB

This commit is contained in:
zilmar 2022-07-25 14:08:09 +09:30
parent c3cae358a1
commit 15466b6a9b
2 changed files with 44 additions and 4 deletions
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8
Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp
View File

@ -602,11 +602,11 @@ bool CMipsMemoryVM::LB_NonMemory(uint32_t VAddr, uint8_t & Value)
else if (PAddr >= 0x10000000 && PAddr < 0x16000000)
{
uint32_t Value32;
if (!m_RomMemoryHandler.Read32(PAddr & ~0x3, Value32))
if (!m_RomMemoryHandler.Read32((PAddr + 2) & ~0x3, Value32))
{
return false;
}
Value = ((Value32 >> (((PAddr & 3) ^ 3) << 3)) & 0xff);
Value = ((Value32 >> (((PAddr & 1) ^ 3) << 3)) & 0xff);
}
else
{
@ -632,11 +632,11 @@ bool CMipsMemoryVM::LH_NonMemory(uint32_t VAddr, uint16_t & Value)
else if (PAddr >= 0x10000000 && PAddr < 0x16000000)
{
uint32_t Value32;
if (!m_RomMemoryHandler.Read32(PAddr & ~0x3, Value32))
if (!m_RomMemoryHandler.Read32((PAddr + 2) & ~0x3, Value32))
{
return false;
}
Value = ((Value32 >> (((PAddr & 2) ^ 2) << 3)) & 0xffff);
Value = ((Value32 >> 16) & 0xffff);
}
else
{

40
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -9727,6 +9727,46 @@ void CX86RecompilerOps::CompileLoadMemoryValue(CX86Ops::x86Reg AddressReg, CX86O
MoveConstToX86reg((uint32_t)&m_TempValue32, TempReg);
SubX86RegToX86Reg(TempReg, AddressReg);
}
else if (ValueSize == 16)
{
m_RegWorkingSet.BeforeCallDirect();
PushImm32("m_TempValue32", (uint32_t)&m_TempValue32);
Push(AddressReg);
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)(&m_MMU), x86_ECX);
Call_Direct(AddressOf(&CMipsMemoryVM::LH_NonMemory), "CMipsMemoryVM::LH_NonMemory");
#else
PushImm32((uint32_t)(&m_MMU));
Call_Direct(AddressOf(&CMipsMemoryVM::LH_NonMemory), "CMipsMemoryVM::LH_NonMemory");
AddConstToX86Reg(x86_ESP, 12);
#endif
TestX86ByteRegToX86Reg(x86_AL, x86_AL);
m_RegWorkingSet.AfterCallDirect();
CompileExit((uint32_t)-1, (uint32_t)-1, m_RegWorkingSet, CExitInfo::Normal_NoSysCheck, false, JeLabel32);
MoveConstToX86reg((uint32_t)&m_TempValue32, TempReg);
SubX86RegToX86Reg(TempReg, AddressReg);
XorConstToX86Reg(AddressReg, 2);
}
else if (ValueSize == 8)
{
m_RegWorkingSet.BeforeCallDirect();
PushImm32("m_TempValue32", (uint32_t)&m_TempValue32);
Push(AddressReg);
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)(&m_MMU), x86_ECX);
Call_Direct(AddressOf(&CMipsMemoryVM::LB_NonMemory), "CMipsMemoryVM::LB_NonMemory");
#else
PushImm32((uint32_t)(&m_MMU));
Call_Direct(AddressOf(&CMipsMemoryVM::LB_NonMemory), "CMipsMemoryVM::LB_NonMemory");
AddConstToX86Reg(x86_ESP, 12);
#endif
TestX86ByteRegToX86Reg(x86_AL, x86_AL);
m_RegWorkingSet.AfterCallDirect();
CompileExit((uint32_t)-1, (uint32_t)-1, m_RegWorkingSet, CExitInfo::Normal_NoSysCheck, false, JeLabel32);
MoveConstToX86reg((uint32_t)&m_TempValue32, TempReg);
SubX86RegToX86Reg(TempReg, AddressReg);
XorConstToX86Reg(AddressReg, 3);
}
else
{
X86BreakPoint(__FILE__,__LINE__);