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Core: Add handler for cartridge domains

This commit is contained in:
zilmar 2022-04-25 17:12:07 +09:30
parent 1975a993f1
commit 2f1074a287
18 changed files with 349 additions and 252 deletions
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27
Source/Project64-core/N64System/MemoryHandler/CartridgeDomain1Address1Handler.cpp Normal file
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@ -0,0 +1,27 @@
#include "stdafx.h"
#include "CartridgeDomain1Address1Handler.h"
#include <Project64-core\N64System\N64Rom.h>
CartridgeDomain1Address1Handler::CartridgeDomain1Address1Handler(CN64Rom * DDRom) :
m_DDRom(DDRom != nullptr ? DDRom->GetRomAddress() : nullptr),
m_DDRomSize(DDRom != nullptr ? DDRom->GetRomSize() : 0)
{
}
bool CartridgeDomain1Address1Handler::Read32(uint32_t Address, uint32_t & Value)
{
if (m_DDRom != nullptr && (Address & 0xFFFFFF) < m_DDRomSize)
{
Value = *(uint32_t *)&m_DDRom[Address & 0xFFFFFF];
}
else
{
Value = ((Address & 0xFFFF) << 16) | (Address & 0xFFFF);
}
return true;
}
bool CartridgeDomain1Address1Handler::Write32(uint32_t /*Address*/, uint32_t /*Value*/, uint32_t /*Mask*/)
{
return true;
}

22
Source/Project64-core/N64System/MemoryHandler/CartridgeDomain1Address1Handler.h Normal file
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@ -0,0 +1,22 @@
#pragma once
#include "MemoryHandler.h"
class CN64Rom;
class CartridgeDomain1Address1Handler :
public MemoryHandler
{
public:
CartridgeDomain1Address1Handler(CN64Rom * DDRom);
bool Read32(uint32_t Address, uint32_t & Value);
bool Write32(uint32_t Address, uint32_t Value, uint32_t Mask);
private:
CartridgeDomain1Address1Handler();
CartridgeDomain1Address1Handler(const CartridgeDomain1Address1Handler &);
CartridgeDomain1Address1Handler & operator=(const CartridgeDomain1Address1Handler &);
uint32_t m_DDRomSize;
uint8_t * m_DDRom;
};

17
Source/Project64-core/N64System/MemoryHandler/CartridgeDomain1Address3Handler.cpp Normal file
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@ -0,0 +1,17 @@
#include "stdafx.h"
#include "CartridgeDomain1Address3Handler.h"
CartridgeDomain1Address3Handler::CartridgeDomain1Address3Handler()
{
}
bool CartridgeDomain1Address3Handler::Read32(uint32_t Address, uint32_t & Value)
{
Value = ((Address & 0xFFFF) << 16) | (Address & 0xFFFF);
return true;
}
bool CartridgeDomain1Address3Handler::Write32(uint32_t Address, uint32_t Value, uint32_t Mask)
{
return true;
}

16
Source/Project64-core/N64System/MemoryHandler/CartridgeDomain1Address3Handler.h Normal file
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@ -0,0 +1,16 @@
#pragma once
#include "MemoryHandler.h"
class CartridgeDomain1Address3Handler :
public MemoryHandler
{
public:
CartridgeDomain1Address3Handler();
bool Read32(uint32_t Address, uint32_t & Value);
bool Write32(uint32_t Address, uint32_t Value, uint32_t Mask);
private:
CartridgeDomain1Address3Handler(const CartridgeDomain1Address3Handler &);
CartridgeDomain1Address3Handler & operator=(const CartridgeDomain1Address3Handler &);
};

1
Source/Project64-core/N64System/MemoryHandler/CartridgeDomain2Address1Handler.h
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@ -77,6 +77,7 @@ class CartridgeDomain2Address1Handler :
{
public:
CartridgeDomain2Address1Handler(CRegisters & Reg);
bool Read32(uint32_t Address, uint32_t & Value);
bool Write32(uint32_t Address, uint32_t Value, uint32_t Mask);

122
Source/Project64-core/N64System/MemoryHandler/CartridgeDomain2Address2Handler.cpp Normal file
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@ -0,0 +1,122 @@
#include "stdafx.h"
#include "CartridgeDomain2Address2Handler.h"
#include <Project64-core\N64System\N64System.h>
CartridgeDomain2Address2Handler::CartridgeDomain2Address2Handler(CN64System & System, CRegisters & Reg, CMipsMemoryVM & MMU, bool SavesReadOnly) :
m_System(System),
m_Reg(Reg),
m_MMU(MMU),
m_Sram(SavesReadOnly),
m_FlashRam(SavesReadOnly)
{
}
bool CartridgeDomain2Address2Handler::Read32(uint32_t Address, uint32_t & Value)
{
uint32_t offset = (Address & 0x1FFFFFFF) - 0x08000000;
if (offset > 0x88000)
{
Value = ((offset & 0xFFFF) << 16) | (offset & 0xFFFF);
return true;
}
if (m_System.m_SaveUsing == SaveChip_Auto)
{
m_System.m_SaveUsing = SaveChip_FlashRam;
}
if (m_System.m_SaveUsing == SaveChip_Sram)
{
// Load SRAM
uint8_t tmp[4] = "";
m_Sram.DmaFromSram(tmp, offset, 4);
Value = tmp[3] << 24 | tmp[2] << 16 | tmp[1] << 8 | tmp[0];
}
else if (m_System.m_SaveUsing != SaveChip_FlashRam)
{
if (HaveDebugger())
{
g_Notify->BreakPoint(__FILE__, __LINE__);
}
Value = ((Address & 0xFFFF) << 16) | (Address & 0xFFFF);
}
else
{
Value = m_FlashRam.ReadFromFlashStatus(Address & 0x1FFFFFFF);
}
return true;
}
bool CartridgeDomain2Address2Handler::Write32(uint32_t Address, uint32_t Value, uint32_t /*Mask*/)
{
uint32_t offset = (Address & 0x1FFFFFFF) - 0x08000000;
if (m_System.m_SaveUsing == SaveChip_Sram && offset < 0x88000)
{
// Store SRAM
uint8_t tmp[4] = "";
tmp[0] = 0xFF & (Value);
tmp[1] = 0xFF & (Value >> 8);
tmp[2] = 0xFF & (Value >> 16);
tmp[3] = 0xFF & (Value >> 24);
m_Sram.DmaToSram(tmp, (Address & 0x1FFFFFFF) - 0x08000000, 4);
return true;
}
if (offset > 0x10000)
{
return true;
}
if (m_System.m_SaveUsing == SaveChip_Auto)
{
m_System.m_SaveUsing = SaveChip_FlashRam;
}
if (m_System.m_SaveUsing == SaveChip_FlashRam)
{
m_FlashRam.WriteToFlashCommand(Value);
}
return true;
}
bool CartridgeDomain2Address2Handler::DMARead()
{
if (m_System.m_SaveUsing == SaveChip_Auto)
{
m_System.m_SaveUsing = SaveChip_Sram;
}
if (m_System.m_SaveUsing == SaveChip_Sram)
{
m_Sram.DmaToSram(m_MMU.Rdram() + m_Reg.PI_DRAM_ADDR_REG,m_Reg.PI_CART_ADDR_REG - 0x08000000, m_Reg.PI_RD_LEN_REG);
m_Reg.PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
m_Reg.MI_INTR_REG |= MI_INTR_PI;
m_Reg.CheckInterrupts();
return true;
}
else if (m_System.m_SaveUsing == SaveChip_FlashRam)
{
m_FlashRam.DmaToFlashram(m_MMU.Rdram() + m_Reg.PI_DRAM_ADDR_REG, m_Reg.PI_CART_ADDR_REG - 0x08000000, m_Reg.PI_RD_LEN_REG);
m_Reg.PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
m_Reg.MI_INTR_REG |= MI_INTR_PI;
m_Reg.CheckInterrupts();
return true;
}
return false;
}
void CartridgeDomain2Address2Handler::DMAWrite()
{
if (m_System.m_SaveUsing == SaveChip_Auto)
{
m_System.m_SaveUsing = SaveChip_Sram;
}
if (m_System.m_SaveUsing == SaveChip_Sram)
{
m_Sram.DmaFromSram(m_MMU.Rdram() + m_Reg.PI_DRAM_ADDR_REG, m_Reg.PI_CART_ADDR_REG - 0x08000000, m_Reg.PI_WR_LEN_REG);
m_Reg.PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
m_Reg.MI_INTR_REG |= MI_INTR_PI;
m_Reg.CheckInterrupts();
}
else if (m_System.m_SaveUsing == SaveChip_FlashRam)
{
m_FlashRam.DmaFromFlashram(m_MMU.Rdram() + m_Reg.PI_DRAM_ADDR_REG, m_Reg.PI_CART_ADDR_REG - 0x08000000, m_Reg.PI_WR_LEN_REG);
m_Reg.PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
m_Reg.MI_INTR_REG |= MI_INTR_PI;
m_Reg.CheckInterrupts();
}
}

37
Source/Project64-core/N64System/MemoryHandler/CartridgeDomain2Address2Handler.h Normal file
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@ -0,0 +1,37 @@
#pragma once
#include <Project64-core\N64System\SaveType\Sram.h>
#include <Project64-core\N64System\SaveType\FlashRam.h>
#include <Project64-core\Settings\DebugSettings.h>
#include "MemoryHandler.h"
class CN64System;
class CMipsMemoryVM;
class CRegisters;
class CartridgeDomain2Address2Handler :
public MemoryHandler,
private CDebugSettings
{
public:
CartridgeDomain2Address2Handler(CN64System & System, CRegisters & Reg, CMipsMemoryVM & MMU, bool SavesReadOnly);
bool Read32(uint32_t Address, uint32_t & Value);
bool Write32(uint32_t Address, uint32_t Value, uint32_t Mask);
bool DMARead();
void DMAWrite();
CSram & Sram(void) { return m_Sram; }
CFlashRam & FlashRam (void) { return m_FlashRam; }
private:
CartridgeDomain2Address2Handler(void);
CartridgeDomain2Address2Handler(const CartridgeDomain2Address2Handler &);
CartridgeDomain2Address2Handler & operator=(const CartridgeDomain2Address2Handler &);
CN64System & m_System;
CRegisters & m_Reg;
CMipsMemoryVM & m_MMU;
CSram m_Sram;
CFlashRam m_FlashRam;
};

59
Source/Project64-core/N64System/Mips/Dma.cpp
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@ -11,9 +11,8 @@
#include <Project64-core/N64System/N64System.h>
#include <Project64-core/Debugger.h>
CDMA::CDMA(CFlashram & FlashRam, CSram & Sram) :
m_FlashRam(FlashRam),
m_Sram(Sram)
CDMA::CDMA(CartridgeDomain2Address2Handler & Domain2Address2Handler) :
m_Domain2Address2Handler(Domain2Address2Handler)
{
}
@ -148,32 +147,8 @@ void CDMA::PI_DMA_READ()
if (g_Reg->PI_CART_ADDR_REG >= 0x08000000 && g_Reg->PI_CART_ADDR_REG < 0x08088000)
{
if (g_System->m_SaveUsing == SaveChip_Auto)
if (m_Domain2Address2Handler.DMARead())
{
g_System->m_SaveUsing = SaveChip_Sram;
}
if (g_System->m_SaveUsing == SaveChip_Sram)
{
m_Sram.DmaToSram(
g_MMU->Rdram() + g_Reg->PI_DRAM_ADDR_REG,
g_Reg->PI_CART_ADDR_REG - 0x08000000,
PI_RD_LEN_REG
);
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
if (g_System->m_SaveUsing == SaveChip_FlashRam)
{
m_FlashRam.DmaToFlashram(
g_MMU->Rdram() + g_Reg->PI_DRAM_ADDR_REG,
g_Reg->PI_CART_ADDR_REG - 0x08000000,
PI_RD_LEN_REG
);
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
}
@ -318,33 +293,7 @@ void CDMA::PI_DMA_WRITE()
if (PI_CART_ADDR_REG >= 0x08000000 && PI_CART_ADDR_REG <= 0x08088000)
{
if (g_System->m_SaveUsing == SaveChip_Auto)
{
g_System->m_SaveUsing = SaveChip_Sram;
}
if (g_System->m_SaveUsing == SaveChip_Sram)
{
m_Sram.DmaFromSram(
g_MMU->Rdram() + g_Reg->PI_DRAM_ADDR_REG,
PI_CART_ADDR_REG - 0x08000000,
PI_WR_LEN_REG
);
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
if (g_System->m_SaveUsing == SaveChip_FlashRam)
{
m_FlashRam.DmaFromFlashram(
g_MMU->Rdram() + g_Reg->PI_DRAM_ADDR_REG,
PI_CART_ADDR_REG - 0x08000000,
PI_WR_LEN_REG
);
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
}
m_Domain2Address2Handler.DMAWrite();
return;
}

11
Source/Project64-core/N64System/Mips/Dma.h
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@ -1,7 +1,7 @@
#pragma once
#include <Project64-core\Settings\DebugSettings.h>
#include <Project64-core\N64System\SaveType\FlashRam.h>
#include <Project64-core\N64System\SaveType\Sram.h>
class CartridgeDomain2Address2Handler;
class CDMA :
private CDebugSettings
@ -14,14 +14,13 @@ public:
void PI_DMA_WRITE();
protected:
CDMA(CFlashram & FlashRam, CSram & Sram);
CDMA(CartridgeDomain2Address2Handler & Domain2Address2Handler);
private:
CDMA(const CDMA&);
CDMA& operator=(const CDMA&);
CFlashram & m_FlashRam;
CSram & m_Sram;
void OnFirstDMA();
CartridgeDomain2Address2Handler & m_Domain2Address2Handler;
};

162
Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp
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@ -13,8 +13,6 @@
uint8_t * CMipsMemoryVM::m_Reserve1 = nullptr;
uint8_t * CMipsMemoryVM::m_Reserve2 = nullptr;
uint32_t CMipsMemoryVM::m_MemLookupAddress = 0;
MIPS_DWORD CMipsMemoryVM::m_MemLookupValue;
bool CMipsMemoryVM::m_MemLookupValid = true;
uint32_t CMipsMemoryVM::RegModValue;
@ -22,12 +20,12 @@ uint32_t CMipsMemoryVM::RegModValue;
CMipsMemoryVM::CMipsMemoryVM(CN64System & System, bool SavesReadOnly) :
CPifRam(SavesReadOnly),
CFlashram(SavesReadOnly),
CSram(SavesReadOnly),
CDMA(*this, *this),
CDMA(m_CartridgeDomain2Address2Handler),
m_Reg(System.m_Reg),
m_AudioInterfaceHandler(System, System.m_Reg),
m_CartridgeDomain1Address1Handler(g_DDRom),
m_CartridgeDomain2Address1Handler(System.m_Reg),
m_CartridgeDomain2Address2Handler(System, System.m_Reg, *this, SavesReadOnly),
m_RDRAMRegistersHandler(System.m_Reg),
m_DPCommandRegistersHandler(System, System.GetPlugins(), System.m_Reg),
m_MIPSInterfaceHandler(System.m_Reg),
@ -44,10 +42,7 @@ CMipsMemoryVM::CMipsMemoryVM(CN64System & System, bool SavesReadOnly) :
m_TLB_WriteMap(nullptr),
m_RDRAM(nullptr),
m_DMEM(nullptr),
m_IMEM(nullptr),
m_DDRomMapped(false),
m_DDRom(nullptr),
m_DDRomSize(0)
m_IMEM(nullptr)
{
g_Settings->RegisterChangeCB(Game_RDRamSize, this, (CSettings::SettingChangedFunc)RdramChanged);
}
@ -185,15 +180,6 @@ bool CMipsMemoryVM::Initialize(bool SyncSystem)
m_DMEM = (uint8_t *)(m_RDRAM + 0x04000000);
m_IMEM = (uint8_t *)(m_RDRAM + 0x04001000);
// 64DD IPL
if (g_DDRom != nullptr)
{
m_DDRomMapped = false;
m_DDRom = g_DDRom->GetRomAddress();
m_DDRomSize = g_DDRom->GetRomSize();
}
CPifRam::Reset();
m_MemoryReadMap = new size_t [0x100000];
@ -280,16 +266,6 @@ void CMipsMemoryVM::FreeMemory()
CPifRam::Reset();
}
CSram* CMipsMemoryVM::GetSram(void)
{
return dynamic_cast<CSram*>(this);
}
CFlashram* CMipsMemoryVM::GetFlashram()
{
return dynamic_cast<CFlashram*>(this);
}
bool CMipsMemoryVM::LB_VAddr(uint32_t VAddr, uint8_t& Value)
{
uint8_t * MemoryPtr = (uint8_t*)m_MemoryReadMap[VAddr >> 12];
@ -529,34 +505,32 @@ bool CMipsMemoryVM::LH_NonMemory(uint32_t PAddr, uint32_t* Value, bool/* SignExt
bool CMipsMemoryVM::LW_NonMemory(uint32_t PAddr, uint32_t* Value)
{
m_MemLookupAddress = PAddr;
switch (PAddr & 0xFFF00000)
{
case 0x03F00000: m_RDRAMRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x04000000: m_SPRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x04100000: m_DPCommandRegistersHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x04300000: m_MIPSInterfaceHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x04400000: m_VideoInterfaceHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x04500000: m_AudioInterfaceHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x04600000: m_PeripheralInterfaceHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x04700000: m_RDRAMInterfaceHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x04800000: m_SerialInterfaceHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x05000000: m_CartridgeDomain2Address1Handler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x06000000: Load32CartridgeDomain1Address1(); break;
case 0x08000000: Load32CartridgeDomain2Address2(); break;
case 0x1FC00000: m_PifRamHandler.Read32(PAddr, m_MemLookupValue.UW[0]); break;
case 0x1FF00000: Load32CartridgeDomain1Address3(); break;
case 0x03F00000: m_RDRAMRegistersHandler.Read32(PAddr, *Value); break;
case 0x04000000: m_SPRegistersHandler.Read32(PAddr, *Value); break;
case 0x04100000: m_DPCommandRegistersHandler.Read32(PAddr, *Value); break;
case 0x04300000: m_MIPSInterfaceHandler.Read32(PAddr, *Value); break;
case 0x04400000: m_VideoInterfaceHandler.Read32(PAddr, *Value); break;
case 0x04500000: m_AudioInterfaceHandler.Read32(PAddr, *Value); break;
case 0x04600000: m_PeripheralInterfaceHandler.Read32(PAddr, *Value); break;
case 0x04700000: m_RDRAMInterfaceHandler.Read32(PAddr, *Value); break;
case 0x04800000: m_SerialInterfaceHandler.Read32(PAddr, *Value); break;
case 0x05000000: m_CartridgeDomain2Address1Handler.Read32(PAddr, *Value); break;
case 0x06000000: m_CartridgeDomain1Address1Handler.Read32(PAddr, *Value); break;
case 0x08000000: m_CartridgeDomain2Address2Handler.Read32(PAddr, *Value); break;
case 0x1FC00000: m_PifRamHandler.Read32(PAddr, *Value); break;
case 0x1FF00000: m_CartridgeDomain1Address3Handler.Read32(PAddr, *Value); break;
default:
if (PAddr >= 0x10000000 && PAddr < 0x16000000)
{
m_RomMemoryHandler.Read32(PAddr, m_MemLookupValue.UW[0]);
m_RomMemoryHandler.Read32(PAddr, *Value);
}
else
{
m_MemLookupValue.UW[0] = ((PAddr & 0xFFFF) << 16) | PAddr & 0xFFFF;
*Value = ((PAddr & 0xFFFF) << 16) | (PAddr & 0xFFFF);
}
}
*Value = m_MemLookupValue.UW[0];
return true;
}
@ -614,9 +588,6 @@ bool CMipsMemoryVM::SH_NonMemory(uint32_t PAddr, uint16_t Value)
bool CMipsMemoryVM::SW_NonMemory(uint32_t PAddr, uint32_t Value)
{
m_MemLookupValue.UW[0] = Value;
m_MemLookupAddress = PAddr;
switch (PAddr & 0xFFF00000)
{
case 0x00000000:
@ -654,8 +625,10 @@ bool CMipsMemoryVM::SW_NonMemory(uint32_t PAddr, uint32_t Value)
case 0x04700000: m_RDRAMInterfaceHandler.Write32(PAddr, Value, 0xFFFFFFFF); break;
case 0x04800000: m_SerialInterfaceHandler.Write32(PAddr, Value, 0xFFFFFFFF); break;
case 0x05000000: m_CartridgeDomain2Address1Handler.Write32(PAddr, Value, 0xFFFFFFFF); break;
case 0x08000000: Write32CartridgeDomain2Address2(); break;
case 0x06000000: m_CartridgeDomain1Address1Handler.Write32(PAddr, Value, 0xFFFFFFFF); break;
case 0x08000000: m_CartridgeDomain2Address2Handler.Write32(PAddr, Value, 0xFFFFFFFF); break;
case 0x1FC00000: m_PifRamHandler.Write32(PAddr, Value, 0xFFFFFFFF); break;
case 0x1FF00000: m_CartridgeDomain1Address3Handler.Write32(PAddr, Value, 0xFFFFFFFF); break;
default:
if (PAddr >= 0x10000000 && PAddr < 0x16000000)
{
@ -972,93 +945,4 @@ void CMipsMemoryVM::ChangeMiIntrMask()
{
g_Reg->MI_INTR_MASK_REG |= MI_INTR_MASK_DP;
}
}
void CMipsMemoryVM::Load32CartridgeDomain1Address1(void)
{
// 64DD IPL ROM
if (g_DDRom != nullptr && (m_MemLookupAddress & 0xFFFFFF) < g_MMU->m_DDRomSize)
{
m_MemLookupValue.UW[0] = *(uint32_t *)&g_MMU->m_DDRom[(m_MemLookupAddress & 0xFFFFFF)];
}
else
{
m_MemLookupValue.UW[0] = m_MemLookupAddress & 0xFFFF;
m_MemLookupValue.UW[0] = (m_MemLookupValue.UW[0] << 16) | m_MemLookupValue.UW[0];
}
}
void CMipsMemoryVM::Load32CartridgeDomain1Address3(void)
{
m_MemLookupValue.UW[0] = m_MemLookupAddress & 0xFFFF;
m_MemLookupValue.UW[0] = (m_MemLookupValue.UW[0] << 16) | m_MemLookupValue.UW[0];
}
void CMipsMemoryVM::Load32CartridgeDomain2Address2(void)
{
uint32_t offset = (m_MemLookupAddress & 0x1FFFFFFF) - 0x08000000;
if (offset > 0x88000)
{
m_MemLookupValue.UW[0] = ((offset & 0xFFFF) << 16) | (offset & 0xFFFF);
return;
}
if (g_System->m_SaveUsing == SaveChip_Auto)
{
g_System->m_SaveUsing = SaveChip_FlashRam;
}
if (g_System->m_SaveUsing == SaveChip_Sram)
{
// Load SRAM
uint8_t tmp[4] = "";
g_MMU->DmaFromSram(tmp, offset, 4);
m_MemLookupValue.UW[0] = tmp[3] << 24 | tmp[2] << 16 | tmp[1] << 8 | tmp[0];
}
else if (g_System->m_SaveUsing != SaveChip_FlashRam)
{
if (HaveDebugger())
{
g_Notify->BreakPoint(__FILE__, __LINE__);
}
m_MemLookupValue.UW[0] = m_MemLookupAddress & 0xFFFF;
m_MemLookupValue.UW[0] = (m_MemLookupValue.UW[0] << 16) | m_MemLookupValue.UW[0];
}
else
{
m_MemLookupValue.UW[0] = g_MMU->ReadFromFlashStatus(m_MemLookupAddress & 0x1FFFFFFF);
}
}
void CMipsMemoryVM::Write32CartridgeDomain2Address2(void)
{
uint32_t offset = (m_MemLookupAddress & 0x1FFFFFFF) - 0x08000000;
if (g_System->m_SaveUsing == SaveChip_Sram && offset < 0x88000)
{
// Store SRAM
uint8_t tmp[4] = "";
tmp[0] = 0xFF & (m_MemLookupValue.UW[0]);
tmp[1] = 0xFF & (m_MemLookupValue.UW[0] >> 8);
tmp[2] = 0xFF & (m_MemLookupValue.UW[0] >> 16);
tmp[3] = 0xFF & (m_MemLookupValue.UW[0] >> 24);
g_MMU->DmaToSram(tmp, (m_MemLookupAddress & 0x1FFFFFFF) - 0x08000000, 4);
return;
}
/*if ((m_MemLookupAddress & 0x1FFFFFFF) != 0x08010000)
{
if (HaveDebugger())
{
g_Notify->BreakPoint(__FILE__, __LINE__);
}
}*/
if (offset > 0x10000)
{
return;
}
if (g_System->m_SaveUsing == SaveChip_Auto)
{
g_System->m_SaveUsing = SaveChip_FlashRam;
}
if (g_System->m_SaveUsing == SaveChip_FlashRam)
{
g_MMU->WriteToFlashCommand(m_MemLookupValue.UW[0]);
}
}

24
Source/Project64-core/N64System/Mips/MemoryVirtualMem.h
View File

@ -5,10 +5,12 @@
#include <Project64-core\N64System\Interpreter\InterpreterOps.h>
#include <Project64-core\N64System\Mips\PifRam.h>
#include <Project64-core\N64System\SaveType\FlashRam.h>
#include <Project64-core\N64System\SaveType\Sram.h>
#include <Project64-core\N64System\Mips\Dma.h>
#include <Project64-core\N64System\MemoryHandler\AudioInterfaceHandler.h>
#include <Project64-core\N64System\MemoryHandler\CartridgeDomain1Address1Handler.h>
#include <Project64-core\N64System\MemoryHandler\CartridgeDomain1Address3Handler.h>
#include <Project64-core\N64System\MemoryHandler\CartridgeDomain2Address1Handler.h>
#include <Project64-core\N64System\MemoryHandler\CartridgeDomain2Address2Handler.h>
#include <Project64-core\N64System\MemoryHandler\DisplayControlRegHandler.h>
#include <Project64-core\N64System\MemoryHandler\MIPSInterfaceHandler.h>
#include <Project64-core\N64System\MemoryHandler\PeripheralInterfaceHandler.h>
@ -51,8 +53,6 @@ class CMipsMemoryVM :
public CTransVaddr,
private R4300iOp,
public CPifRam,
private CFlashram,
private CSram,
public CDMA,
private CGameSettings
{
@ -72,8 +72,8 @@ public:
uint8_t * Imem() const { return m_IMEM; }
uint8_t * PifRam() { return &m_PifRam[0]; }
CSram * GetSram();
CFlashram * GetFlashram();
CSram & GetSram() { return m_CartridgeDomain2Address2Handler.Sram(); }
CFlashRam & GetFlashRam() { return m_CartridgeDomain2Address2Handler.FlashRam(); }
bool LB_VAddr(uint32_t VAddr, uint8_t & Value);
bool LH_VAddr(uint32_t VAddr, uint16_t & Value);
@ -135,12 +135,6 @@ private:
bool SH_NonMemory(uint32_t PAddr, uint16_t Value);
bool SW_NonMemory(uint32_t PAddr, uint32_t Value);
static void Load32CartridgeDomain1Address1(void);
static void Load32CartridgeDomain1Address3(void);
static void Load32CartridgeDomain2Address2(void);
static void Write32CartridgeDomain2Address2(void);
#if defined(__i386__) || defined(_M_IX86)
typedef struct _X86_CONTEXT
@ -167,7 +161,10 @@ private:
static uint8_t * m_Reserve1, *m_Reserve2;
CRegisters & m_Reg;
AudioInterfaceHandler m_AudioInterfaceHandler;
CartridgeDomain1Address1Handler m_CartridgeDomain1Address1Handler;
CartridgeDomain1Address3Handler m_CartridgeDomain1Address3Handler;
CartridgeDomain2Address1Handler m_CartridgeDomain2Address1Handler;
CartridgeDomain2Address2Handler m_CartridgeDomain2Address2Handler;
DisplayControlRegHandler m_DPCommandRegistersHandler;
MIPSInterfaceHandler m_MIPSInterfaceHandler;
PeripheralInterfaceHandler m_PeripheralInterfaceHandler;
@ -180,9 +177,6 @@ private:
VideoInterfaceHandler m_VideoInterfaceHandler;
uint8_t * m_RDRAM, *m_DMEM, *m_IMEM;
uint32_t m_AllocatedRdramSize;
bool m_DDRomMapped;
uint8_t * m_DDRom;
uint32_t m_DDRomSize;
mutable char m_strLabelName[100];
size_t * m_TLB_ReadMap;
@ -190,8 +184,6 @@ private:
size_t * m_MemoryReadMap;
size_t * m_MemoryWriteMap;
static uint32_t m_MemLookupAddress;
static MIPS_DWORD m_MemLookupValue;
static bool m_MemLookupValid;
static uint32_t RegModValue;
};

6
Source/Project64-core/N64System/N64System.cpp
View File

@ -387,11 +387,17 @@ bool CN64System::LoadFileImage(const char * FileLoc)
}
g_DDRom->LoadN64ImageIPL(FileLoc);
if (g_DDRom->CicChipID() == CIC_NUS_8303)
{
g_Settings->SaveString(File_DiskIPLPath, FileLoc);
}
else if (g_DDRom->CicChipID() == CIC_NUS_DDUS)
{
g_Settings->SaveString(File_DiskIPLUSAPath, FileLoc);
}
else if (g_DDRom->CicChipID() == CIC_NUS_8401)
{
g_Settings->SaveString(File_DiskIPLTOOLPath, FileLoc);
}
}
g_System->RefreshGameSettings();

5
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -11299,9 +11299,10 @@ void CX86RecompilerOps::SW_Register(x86Reg Reg, uint32_t VAddr)
switch (PAddr)
{
case 0x04300000:
MoveX86regToVariable(Reg, &CMipsMemoryVM::m_MemLookupValue.UW[0], "CMipsMemoryVM::m_MemLookupValue.UW[0]");
MoveConstToVariable(PAddr, &CMipsMemoryVM::m_MemLookupAddress, "m_MemLookupAddress");
m_RegWorkingSet.BeforeCallDirect();
PushImm32(0xFFFFFFFF);
Push(Reg);
PushImm32(PAddr & 0x1FFFFFFF);
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)(MemoryHandler*)&g_MMU->m_MIPSInterfaceHandler, x86_ECX);
Call_Direct((void*)((long**)(MemoryHandler*)&g_MMU->m_MIPSInterfaceHandler)[0][1], "MIPSInterfaceHandler::Write32");

24
Source/Project64-core/N64System/SaveType/FlashRam.cpp
View File

@ -4,20 +4,20 @@
#include <Project64-core\N64System\Mips\MemoryVirtualMem.h>
#include <Common\path.h>
CFlashram::CFlashram(bool ReadOnly) :
m_FlashRamPointer(nullptr),
m_FlashFlag(FLASHRAM_MODE_NOPES),
m_FlashStatus(0),
m_FlashRAM_Offset(0),
m_ReadOnly(ReadOnly)
CFlashRam::CFlashRam(bool ReadOnly) :
m_FlashRamPointer(nullptr),
m_FlashFlag(FLASHRAM_MODE_NOPES),
m_FlashStatus(0),
m_FlashRAM_Offset(0),
m_ReadOnly(ReadOnly)
{
}
CFlashram::~CFlashram()
CFlashRam::~CFlashRam()
{
}
void CFlashram::DmaFromFlashram(uint8_t * dest, int32_t StartOffset, int32_t len)
void CFlashRam::DmaFromFlashram(uint8_t * dest, int32_t StartOffset, int32_t len)
{
uint8_t FlipBuffer[0x10000];
@ -78,7 +78,7 @@ void CFlashram::DmaFromFlashram(uint8_t * dest, int32_t StartOffset, int32_t len
}
}
void CFlashram::DmaToFlashram(uint8_t * Source, int32_t StartOffset, int32_t len)
void CFlashRam::DmaToFlashram(uint8_t * Source, int32_t StartOffset, int32_t len)
{
switch (m_FlashFlag)
{
@ -93,7 +93,7 @@ void CFlashram::DmaToFlashram(uint8_t * Source, int32_t StartOffset, int32_t len
}
}
uint32_t CFlashram::ReadFromFlashStatus(uint32_t PAddr)
uint32_t CFlashRam::ReadFromFlashStatus(uint32_t PAddr)
{
switch (PAddr)
{
@ -108,7 +108,7 @@ uint32_t CFlashram::ReadFromFlashStatus(uint32_t PAddr)
return (uint32_t)(m_FlashStatus >> 32);
}
bool CFlashram::LoadFlashram()
bool CFlashRam::LoadFlashram()
{
CPath FileName(g_Settings->LoadStringVal(Directory_NativeSave).c_str(), stdstr_f("%s.fla", g_Settings->LoadStringVal(Game_GameName).c_str()).c_str());
if (g_Settings->LoadBool(Setting_UniqueSaveDir))
@ -134,7 +134,7 @@ bool CFlashram::LoadFlashram()
return true;
}
void CFlashram::WriteToFlashCommand(uint32_t FlashRAM_Command)
void CFlashRam::WriteToFlashCommand(uint32_t FlashRAM_Command)
{
uint8_t EmptyBlock[16 * sizeof(int64_t)];

30
Source/Project64-core/N64System/SaveType/FlashRam.h
View File

@ -1,7 +1,7 @@
#pragma once
#include <Project64-core/Settings/DebugSettings.h>
class CFlashram :
class CFlashRam :
private CDebugSettings
{
enum Modes
@ -14,25 +14,25 @@ class CFlashram :
};
public:
CFlashram(bool ReadOnly);
~CFlashram();
CFlashRam(bool ReadOnly);
~CFlashRam();
void DmaFromFlashram(uint8_t * dest, int32_t StartOffset, int32_t len);
void DmaToFlashram(uint8_t * Source, int32_t StartOffset, int32_t len);
void DmaFromFlashram(uint8_t * dest, int32_t StartOffset, int32_t len);
void DmaToFlashram(uint8_t * Source, int32_t StartOffset, int32_t len);
uint32_t ReadFromFlashStatus(uint32_t PAddr);
void WriteToFlashCommand(uint32_t Value);
void WriteToFlashCommand(uint32_t Value);
private:
CFlashram(void);
CFlashram(const CFlashram&);
CFlashram& operator=(const CFlashram&);
CFlashRam(void);
CFlashRam(const CFlashRam&);
CFlashRam& operator=(const CFlashRam&);
bool LoadFlashram();
bool LoadFlashram();
uint8_t * m_FlashRamPointer;
Modes m_FlashFlag;
uint64_t m_FlashStatus;
uint32_t m_FlashRAM_Offset;
bool m_ReadOnly;
CFile m_File;
Modes m_FlashFlag;
uint64_t m_FlashStatus;
uint32_t m_FlashRAM_Offset;
bool m_ReadOnly;
CFile m_File;
};

6
Source/Project64-core/Project64-core.vcxproj
View File

@ -54,7 +54,10 @@
<ClCompile Include="N64System\Interpreter\InterpreterOps.cpp" />
<ClCompile Include="N64System\Interpreter\InterpreterOps32.cpp" />
<ClCompile Include="N64System\MemoryHandler\AudioInterfaceHandler.cpp" />
<ClCompile Include="N64System\MemoryHandler\CartridgeDomain1Address1Handler.cpp" />
<ClCompile Include="N64System\MemoryHandler\CartridgeDomain1Address3Handler.cpp" />
<ClCompile Include="N64System\MemoryHandler\CartridgeDomain2Address1Handler.cpp" />
<ClCompile Include="N64System\MemoryHandler\CartridgeDomain2Address2Handler.cpp" />
<ClCompile Include="N64System\MemoryHandler\DisplayControlRegHandler.cpp" />
<ClCompile Include="N64System\MemoryHandler\MIPSInterfaceHandler.cpp" />
<ClCompile Include="N64System\MemoryHandler\PeripheralInterfaceHandler.cpp" />
@ -160,7 +163,10 @@
<ClInclude Include="N64System\Interpreter\InterpreterOps32.h" />
<ClInclude Include="N64System\Interpreter\InterpreterOps.h" />
<ClInclude Include="N64System\MemoryHandler\AudioInterfaceHandler.h" />
<ClInclude Include="N64System\MemoryHandler\CartridgeDomain1Address1Handler.h" />
<ClInclude Include="N64System\MemoryHandler\CartridgeDomain1Address3Handler.h" />
<ClInclude Include="N64System\MemoryHandler\CartridgeDomain2Address1Handler.h" />
<ClInclude Include="N64System\MemoryHandler\CartridgeDomain2Address2Handler.h" />
<ClInclude Include="N64System\MemoryHandler\DisplayControlRegHandler.h" />
<ClInclude Include="N64System\MemoryHandler\MemoryHandler.h" />
<ClInclude Include="N64System\MemoryHandler\MIPSInterfaceHandler.h" />

18
Source/Project64-core/Project64-core.vcxproj.filters
View File

@ -396,6 +396,15 @@
<ClCompile Include="N64System\SaveType\Sram.cpp">
<Filter>Source Files\N64 System\SaveType</Filter>
</ClCompile>
<ClCompile Include="N64System\MemoryHandler\CartridgeDomain1Address1Handler.cpp">
<Filter>Source Files\N64 System\MemoryHandler</Filter>
</ClCompile>
<ClCompile Include="N64System\MemoryHandler\CartridgeDomain1Address3Handler.cpp">
<Filter>Source Files\N64 System\MemoryHandler</Filter>
</ClCompile>
<ClCompile Include="N64System\MemoryHandler\CartridgeDomain2Address2Handler.cpp">
<Filter>Source Files\N64 System\MemoryHandler</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="stdafx.h">
@ -761,6 +770,15 @@
<ClInclude Include="N64System\SaveType\Sram.h">
<Filter>Header Files\N64 System\SaveType</Filter>
</ClInclude>
<ClInclude Include="N64System\MemoryHandler\CartridgeDomain1Address1Handler.h">
<Filter>Header Files\N64 System\MemoryHandler</Filter>
</ClInclude>
<ClInclude Include="N64System\MemoryHandler\CartridgeDomain1Address3Handler.h">
<Filter>Header Files\N64 System\MemoryHandler</Filter>
</ClInclude>
<ClInclude Include="N64System\MemoryHandler\CartridgeDomain2Address2Handler.h">
<Filter>Header Files\N64 System\MemoryHandler</Filter>
</ClInclude>
</ItemGroup>
<ItemGroup>
<None Include="Version.h.in">

14
Source/Project64/UserInterface/Debugger/DebugMMU.cpp
View File

@ -188,15 +188,15 @@ bool CDebugMMU::GetPhysicalByte(uint32_t paddr, uint8_t* value)
uint32_t wordpaddr = paddr & ~3;
uint8_t data[4];
CSram *sram = g_MMU->GetSram();
sram->DmaFromSram(data, wordpaddr - 0x08000000, 4);
CSram & sram = g_MMU->GetSram();
sram.DmaFromSram(data, wordpaddr - 0x08000000, 4);
*value = data[nByte ^ 3];
return true;
}
else if (g_System->m_SaveUsing == SaveChip_FlashRam && saveOffset <= 3) // FlashRAM status
{
CFlashram* flashRam = g_MMU->GetFlashram();
uint32_t flashStatus = flashRam->ReadFromFlashStatus(0x08000000);
CFlashRam & FlashRam = g_MMU->GetFlashRam();
uint32_t flashStatus = FlashRam.ReadFromFlashStatus(0x08000000);
*value = (flashStatus >> (24 - nByte * 8)) & 0xFF;
return true;
}
@ -262,10 +262,10 @@ bool CDebugMMU::SetPhysicalByte(uint32_t paddr, uint8_t value)
uint32_t wordpaddr = paddr & ~3;
uint8_t data[4];
CSram *sram = g_MMU->GetSram();
sram->DmaFromSram(data, wordpaddr - 0x08000000, sizeof(data));
CSram & sram = g_MMU->GetSram();
sram.DmaFromSram(data, wordpaddr - 0x08000000, sizeof(data));
data[nByte ^ 3] = value;
sram->DmaToSram(data, wordpaddr - 0x08000000, sizeof(data));
sram.DmaToSram(data, wordpaddr - 0x08000000, sizeof(data));
return true;
}
}