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Core: Move PI_DMA_READ & PI_DMA_WRITE into PeripheralInterfaceHandler

This commit is contained in:
zilmar 2022-06-20 09:10:01 +09:30
parent cec55c7fd9
commit 837e93d775
9 changed files with 452 additions and 525 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

426
Source/Project64-core/N64System/MemoryHandler/PeripheralInterfaceHandler.cpp
View File

@ -3,7 +3,12 @@
#include <Project64-core\N64System\Mips\MemoryVirtualMem.h>
#include <Project64-core\N64System\Mips\Register.h>
#include <Project64-core\N64System\Mips\Disk.h>
#include <Project64-core\N64System\N64System.h>
#include <Project64-core\N64System\N64Rom.h>
#include <Project64-core\N64System\N64Disk.h>
#include <Project64-core\Debugger.h>
#include "PeripheralInterfaceHandler.h"
#include <Common\MemoryManagement.h>
PeripheralInterfaceReg::PeripheralInterfaceReg(uint32_t * PeripheralInterface) :
PI_DRAM_ADDR_REG(PeripheralInterface[0]),
@ -24,8 +29,9 @@ PeripheralInterfaceReg::PeripheralInterfaceReg(uint32_t * PeripheralInterface) :
{
}
PeripheralInterfaceHandler::PeripheralInterfaceHandler(CMipsMemoryVM & MMU, CRegisters & Reg) :
PeripheralInterfaceHandler::PeripheralInterfaceHandler(CMipsMemoryVM & MMU, CRegisters & Reg, CartridgeDomain2Address2Handler & Domain2Address2Handler) :
PeripheralInterfaceReg(Reg.m_Peripheral_Interface),
m_Domain2Address2Handler(Domain2Address2Handler),
m_MMU(MMU),
m_Reg(Reg),
m_PC(Reg.m_PROGRAM_COUNTER)
@ -123,11 +129,11 @@ bool PeripheralInterfaceHandler::Write32(uint32_t Address, uint32_t Value, uint3
break;
case 0x04600008:
PI_RD_LEN_REG = (PI_RD_LEN_REG & ~Mask) | (Value & Mask);
m_MMU.PI_DMA_READ();
PI_DMA_READ();
break;
case 0x0460000C:
PI_WR_LEN_REG = (PI_WR_LEN_REG & ~Mask) | (Value & Mask);
m_MMU.PI_DMA_WRITE();
PI_DMA_WRITE();
break;
case 0x04600010:
//if ((Value & PI_SET_RESET) != 0 )
@ -156,3 +162,417 @@ bool PeripheralInterfaceHandler::Write32(uint32_t Address, uint32_t Value, uint3
}
return true;
}
void PeripheralInterfaceHandler::OnFirstDMA()
{
int16_t offset;
const uint32_t rt = g_MMU->RdramSize();
switch (g_Rom->CicChipID())
{
case CIC_NUS_6101:
case CIC_NUS_5167:
case CIC_NUS_8303:
case CIC_NUS_DDUS:
case CIC_NUS_8401:
case CIC_UNKNOWN:
case CIC_NUS_6102:
case CIC_NUS_6103:
case CIC_NUS_6106:
case CIC_NUS_5101:
offset = 0x0318;
break;
case CIC_NUS_6105:
offset = 0x03F0;
break;
default:
g_Notify->DisplayError(stdstr_f("Unhandled CicChip(%d) in first DMA", g_Rom->CicChipID()).c_str());
return;
}
g_MMU->UpdateMemoryValue32(0x80000000 + offset, rt);
}
void PeripheralInterfaceHandler::PI_DMA_READ()
{
if (g_Debugger != NULL && HaveDebugger())
{
g_Debugger->PIDMAReadStarted();
}
// PI_STATUS_REG |= PI_STATUS_DMA_BUSY;
uint32_t PI_RD_LEN = ((g_Reg->PI_RD_LEN_REG) & 0x00FFFFFFul) + 1;
if ((PI_RD_LEN & 1) != 0)
{
PI_RD_LEN += 1;
}
if (g_Reg->PI_DRAM_ADDR_REG + PI_RD_LEN > g_MMU->RdramSize())
{
if (HaveDebugger())
{
g_Notify->DisplayError(stdstr_f("PI_DMA_READ not in Memory: %08X", g_Reg->PI_DRAM_ADDR_REG + PI_RD_LEN).c_str());
}
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
// 64DD buffers write
if (g_Reg->PI_CART_ADDR_REG >= 0x05000000 && g_Reg->PI_CART_ADDR_REG <= 0x050003FF)
{
// 64DD C2 sectors (don't care)
g_SystemTimer->SetTimer(g_SystemTimer->DDPiTimer, (PI_RD_LEN * 63) / 25, false);
return;
}
if (g_Reg->PI_CART_ADDR_REG >= 0x05000400 && g_Reg->PI_CART_ADDR_REG <= 0x050004FF)
{
// 64DD user sector
uint32_t i;
uint8_t * RDRAM = g_MMU->Rdram();
uint8_t * DISK = g_Disk->GetDiskAddressBuffer();
for (i = 0; i < PI_RD_LEN_REG; i++)
{
*(DISK + (i ^ 3)) = *(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3));
}
g_SystemTimer->SetTimer(g_SystemTimer->DDPiTimer, (PI_RD_LEN_REG * 63) / 25, false);
return;
}
if (g_Reg->PI_CART_ADDR_REG >= 0x05000580 && g_Reg->PI_CART_ADDR_REG <= 0x050005BF)
{
// 64DD MSEQ (don't care)
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
// Write ROM area (for 64DD conversion)
if (g_Reg->PI_CART_ADDR_REG >= 0x10000000 && g_Reg->PI_CART_ADDR_REG <= 0x1FBFFFFF && g_Settings->LoadBool(Game_AllowROMWrites))
{
uint32_t i;
uint8_t * ROM = g_Rom->GetRomAddress();
uint8_t * RDRAM = g_MMU->Rdram();
ProtectMemory(ROM, g_Rom->GetRomSize(), MEM_READWRITE);
g_Reg->PI_CART_ADDR_REG -= 0x10000000;
if (g_Reg->PI_CART_ADDR_REG + PI_RD_LEN_REG < g_Rom->GetRomSize())
{
for (i = 0; i < PI_RD_LEN_REG; i++)
{
*(ROM + ((g_Reg->PI_CART_ADDR_REG + i) ^ 3)) = *(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3));
}
}
else
{
uint32_t Len;
Len = g_Rom->GetRomSize() - g_Reg->PI_CART_ADDR_REG;
for (i = 0; i < Len; i++)
{
*(ROM + ((g_Reg->PI_CART_ADDR_REG + i) ^ 3)) = *(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3));
}
}
g_Reg->PI_CART_ADDR_REG += 0x10000000;
if (!g_System->DmaUsed())
{
g_System->SetDmaUsed(true);
OnFirstDMA();
}
if (g_Recompiler && g_System->bSMM_PIDMA())
{
g_Recompiler->ClearRecompCode_Phys(g_Reg->PI_DRAM_ADDR_REG, g_Reg->PI_WR_LEN_REG, CRecompiler::Remove_DMA);
}
ProtectMemory(ROM, g_Rom->GetRomSize(), MEM_READONLY);
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
if (g_Reg->PI_CART_ADDR_REG >= 0x08000000 && g_Reg->PI_CART_ADDR_REG < 0x08088000)
{
if (m_Domain2Address2Handler.DMARead())
{
return;
}
}
if (g_System->m_SaveUsing == SaveChip_FlashRam)
{
g_Notify->DisplayError(stdstr_f("**** FlashRAM DMA read address %08X ****", g_Reg->PI_CART_ADDR_REG).c_str());
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
if (HaveDebugger())
{
g_Notify->DisplayError(stdstr_f("PI_DMA_READ where are you DMAing to? : %08X", g_Reg->PI_CART_ADDR_REG).c_str());
}
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
void PeripheralInterfaceHandler::PI_DMA_WRITE()
{
if (g_Debugger != NULL && HaveDebugger())
{
g_Debugger->PIDMAWriteStarted();
}
// Rounding PI_WR_LEN up to the nearest even number fixes AI Shougi 3, Doraemon 3, etc.
uint32_t PI_WR_LEN = ((g_Reg->PI_WR_LEN_REG) & 0x00FFFFFEul) + 2;
uint32_t PI_CART_ADDR = !g_Settings->LoadBool(Game_UnalignedDMA) ? g_Reg->PI_CART_ADDR_REG & ~1 : g_Reg->PI_CART_ADDR_REG;
g_Reg->PI_STATUS_REG |= PI_STATUS_DMA_BUSY;
if (g_Reg->PI_DRAM_ADDR_REG + PI_WR_LEN > g_MMU->RdramSize())
{
if (ShowUnhandledMemory()) { g_Notify->DisplayError(stdstr_f("PI_DMA_WRITE not in memory: %08X", g_Reg->PI_DRAM_ADDR_REG + PI_WR_LEN).c_str()); }
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
// 64DD buffers read
if (PI_CART_ADDR >= 0x05000000 && PI_CART_ADDR <= 0x050003FF)
{
// 64DD C2 sectors (just read 0)
uint32_t i;
uint8_t * RDRAM = g_MMU->Rdram();
for (i = 0; i < PI_WR_LEN; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = 0;
}
// Timer is needed for track read
g_SystemTimer->SetTimer(g_SystemTimer->DDPiTimer, (PI_WR_LEN * 63) / 25, false);
return;
}
if (PI_CART_ADDR >= 0x05000400 && PI_CART_ADDR <= 0x050004FF)
{
// 64DD user sector
uint32_t i;
uint8_t * RDRAM = g_MMU->Rdram();
uint8_t * DISK = g_Disk->GetDiskAddressBuffer();
for (i = 0; i < PI_WR_LEN; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(DISK + (i ^ 3));
}
// Timer is needed for track read
g_SystemTimer->SetTimer(g_SystemTimer->DDPiTimer, (PI_WR_LEN * 63) / 25, false);
return;
}
if (PI_CART_ADDR >= 0x05000580 && PI_CART_ADDR <= 0x050005BF)
{
// 64DD MSEQ (don't care)
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
// 64DD IPL ROM
if (PI_CART_ADDR >= 0x06000000 && PI_CART_ADDR <= 0x063FFFFF)
{
uint32_t i;
uint8_t * ROM = g_DDRom->GetRomAddress();
uint8_t * RDRAM = g_MMU->Rdram();
PI_CART_ADDR -= 0x06000000;
if (PI_CART_ADDR + PI_WR_LEN < g_DDRom->GetRomSize())
{
for (i = 0; i < PI_WR_LEN; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((PI_CART_ADDR + i) ^ 3));
}
}
else if (PI_CART_ADDR >= g_DDRom->GetRomSize())
{
uint32_t cart = PI_CART_ADDR - g_DDRom->GetRomSize();
while (cart >= g_DDRom->GetRomSize())
{
cart -= g_DDRom->GetRomSize();
}
for (i = 0; i < PI_WR_LEN; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((cart + i) ^ 3));
}
}
else
{
uint32_t Len;
Len = g_DDRom->GetRomSize() - PI_CART_ADDR;
for (i = 0; i < Len; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((PI_CART_ADDR + i) ^ 3));
}
for (i = Len; i < PI_WR_LEN - Len; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = 0;
}
}
PI_CART_ADDR += 0x06000000;
if (!g_System->DmaUsed())
{
g_System->SetDmaUsed(true);
OnFirstDMA();
}
if (g_Recompiler && g_System->bSMM_PIDMA())
{
g_Recompiler->ClearRecompCode_Phys(g_Reg->PI_DRAM_ADDR_REG, g_Reg->PI_WR_LEN_REG, CRecompiler::Remove_DMA);
}
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
//ChangeTimer(PiTimer,(int32_t)(PI_WR_LEN * 8.9) + 50);
//ChangeTimer(PiTimer,(int32_t)(PI_WR_LEN * 8.9));
return;
}
if (PI_CART_ADDR >= 0x08000000 && PI_CART_ADDR <= 0x08088000)
{
m_Domain2Address2Handler.DMAWrite();
return;
}
if (PI_CART_ADDR >= 0x10000000 && PI_CART_ADDR <= 0x1FFFFFFF)
{
if (g_Recompiler && g_System->bSMM_PIDMA())
{
g_Recompiler->ClearRecompCode_Phys(g_Reg->PI_DRAM_ADDR_REG, g_Reg->PI_WR_LEN_REG, CRecompiler::Remove_DMA);
}
uint32_t i;
uint8_t * ROM = g_Rom->GetRomAddress();
uint8_t * RDRAM = g_MMU->Rdram();
PI_CART_ADDR -= 0x10000000;
if (PI_CART_ADDR + PI_WR_LEN < g_Rom->GetRomSize())
{
size_t alignment;
RDRAM += g_Reg->PI_DRAM_ADDR_REG;
ROM += PI_CART_ADDR;
alignment = PI_WR_LEN | (size_t)RDRAM | (size_t)ROM;
if ((alignment & 0x3) == 0)
{
for (i = 0; i < PI_WR_LEN; i += 4)
{
*(uint32_t *)(RDRAM + i) = *(uint32_t *)(ROM + i);
}
}
else if ((alignment & 1) == 0)
{
if ((PI_WR_LEN & 2) == 0)
{
if (((size_t)RDRAM & 2) == 0)
{
for (i = 0; i < PI_WR_LEN; i += 4)
{
*(uint16_t *)(((size_t)RDRAM + i) + 2) = *(uint16_t *)(((size_t)ROM + i) - 2);
*(uint16_t *)(((size_t)RDRAM + i) + 0) = *(uint16_t *)(((size_t)ROM + i) + 4);
}
}
else
{
if (((size_t)ROM & 2) == 0)
{
for (i = 0; i < PI_WR_LEN; i += 4)
{
*(uint16_t *)(((size_t)RDRAM + i) - 2) = *(uint16_t *)(((size_t)ROM + i) + 2);
*(uint16_t *)(((size_t)RDRAM + i) + 4) = *(uint16_t *)(((size_t)ROM + i) + 0);
}
}
else
{
for (i = 0; i < PI_WR_LEN; i += 4)
{
*(uint16_t *)(((size_t)RDRAM + i) - 2) = *(uint16_t *)(((size_t)ROM + i) - 2);
*(uint16_t *)(((size_t)RDRAM + i) + 4) = *(uint16_t *)(((size_t)ROM + i) + 4);
}
}
}
}
else
{
for (i = 0; i < PI_WR_LEN; i += 2)
{
*(uint16_t *)(((size_t)RDRAM + i) ^ 2) = *(uint16_t *)(((size_t)ROM + i) ^ 2);
}
}
}
else
{
for (i = 0; i < PI_WR_LEN; i++)
{
*(uint8_t *)(((size_t)RDRAM + i) ^ 3) = *(uint8_t *)(((size_t)ROM + i) ^ 3);
}
}
}
else if (PI_CART_ADDR >= g_Rom->GetRomSize())
{
uint32_t cart = PI_CART_ADDR - g_Rom->GetRomSize();
while (cart >= g_Rom->GetRomSize())
{
cart -= g_Rom->GetRomSize();
}
for (i = 0; i < PI_WR_LEN; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((cart + i) ^ 3));
}
}
else
{
uint32_t Len;
Len = g_Rom->GetRomSize() - PI_CART_ADDR;
for (i = 0; i < Len; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((PI_CART_ADDR + i) ^ 3));
}
for (i = Len; i < PI_WR_LEN - Len; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = 0;
}
}
PI_CART_ADDR += 0x10000000;
if (!g_System->DmaUsed())
{
g_System->SetDmaUsed(true);
OnFirstDMA();
}
if (g_System->bRandomizeSIPIInterrupts())
{
g_SystemTimer->SetTimer(g_SystemTimer->PiTimer, PI_WR_LEN / 8 + (g_Random->next() % 0x40), false);
}
else
{
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
}
//ChangeTimer(PiTimer,(int32_t)(PI_WR_LEN * 8.9) + 50);
//ChangeTimer(PiTimer,(int32_t)(PI_WR_LEN * 8.9));
return;
}
if (ShowUnhandledMemory())
{
g_Notify->DisplayError(stdstr_f("PI_DMA_WRITE not in ROM: %08X", PI_CART_ADDR).c_str());
}
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
}

9
Source/Project64-core/N64System/MemoryHandler/PeripheralInterfaceHandler.h
View File

@ -35,6 +35,7 @@ private:
class CRegisters;
class CMipsMemoryVM;
class CartridgeDomain2Address2Handler;
class PeripheralInterfaceHandler :
public MemoryHandler,
@ -44,7 +45,7 @@ class PeripheralInterfaceHandler :
private PeripheralInterfaceReg
{
public:
PeripheralInterfaceHandler(CMipsMemoryVM & MMU, CRegisters & Reg);
PeripheralInterfaceHandler(CMipsMemoryVM & MMU, CRegisters & Reg, CartridgeDomain2Address2Handler & Domain2Address2Handler);
bool Read32(uint32_t Address, uint32_t & Value);
bool Write32(uint32_t Address, uint32_t Value, uint32_t Mask);
@ -54,6 +55,12 @@ private:
PeripheralInterfaceHandler(const PeripheralInterfaceHandler &);
PeripheralInterfaceHandler & operator=(const PeripheralInterfaceHandler &);
void PI_DMA_READ();
void PI_DMA_WRITE();
void OnFirstDMA();
CartridgeDomain2Address2Handler & m_Domain2Address2Handler;
CMipsMemoryVM & m_MMU;
CRegisters & m_Reg;
uint32_t & m_PC;

431
Source/Project64-core/N64System/Mips/Dma.cpp
View File

@ -1,431 +0,0 @@
#include "stdafx.h"
#include <Common/MemoryManagement.h>
#include <Project64-core/N64System/Mips/Dma.h>
#include <Project64-core/N64System/SystemGlobals.h>
#include <Project64-core/N64System/N64Rom.h>
#include <Project64-core/N64System/Mips/MemoryVirtualMem.h>
#include <Project64-core/N64System/Mips/Register.h>
#include <Project64-core/N64System/Mips/Disk.h>
#include <Project64-core/N64System/N64Disk.h>
#include <Project64-core/N64System/N64System.h>
#include <Project64-core/Debugger.h>
CDMA::CDMA(CartridgeDomain2Address2Handler & Domain2Address2Handler) :
m_Domain2Address2Handler(Domain2Address2Handler)
{
}
void CDMA::OnFirstDMA()
{
int16_t offset;
const uint32_t rt = g_MMU->RdramSize();
switch (g_Rom->CicChipID())
{
case CIC_NUS_6101:
case CIC_NUS_5167:
case CIC_NUS_8303:
case CIC_NUS_DDUS:
case CIC_NUS_8401:
case CIC_UNKNOWN:
case CIC_NUS_6102:
case CIC_NUS_6103:
case CIC_NUS_6106:
case CIC_NUS_5101:
offset = 0x0318;
break;
case CIC_NUS_6105:
offset = 0x03F0;
break;
default:
g_Notify->DisplayError(stdstr_f("Unhandled CicChip(%d) in first DMA", g_Rom->CicChipID()).c_str());
return;
}
g_MMU->UpdateMemoryValue32(0x80000000 + offset, rt);
}
void CDMA::PI_DMA_READ()
{
if (g_Debugger != NULL && HaveDebugger())
{
g_Debugger->PIDMAReadStarted();
}
// PI_STATUS_REG |= PI_STATUS_DMA_BUSY;
uint32_t PI_RD_LEN_REG = ((g_Reg->PI_RD_LEN_REG) & 0x00FFFFFFul) + 1;
if ((PI_RD_LEN_REG & 1) != 0)
{
PI_RD_LEN_REG += 1;
}
if (g_Reg->PI_DRAM_ADDR_REG + PI_RD_LEN_REG > g_MMU->RdramSize())
{
if (HaveDebugger())
{
g_Notify->DisplayError(stdstr_f("PI_DMA_READ not in Memory: %08X", g_Reg->PI_DRAM_ADDR_REG + PI_RD_LEN_REG).c_str());
}
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
// 64DD buffers write
if (g_Reg->PI_CART_ADDR_REG >= 0x05000000 && g_Reg->PI_CART_ADDR_REG <= 0x050003FF)
{
// 64DD C2 sectors (don't care)
g_SystemTimer->SetTimer(g_SystemTimer->DDPiTimer, (PI_RD_LEN_REG * 63) / 25, false);
return;
}
if (g_Reg->PI_CART_ADDR_REG >= 0x05000400 && g_Reg->PI_CART_ADDR_REG <= 0x050004FF)
{
// 64DD user sector
uint32_t i;
uint8_t * RDRAM = g_MMU->Rdram();
uint8_t * DISK = g_Disk->GetDiskAddressBuffer();
for (i = 0; i < PI_RD_LEN_REG; i++)
{
*(DISK + (i ^ 3)) = *(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3));
}
g_SystemTimer->SetTimer(g_SystemTimer->DDPiTimer, (PI_RD_LEN_REG * 63) / 25, false);
return;
}
if (g_Reg->PI_CART_ADDR_REG >= 0x05000580 && g_Reg->PI_CART_ADDR_REG <= 0x050005BF)
{
// 64DD MSEQ (don't care)
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
// Write ROM area (for 64DD conversion)
if (g_Reg->PI_CART_ADDR_REG >= 0x10000000 && g_Reg->PI_CART_ADDR_REG <= 0x1FBFFFFF && g_Settings->LoadBool(Game_AllowROMWrites))
{
uint32_t i;
uint8_t * ROM = g_Rom->GetRomAddress();
uint8_t * RDRAM = g_MMU->Rdram();
ProtectMemory(ROM, g_Rom->GetRomSize(), MEM_READWRITE);
g_Reg->PI_CART_ADDR_REG -= 0x10000000;
if (g_Reg->PI_CART_ADDR_REG + PI_RD_LEN_REG < g_Rom->GetRomSize())
{
for (i = 0; i < PI_RD_LEN_REG; i++)
{
*(ROM + ((g_Reg->PI_CART_ADDR_REG + i) ^ 3)) = *(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3));
}
}
else
{
uint32_t Len;
Len = g_Rom->GetRomSize() - g_Reg->PI_CART_ADDR_REG;
for (i = 0; i < Len; i++)
{
*(ROM + ((g_Reg->PI_CART_ADDR_REG + i) ^ 3)) = *(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3));
}
}
g_Reg->PI_CART_ADDR_REG += 0x10000000;
if (!g_System->DmaUsed())
{
g_System->SetDmaUsed(true);
OnFirstDMA();
}
if (g_Recompiler && g_System->bSMM_PIDMA())
{
g_Recompiler->ClearRecompCode_Phys(g_Reg->PI_DRAM_ADDR_REG, g_Reg->PI_WR_LEN_REG, CRecompiler::Remove_DMA);
}
ProtectMemory(ROM, g_Rom->GetRomSize(), MEM_READONLY);
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
if (g_Reg->PI_CART_ADDR_REG >= 0x08000000 && g_Reg->PI_CART_ADDR_REG < 0x08088000)
{
if (m_Domain2Address2Handler.DMARead())
{
return;
}
}
if (g_System->m_SaveUsing == SaveChip_FlashRam)
{
g_Notify->DisplayError(stdstr_f("**** FlashRAM DMA read address %08X ****", g_Reg->PI_CART_ADDR_REG).c_str());
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
if (HaveDebugger())
{
g_Notify->DisplayError(stdstr_f("PI_DMA_READ where are you DMAing to? : %08X", g_Reg->PI_CART_ADDR_REG).c_str());
}
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
void CDMA::PI_DMA_WRITE()
{
if (g_Debugger != NULL && HaveDebugger())
{
g_Debugger->PIDMAWriteStarted();
}
// Rounding PI_WR_LEN_REG up to the nearest even number fixes AI Shougi 3, Doraemon 3, etc.
uint32_t PI_WR_LEN_REG = ((g_Reg->PI_WR_LEN_REG) & 0x00FFFFFEul) + 2;
uint32_t PI_CART_ADDR_REG = !g_Settings->LoadBool(Game_UnalignedDMA) ? g_Reg->PI_CART_ADDR_REG & ~1 : g_Reg->PI_CART_ADDR_REG;
g_Reg->PI_STATUS_REG |= PI_STATUS_DMA_BUSY;
if (g_Reg->PI_DRAM_ADDR_REG + PI_WR_LEN_REG > g_MMU->RdramSize())
{
if (ShowUnhandledMemory()) { g_Notify->DisplayError(stdstr_f("PI_DMA_WRITE not in memory: %08X", g_Reg->PI_DRAM_ADDR_REG + PI_WR_LEN_REG).c_str()); }
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
// 64DD buffers read
if (PI_CART_ADDR_REG >= 0x05000000 && PI_CART_ADDR_REG <= 0x050003FF)
{
// 64DD C2 sectors (just read 0)
uint32_t i;
uint8_t * RDRAM = g_MMU->Rdram();
for (i = 0; i < PI_WR_LEN_REG; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = 0;
}
// Timer is needed for track read
g_SystemTimer->SetTimer(g_SystemTimer->DDPiTimer, (PI_WR_LEN_REG * 63) / 25, false);
return;
}
if (PI_CART_ADDR_REG >= 0x05000400 && PI_CART_ADDR_REG <= 0x050004FF)
{
// 64DD user sector
uint32_t i;
uint8_t * RDRAM = g_MMU->Rdram();
uint8_t * DISK = g_Disk->GetDiskAddressBuffer();
for (i = 0; i < PI_WR_LEN_REG; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(DISK + (i ^ 3));
}
// Timer is needed for track read
g_SystemTimer->SetTimer(g_SystemTimer->DDPiTimer, (PI_WR_LEN_REG * 63) / 25, false);
return;
}
if (PI_CART_ADDR_REG >= 0x05000580 && PI_CART_ADDR_REG <= 0x050005BF)
{
// 64DD MSEQ (don't care)
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
return;
}
// 64DD IPL ROM
if (PI_CART_ADDR_REG >= 0x06000000 && PI_CART_ADDR_REG <= 0x063FFFFF)
{
uint32_t i;
uint8_t * ROM = g_DDRom->GetRomAddress();
uint8_t * RDRAM = g_MMU->Rdram();
PI_CART_ADDR_REG -= 0x06000000;
if (PI_CART_ADDR_REG + PI_WR_LEN_REG < g_DDRom->GetRomSize())
{
for (i = 0; i < PI_WR_LEN_REG; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((PI_CART_ADDR_REG + i) ^ 3));
}
}
else if (PI_CART_ADDR_REG >= g_DDRom->GetRomSize())
{
uint32_t cart = PI_CART_ADDR_REG - g_DDRom->GetRomSize();
while (cart >= g_DDRom->GetRomSize())
{
cart -= g_DDRom->GetRomSize();
}
for (i = 0; i < PI_WR_LEN_REG; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((cart + i) ^ 3));
}
}
else
{
uint32_t Len;
Len = g_DDRom->GetRomSize() - PI_CART_ADDR_REG;
for (i = 0; i < Len; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((PI_CART_ADDR_REG + i) ^ 3));
}
for (i = Len; i < PI_WR_LEN_REG - Len; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = 0;
}
}
PI_CART_ADDR_REG += 0x06000000;
if (!g_System->DmaUsed())
{
g_System->SetDmaUsed(true);
OnFirstDMA();
}
if (g_Recompiler && g_System->bSMM_PIDMA())
{
g_Recompiler->ClearRecompCode_Phys(g_Reg->PI_DRAM_ADDR_REG, g_Reg->PI_WR_LEN_REG, CRecompiler::Remove_DMA);
}
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
//ChangeTimer(PiTimer,(int32_t)(PI_WR_LEN_REG * 8.9) + 50);
//ChangeTimer(PiTimer,(int32_t)(PI_WR_LEN_REG * 8.9));
return;
}
if (PI_CART_ADDR_REG >= 0x08000000 && PI_CART_ADDR_REG <= 0x08088000)
{
m_Domain2Address2Handler.DMAWrite();
return;
}
if (PI_CART_ADDR_REG >= 0x10000000 && PI_CART_ADDR_REG <= 0x1FFFFFFF)
{
if (g_Recompiler && g_System->bSMM_PIDMA())
{
g_Recompiler->ClearRecompCode_Phys(g_Reg->PI_DRAM_ADDR_REG, g_Reg->PI_WR_LEN_REG, CRecompiler::Remove_DMA);
}
uint32_t i;
uint8_t * ROM = g_Rom->GetRomAddress();
uint8_t * RDRAM = g_MMU->Rdram();
PI_CART_ADDR_REG -= 0x10000000;
if (PI_CART_ADDR_REG + PI_WR_LEN_REG < g_Rom->GetRomSize())
{
size_t alignment;
RDRAM += g_Reg->PI_DRAM_ADDR_REG;
ROM += PI_CART_ADDR_REG;
alignment = PI_WR_LEN_REG | (size_t)RDRAM | (size_t)ROM;
if ((alignment & 0x3) == 0)
{
for (i = 0; i < PI_WR_LEN_REG; i += 4)
{
*(uint32_t *)(RDRAM + i) = *(uint32_t *)(ROM + i);
}
}
else if ((alignment & 1) == 0)
{
if ((PI_WR_LEN_REG & 2) == 0)
{
if (((size_t)RDRAM & 2) == 0)
{
for (i = 0; i < PI_WR_LEN_REG; i += 4)
{
*(uint16_t *)(((size_t)RDRAM + i) + 2) = *(uint16_t *)(((size_t)ROM + i) - 2);
*(uint16_t *)(((size_t)RDRAM + i) + 0) = *(uint16_t *)(((size_t)ROM + i) + 4);
}
}
else
{
if (((size_t)ROM & 2) == 0)
{
for (i = 0; i < PI_WR_LEN_REG; i += 4)
{
*(uint16_t *)(((size_t)RDRAM + i) - 2) = *(uint16_t *)(((size_t)ROM + i) + 2);
*(uint16_t *)(((size_t)RDRAM + i) + 4) = *(uint16_t *)(((size_t)ROM + i) + 0);
}
}
else
{
for (i = 0; i < PI_WR_LEN_REG; i += 4)
{
*(uint16_t *)(((size_t)RDRAM + i) - 2) = *(uint16_t *)(((size_t)ROM + i) - 2);
*(uint16_t *)(((size_t)RDRAM + i) + 4) = *(uint16_t *)(((size_t)ROM + i) + 4);
}
}
}
}
else
{
for (i = 0; i < PI_WR_LEN_REG; i += 2)
{
*(uint16_t *)(((size_t)RDRAM + i) ^ 2) = *(uint16_t *)(((size_t)ROM + i) ^ 2);
}
}
}
else
{
for (i = 0; i < PI_WR_LEN_REG; i++)
{
*(uint8_t *)(((size_t)RDRAM + i) ^ 3) = *(uint8_t *)(((size_t)ROM + i) ^ 3);
}
}
}
else if (PI_CART_ADDR_REG >= g_Rom->GetRomSize())
{
uint32_t cart = PI_CART_ADDR_REG - g_Rom->GetRomSize();
while (cart >= g_Rom->GetRomSize())
{
cart -= g_Rom->GetRomSize();
}
for (i = 0; i < PI_WR_LEN_REG; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((cart + i) ^ 3));
}
}
else
{
uint32_t Len;
Len = g_Rom->GetRomSize() - PI_CART_ADDR_REG;
for (i = 0; i < Len; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = *(ROM + ((PI_CART_ADDR_REG + i) ^ 3));
}
for (i = Len; i < PI_WR_LEN_REG - Len; i++)
{
*(RDRAM + ((g_Reg->PI_DRAM_ADDR_REG + i) ^ 3)) = 0;
}
}
PI_CART_ADDR_REG += 0x10000000;
if (!g_System->DmaUsed())
{
g_System->SetDmaUsed(true);
OnFirstDMA();
}
if(g_System->bRandomizeSIPIInterrupts())
{
g_SystemTimer->SetTimer(g_SystemTimer->PiTimer, PI_WR_LEN_REG / 8 + (g_Random->next() % 0x40), false);
}
else
{
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
}
//ChangeTimer(PiTimer,(int32_t)(PI_WR_LEN_REG * 8.9) + 50);
//ChangeTimer(PiTimer,(int32_t)(PI_WR_LEN_REG * 8.9));
return;
}
if (ShowUnhandledMemory())
{
g_Notify->DisplayError(stdstr_f("PI_DMA_WRITE not in ROM: %08X", PI_CART_ADDR_REG).c_str());
}
g_Reg->PI_STATUS_REG &= ~PI_STATUS_DMA_BUSY;
g_Reg->MI_INTR_REG |= MI_INTR_PI;
g_Reg->CheckInterrupts();
}

25
Source/Project64-core/N64System/Mips/Dma.h
View File

@ -1,25 +0,0 @@
#pragma once
#include <Project64-core\Settings\DebugSettings.h>
class CartridgeDomain2Address2Handler;
class CDMA :
private CDebugSettings
{
CDMA();
public:
void PI_DMA_READ();
void PI_DMA_WRITE();
protected:
CDMA(CartridgeDomain2Address2Handler & Domain2Address2Handler);
private:
CDMA(const CDMA&);
CDMA& operator=(const CDMA&);
void OnFirstDMA();
CartridgeDomain2Address2Handler & m_Domain2Address2Handler;
};

3
Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp
View File

@ -20,7 +20,6 @@ uint32_t CMipsMemoryVM::RegModValue;
CMipsMemoryVM::CMipsMemoryVM(CN64System & System, bool SavesReadOnly) :
CPifRam(SavesReadOnly),
CDMA(m_CartridgeDomain2Address2Handler),
m_System(System),
m_Reg(System.m_Reg),
m_AudioInterfaceHandler(System, System.m_Reg),
@ -30,7 +29,7 @@ CMipsMemoryVM::CMipsMemoryVM(CN64System & System, bool SavesReadOnly) :
m_RDRAMRegistersHandler(System.m_Reg),
m_DPCommandRegistersHandler(System, System.GetPlugins(), System.m_Reg),
m_MIPSInterfaceHandler(System.m_Reg),
m_PeripheralInterfaceHandler(*this, System.m_Reg),
m_PeripheralInterfaceHandler(*this, System.m_Reg, m_CartridgeDomain2Address2Handler),
m_PifRamHandler(*this, System.m_Reg),
m_RDRAMInterfaceHandler(System.m_Reg),
m_RomMemoryHandler(System, System.m_Reg, *g_Rom),

2
Source/Project64-core/N64System/Mips/MemoryVirtualMem.h
View File

@ -4,7 +4,6 @@
#include <Project64-core\N64System\Interpreter\InterpreterOps.h>
#include <Project64-core\N64System\Mips\PifRam.h>
#include <Project64-core\N64System\SaveType\FlashRam.h>
#include <Project64-core\N64System\Mips\Dma.h>
#include <Project64-core\N64System\MemoryHandler\AudioInterfaceHandler.h>
#include <Project64-core\N64System\MemoryHandler\CartridgeDomain1Address1Handler.h>
#include <Project64-core\N64System\MemoryHandler\CartridgeDomain1Address3Handler.h>
@ -51,7 +50,6 @@ class CArmRecompilerOps;
class CMipsMemoryVM :
private R4300iOp,
public CPifRam,
public CDMA,
private CGameSettings
{
public:

73
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -10580,48 +10580,24 @@ void CX86RecompilerOps::SW_Const(uint32_t Value, uint32_t VAddr)
case 0x04600000: MoveConstToVariable(Value, &g_Reg->PI_DRAM_ADDR_REG, "PI_DRAM_ADDR_REG"); break;
case 0x04600004: MoveConstToVariable(Value, &g_Reg->PI_CART_ADDR_REG, "PI_CART_ADDR_REG"); break;
case 0x04600008:
MoveConstToVariable(Value, &g_Reg->PI_RD_LEN_REG, "PI_RD_LEN_REG");
m_RegWorkingSet.BeforeCallDirect();
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)((CDMA *)g_MMU), x86_ECX);
Call_Direct(AddressOf(&CDMA::PI_DMA_READ), "CDMA::PI_DMA_READ");
#else
PushImm32((uint32_t)((CDMA *)g_MMU));
Call_Direct(AddressOf(&CDMA::PI_DMA_READ), "CDMA::PI_DMA_READ");
AddConstToX86Reg(x86_ESP, 4);
#endif
m_RegWorkingSet.AfterCallDirect();
break;
case 0x0460000C:
case 0x04600010:
UpdateCounters(m_RegWorkingSet, false, true, false);
MoveConstToVariable(Value, &g_Reg->PI_WR_LEN_REG, "PI_WR_LEN_REG");
m_RegWorkingSet.BeforeCallDirect();
PushImm32(0xFFFFFFFF);
PushImm32(Value);
PushImm32(PAddr & 0x1FFFFFFF);
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)((CDMA *)g_MMU), x86_ECX);
Call_Direct(AddressOf(&CDMA::PI_DMA_WRITE), "CDMA::PI_DMA_WRITE");
MoveConstToX86reg((uint32_t)(MemoryHandler *)&g_MMU->m_PeripheralInterfaceHandler, x86_ECX);
Call_Direct((void *)((long**)(MemoryHandler *)&g_MMU->m_PeripheralInterfaceHandler)[0][1], "PeripheralInterfaceHandler::Write32");
#else
PushImm32((uint32_t)((CDMA *)g_MMU));
Call_Direct(AddressOf(&CDMA::PI_DMA_WRITE), "CDMA::PI_DMA_WRITE");
AddConstToX86Reg(x86_ESP, 4);
PushImm32((uint32_t)&g_MMU->m_PeripheralInterfaceHandler);
Call_Direct(AddressOf(&m_PeripheralInterfaceHandler::Write32), "PeripheralInterfaceHandler::Write32");
AddConstToX86Reg(x86_ESP, 16);
#endif
m_RegWorkingSet.AfterCallDirect();
break;
case 0x04600010:
if ((Value & PI_CLR_INTR) != 0)
{
AndConstToVariable((uint32_t)~MI_INTR_PI, &g_Reg->MI_INTR_REG, "MI_INTR_REG");
m_RegWorkingSet.BeforeCallDirect();
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)g_Reg, x86_ECX);
Call_Direct(AddressOf(&CRegisters::CheckInterrupts), "CRegisters::CheckInterrupts");
#else
PushImm32((uint32_t)g_Reg);
Call_Direct(AddressOf(&CRegisters::CheckInterrupts), "CRegisters::CheckInterrupts");
AddConstToX86Reg(x86_ESP, 4);
#endif
m_RegWorkingSet.AfterCallDirect();
}
break;
case 0x04600014: MoveConstToVariable((Value & 0xFF), &g_Reg->PI_DOMAIN1_REG, "PI_DOMAIN1_REG"); break;
case 0x04600018: MoveConstToVariable((Value & 0xFF), &g_Reg->PI_BSD_DOM1_PWD_REG, "PI_BSD_DOM1_PWD_REG"); break;
case 0x0460001C: MoveConstToVariable((Value & 0xFF), &g_Reg->PI_BSD_DOM1_PGS_REG, "PI_BSD_DOM1_PGS_REG"); break;
@ -11039,29 +11015,20 @@ void CX86RecompilerOps::SW_Register(x86Reg Reg, uint32_t VAddr)
}
break;
case 0x04600008:
MoveX86regToVariable(Reg, &g_Reg->PI_RD_LEN_REG, "PI_RD_LEN_REG");
m_RegWorkingSet.BeforeCallDirect();
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)((CDMA *)g_MMU), x86_ECX);
Call_Direct(AddressOf(&CDMA::PI_DMA_READ), "CDMA::PI_DMA_READ");
#else
PushImm32((uint32_t)((CDMA *)g_MMU));
Call_Direct(AddressOf(&CDMA::PI_DMA_READ), "CDMA::PI_DMA_READ");
AddConstToX86Reg(x86_ESP, 4);
#endif
m_RegWorkingSet.AfterCallDirect();
break;
case 0x0460000C:
UpdateCounters(m_RegWorkingSet, false, true, false);
MoveX86regToVariable(Reg, &g_Reg->PI_WR_LEN_REG, "PI_WR_LEN_REG");
UpdateCounters(m_RegWorkingSet, false, true);
m_RegWorkingSet.BeforeCallDirect();
PushImm32(0xFFFFFFFF);
Push(Reg);
PushImm32(PAddr & 0x1FFFFFFF);
#ifdef _MSC_VER
MoveConstToX86reg((uint32_t)((CDMA *)g_MMU), x86_ECX);
Call_Direct(AddressOf(&CDMA::PI_DMA_WRITE), "CDMA::PI_DMA_WRITE");
MoveConstToX86reg((uint32_t)(MemoryHandler *)&g_MMU->m_PeripheralInterfaceHandler, x86_ECX);
Call_Direct((void *)((long**)(MemoryHandler *)&g_MMU->m_PeripheralInterfaceHandler)[0][1], "PeripheralInterfaceHandler::Write32");
#else
PushImm32((uint32_t)((CDMA *)g_MMU));
Call_Direct(AddressOf(&CDMA::PI_DMA_WRITE), "CDMA::PI_DMA_WRITE");
AddConstToX86Reg(x86_ESP, 4);
PushImm32((uint32_t)&g_MMU->PeripheralInterfaceHandler);
Call_Direct(AddressOf(&PeripheralInterfaceHandler::Write32), "PeripheralInterfaceHandler::Write32");
AddConstToX86Reg(x86_ESP, 16);
#endif
m_RegWorkingSet.AfterCallDirect();
break;

2
Source/Project64-core/Project64-core.vcxproj
View File

@ -69,7 +69,6 @@
<ClCompile Include="N64System\MemoryHandler\SPRegistersHandler.cpp" />
<ClCompile Include="N64System\MemoryHandler\VideoInterfaceHandler.cpp" />
<ClCompile Include="N64System\Mips\Disk.cpp" />
<ClCompile Include="N64System\Mips\Dma.cpp" />
<ClCompile Include="N64System\Mips\GBCart.cpp" />
<ClCompile Include="N64System\Mips\MemoryVirtualMem.cpp" />
<ClCompile Include="N64System\Mips\Mempak.cpp" />
@ -179,7 +178,6 @@
<ClInclude Include="N64System\MemoryHandler\SPRegistersHandler.h" />
<ClInclude Include="N64System\MemoryHandler\VideoInterfaceHandler.h" />
<ClInclude Include="N64System\Mips\Disk.h" />
<ClInclude Include="N64System\Mips\Dma.h" />
<ClInclude Include="N64System\Mips\Eeprom.h" />
<ClInclude Include="N64System\Mips\FlashRam.h" />
<ClInclude Include="N64System\Mips\GBCart.h" />

6
Source/Project64-core/Project64-core.vcxproj.filters
View File

@ -249,9 +249,6 @@
<ClCompile Include="N64System\Recompiler\SectionInfo.cpp">
<Filter>Source Files\N64 System\Recompiler</Filter>
</ClCompile>
<ClCompile Include="N64System\Mips\Dma.cpp">
<Filter>Source Files\N64 System\Mips</Filter>
</ClCompile>
<ClCompile Include="N64System\Mips\MemoryVirtualMem.cpp">
<Filter>Source Files\N64 System\Mips</Filter>
</ClCompile>
@ -590,9 +587,6 @@
<ClInclude Include="N64System\Recompiler\SectionInfo.h">
<Filter>Header Files\N64 System\Recompiler</Filter>
</ClInclude>
<ClInclude Include="N64System\Mips\Dma.h">
<Filter>Header Files\N64 System\Mips</Filter>
</ClInclude>
<ClInclude Include="N64System\Mips\Eeprom.h">
<Filter>Header Files\N64 System\Mips</Filter>
</ClInclude>