Connor McLaughlin
|
767e8f08e0
|
CDROM: Move pregap handling to image class
|
2019-09-26 00:15:06 +10:00 |
|
Connor McLaughlin
|
ba67f69c2a
|
GTE: Implement NCCS/NCCT/NCDT/DPCS
|
2019-09-25 20:24:50 +10:00 |
|
Connor McLaughlin
|
b9b286e93d
|
GPU: Fix shader compile error on Intel
|
2019-09-25 20:24:19 +10:00 |
|
Connor McLaughlin
|
c18597c3bf
|
GTE: Implement unverified MVMVA
|
2019-09-25 15:58:33 +10:00 |
|
Connor McLaughlin
|
3df7b22c37
|
GTE: Fix NCDS
|
2019-09-25 15:40:08 +10:00 |
|
Connor McLaughlin
|
607cd4d3e4
|
CDROM: Stub out Setfilter
|
2019-09-25 00:44:41 +10:00 |
|
Connor McLaughlin
|
9359d0778e
|
Clean up memory access handlers, reduce template specializations
|
2019-09-25 00:36:24 +10:00 |
|
Connor McLaughlin
|
4aca52cdf4
|
CPU: Silence some debug spam
|
2019-09-24 23:56:30 +10:00 |
|
Connor McLaughlin
|
6aa36c2ead
|
SPU: Hook up DMA reads/writes to RAM
|
2019-09-24 23:55:57 +10:00 |
|
Connor McLaughlin
|
575a3b36f5
|
CDROM: Store the image path/current lba as part of the save state
|
2019-09-24 23:55:34 +10:00 |
|
Connor McLaughlin
|
1276241622
|
SPU: Create stub needed for DMA to work
|
2019-09-24 23:44:38 +10:00 |
|
Connor McLaughlin
|
7a413b4031
|
CDROM: Proper handling of request register
|
2019-09-24 21:39:38 +10:00 |
|
Connor McLaughlin
|
4bb8fb211d
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DMA: Delay transfer/interrupt
|
2019-09-24 21:39:13 +10:00 |
|
Connor McLaughlin
|
4cc83e2228
|
DMA: Implement interrupts
|
2019-09-24 19:43:10 +10:00 |
|
Connor McLaughlin
|
db777fdabb
|
CDROM: Various fixes
|
2019-09-24 01:33:18 +10:00 |
|
Connor McLaughlin
|
1f13c4ad2c
|
Pad: Fix long transmit delay breaking other things
|
2019-09-24 01:31:17 +10:00 |
|
Connor McLaughlin
|
d65c9b3592
|
CDROM: Read timing and demute command, seek on ReadN
|
2019-09-23 23:31:51 +10:00 |
|
Connor McLaughlin
|
20f14688ca
|
System: Support loading expansion ROMs
|
2019-09-23 01:38:21 +10:00 |
|
Connor McLaughlin
|
5d1c12c9ad
|
Pad: Fix timing issues w/ BIOS
|
2019-09-23 01:25:58 +10:00 |
|
Connor McLaughlin
|
734d1a7ee1
|
InterruptController: Masked interrupts are still set in the status register
|
2019-09-23 01:24:36 +10:00 |
|
Connor McLaughlin
|
fbd7fcec48
|
GTE: Implement NCDS (but incorrectly)
|
2019-09-22 21:41:11 +10:00 |
|
Connor McLaughlin
|
f2d62fcce0
|
CDROM: Hack timings to get further with booting
|
2019-09-22 21:40:44 +10:00 |
|
Connor McLaughlin
|
c772047715
|
GTE: Add AVSZ3/AVSZ4
|
2019-09-22 20:38:11 +10:00 |
|
Connor McLaughlin
|
005b06ae0c
|
GTE: More implementation work, Reg+NCLIP+STR tests passing
|
2019-09-22 17:33:11 +10:00 |
|
Connor McLaughlin
|
3fb08a72a4
|
CDROM: Hack around missing pregap in images
|
2019-09-22 02:32:45 +10:00 |
|
Connor McLaughlin
|
948ac50020
|
CPU: Refactoring, implement LWC/SWC
|
2019-09-22 02:06:47 +10:00 |
|
Connor McLaughlin
|
2875a22987
|
CDROM: Reads appear to be functioning
|
2019-09-22 01:12:16 +10:00 |
|
Connor McLaughlin
|
c988af453c
|
Refactor timing to allow sync/updates in the middle of a slice
|
2019-09-21 01:24:33 +10:00 |
|
Connor McLaughlin
|
ad316162f3
|
Basic timer implementation
|
2019-09-20 23:40:19 +10:00 |
|
Connor McLaughlin
|
ad652c47ed
|
Basic CD image loading
|
2019-09-20 20:14:00 +10:00 |
|
Connor McLaughlin
|
53e755aa68
|
Pad: Save state support
|
2019-09-20 19:21:45 +10:00 |
|
Connor McLaughlin
|
8cd75a4937
|
PAD: Basic support for digital controllers
|
2019-09-20 16:47:41 +10:00 |
|
Connor McLaughlin
|
d84bffead1
|
GPU: Implement transparency mode
|
2019-09-19 00:55:06 +10:00 |
|
Connor McLaughlin
|
23ef1cafbd
|
GPU: Force 16-bit precision when filling VRAM, clear mask bit
|
2019-09-18 15:54:57 +10:00 |
|
Connor McLaughlin
|
d8150c996b
|
GPU: Support dumping copies out to file
|
2019-09-18 15:43:25 +10:00 |
|
Connor McLaughlin
|
4d624946d6
|
GPU: Texpage attribute can change texture mode too
|
2019-09-18 15:24:29 +10:00 |
|
Connor McLaughlin
|
4d4ab898c0
|
GPU: Flush rendering before VRAM->VRAM copies
|
2019-09-18 15:15:03 +10:00 |
|
Connor McLaughlin
|
2c07db6dd5
|
GPU: Flush rendering before VRAM reads
|
2019-09-18 15:14:31 +10:00 |
|
Connor McLaughlin
|
4d38213f23
|
GPU: Implement VRAM-to-VRAM copies
|
2019-09-18 00:58:30 +10:00 |
|
Connor McLaughlin
|
0a8bce8936
|
GPU: Hook up vblank interrupt
|
2019-09-18 00:22:41 +10:00 |
|
Connor McLaughlin
|
a84b3d7a2b
|
CPU: Fix interrupts in branch delay slots messing up PC
|
2019-09-18 00:22:17 +10:00 |
|
Connor McLaughlin
|
4025d6e4a6
|
GTE: Stub and register read/write function
|
2019-09-17 23:38:04 +10:00 |
|
Connor McLaughlin
|
6df8d42480
|
CDROM: Add missing fields to save state
|
2019-09-17 23:04:00 +10:00 |
|
Connor McLaughlin
|
e3c6035152
|
CDROM: Implement get version and getstat commands
|
2019-09-17 22:18:58 +10:00 |
|
Connor McLaughlin
|
b951f27381
|
CDROM: Stub implementation
|
2019-09-17 21:07:56 +10:00 |
|
Connor McLaughlin
|
a0e7dff37c
|
common: Add a FIFOQueue helper class
|
2019-09-17 19:22:23 +10:00 |
|
Connor McLaughlin
|
2128a2984b
|
Add interrupt controller emulation
|
2019-09-17 16:26:00 +10:00 |
|
Connor McLaughlin
|
c615e007c0
|
GPU: Serialization for CRTC state
|
2019-09-17 14:40:23 +10:00 |
|
Connor McLaughlin
|
f47688b61f
|
System: Basic timings for GPU scanout
|
2019-09-17 14:25:25 +10:00 |
|
Connor McLaughlin
|
9475c281bd
|
Build: Set /MP on projects which are missing it
|
2019-09-17 14:25:17 +10:00 |
|
Connor McLaughlin
|
540f282213
|
CPU: Fix incorrect exception vector for break
|
2019-09-15 12:43:54 +10:00 |
|
Connor McLaughlin
|
5babc076f5
|
Bitfield: Fix incorrect shift in operator<<=
|
2019-09-15 12:42:43 +10:00 |
|
Connor McLaughlin
|
d58dbe04c0
|
CPU: Fix load delay register reads for same register in delay slot
|
2019-09-15 12:16:51 +10:00 |
|
Connor McLaughlin
|
1bb794dd39
|
GPU: Use max vertex count based on buffer size
|
2019-09-15 01:18:58 +10:00 |
|
Connor McLaughlin
|
a58b687352
|
GPU: Cap batch sizes at 1024 vertices, flush if exceeded
|
2019-09-15 01:13:23 +10:00 |
|
Connor McLaughlin
|
4ca3b4b570
|
CPU: Fix alignment exception on register indirect branch
|
2019-09-15 01:13:11 +10:00 |
|
Connor McLaughlin
|
bea727bbe4
|
CPU: Fix BGEZAL with rs == ra
|
2019-09-15 01:02:35 +10:00 |
|
Connor McLaughlin
|
273f010d17
|
GPU: Use degenerate triangles to split strips and batch them
|
2019-09-15 00:17:43 +10:00 |
|
Connor McLaughlin
|
1c8e326624
|
GPU: Fix off-by-one in rectangle rendering
|
2019-09-14 23:50:34 +10:00 |
|
Connor McLaughlin
|
77b15d156d
|
System: Periodically flush GPU
Needs real timings...
|
2019-09-14 23:50:24 +10:00 |
|
Connor McLaughlin
|
03bd135060
|
SDL: Make GL debug output less noisy in Release
|
2019-09-14 23:49:21 +10:00 |
|
Connor McLaughlin
|
b5d51f47cd
|
GPU: Use texel fetch for creating page textures
|
2019-09-14 23:48:32 +10:00 |
|
Connor McLaughlin
|
19d9322e67
|
GPU: Fix texture coordinates when rendering paletted textures
|
2019-09-14 23:05:10 +10:00 |
|
Connor McLaughlin
|
e40393fec4
|
GPU: Use scissor test for drawing area
|
2019-09-14 21:54:58 +10:00 |
|
Connor McLaughlin
|
3d6b8e485e
|
Interface: Support loading filenames on command line
|
2019-09-14 21:54:46 +10:00 |
|
Connor McLaughlin
|
363d62e5c1
|
GPU: Various HW renderer fixes
|
2019-09-14 21:34:55 +10:00 |
|
Connor McLaughlin
|
d94d608ad7
|
GPU: Implment actual data copy of VRAM->CPU readbacks
|
2019-09-14 20:48:15 +10:00 |
|
Connor McLaughlin
|
f6ef3f7ba6
|
GPU: Saving/loading of VRAM
|
2019-09-14 20:45:26 +10:00 |
|
Connor McLaughlin
|
2560efbebd
|
Save state support
|
2019-09-14 20:28:47 +10:00 |
|
Connor McLaughlin
|
851ef67814
|
GPU: Implement fill VRAM command
|
2019-09-14 16:43:53 +10:00 |
|
Connor McLaughlin
|
46870c6a7a
|
GPU: Implement basic rectangle rendering
|
2019-09-14 16:27:24 +10:00 |
|
Connor McLaughlin
|
f47d44c151
|
CPU: Implement break instruction
|
2019-09-14 14:41:41 +10:00 |
|
Connor McLaughlin
|
32a36ef1bc
|
CPU: Implement alignment (memory) exception
|
2019-09-14 14:29:23 +10:00 |
|
Connor McLaughlin
|
0726095f00
|
CPU: Implement fixed dcache/scratchpad
|
2019-09-14 14:18:42 +10:00 |
|
Connor McLaughlin
|
ced3038e73
|
CPU: Implement sub instruction
|
2019-09-14 13:39:36 +10:00 |
|
Connor McLaughlin
|
1afa02d475
|
CPU: Fix overflowed register written back in add instruction
|
2019-09-14 13:33:29 +10:00 |
|
Connor McLaughlin
|
459db392e7
|
CPU: Add missing cop0 register reads
|
2019-09-14 13:31:44 +10:00 |
|
Connor McLaughlin
|
9f36384752
|
System: Support sideloading EXE files via BIOS patch
|
2019-09-14 13:22:34 +10:00 |
|
Connor McLaughlin
|
ae43cc838b
|
GPU: Partially implemented texture support
|
2019-09-14 02:07:31 +10:00 |
|
Connor McLaughlin
|
cfe361c1a6
|
GPU: Basic/hacky CPU->VRAM transfers
|
2019-09-13 01:10:08 +10:00 |
|
Connor McLaughlin
|
52b619facc
|
DMA: Implement block transfers
|
2019-09-13 01:09:44 +10:00 |
|
Connor McLaughlin
|
aea7a18ac2
|
GPU: More work on OpenGL renderer
|
2019-09-13 01:09:07 +10:00 |
|
Connor McLaughlin
|
4706a906d5
|
GPU: Base work for hardware renderer
|
2019-09-12 12:53:04 +10:00 |
|
Connor McLaughlin
|
c0853de6a6
|
GPU: Partial render polygon command processing
|
2019-09-11 16:04:31 +10:00 |
|
Connor McLaughlin
|
162f94337e
|
DMA: Implement linked list mode
|
2019-09-11 15:02:22 +10:00 |
|
Connor McLaughlin
|
27913cd20a
|
Partial implementation of DMA controller and GPU stubs
|
2019-09-11 14:01:19 +10:00 |
|
Connor McLaughlin
|
2149ab4d69
|
Initial commit
|
2019-09-11 14:00:42 +10:00 |