GTE: Stub and register read/write function
This commit is contained in:
parent
6df8d42480
commit
4025d6e4a6
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@ -1,192 +0,0 @@
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#include "cpu_bus.h"
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#include "YBaseLib/ByteStream.h"
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#include "YBaseLib/Log.h"
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#include "YBaseLib/String.h"
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#include <cstdio>
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Log_SetChannel(Bus);
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Bus::Bus() = default;
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Bus::~Bus() = default;
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bool Bus::Initialize(System* system)
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{
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if (!LoadBIOS())
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return false;
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return true;
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}
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void Bus::Reset()
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{
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m_ram.fill(static_cast<u8>(0));
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}
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bool Bus::DoState(StateWrapper& sw)
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{
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return false;
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}
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bool Bus::ReadByte(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u8* value)
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{
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u32 temp = 0;
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const bool result = DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::Byte>(cpu_address, bus_address, temp);
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*value = Truncate8(temp);
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return result;
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}
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bool Bus::ReadWord(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u16* value)
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{
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u32 temp = 0;
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const bool result =
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DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(cpu_address, bus_address, temp);
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*value = Truncate16(temp);
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return result;
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}
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bool Bus::ReadDWord(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u32* value)
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{
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return DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::Word>(cpu_address, bus_address, *value);
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}
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bool Bus::WriteByte(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u8 value)
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{
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u32 temp = ZeroExtend32(value);
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return DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::Byte>(cpu_address, bus_address, temp);
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}
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bool Bus::WriteWord(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u16 value)
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{
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u32 temp = ZeroExtend32(value);
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return DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(cpu_address, bus_address, temp);
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}
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bool Bus::WriteDWord(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u32 value)
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{
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return DispatchAccess<MemoryAccessType::Write, MemoryAccessSize::Word>(cpu_address, bus_address, value);
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}
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bool Bus::LoadBIOS()
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{
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std::FILE* fp = std::fopen("SCPH1001.BIN", "rb");
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if (!fp)
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return false;
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std::fseek(fp, 0, SEEK_END);
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const u32 size = static_cast<u32>(std::ftell(fp));
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std::fseek(fp, 0, SEEK_SET);
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if (size != m_bios.size())
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{
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Log_ErrorPrintf("BIOS image mismatch, expecting %u bytes, got %u bytes", static_cast<u32>(m_bios.size()), size);
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std::fclose(fp);
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return false;
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}
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if (std::fread(m_bios.data(), 1, m_bios.size(), fp) != m_bios.size())
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{
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Log_ErrorPrintf("Failed to read BIOS image");
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std::fclose(fp);
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return false;
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}
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std::fclose(fp);
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#if 1
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auto Patch = [this](u32 address, u32 value) { std::memcpy(&m_bios[address], &value, sizeof(value)); };
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Patch(0x6F0C, 0x24010001); // addiu $at, $zero, 1
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Patch(0x6F14, 0xaf81a9c0); // sw at, -0x5640(gp)
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#endif
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return true;
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}
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bool Bus::DoInvalidAccess(MemoryAccessType type, MemoryAccessSize size, PhysicalMemoryAddress cpu_address,
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PhysicalMemoryAddress bus_address, u32& value)
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{
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SmallString str;
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str.AppendString("Invalid bus ");
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if (size == MemoryAccessSize::Byte)
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str.AppendString("byte");
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if (size == MemoryAccessSize::HalfWord)
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str.AppendString("word");
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if (size == MemoryAccessSize::Word)
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str.AppendString("dword");
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str.AppendCharacter(' ');
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if (type == MemoryAccessType::Read)
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str.AppendString("read");
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else
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str.AppendString("write");
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str.AppendFormattedString(" at address 0x%08X (virtual address 0x%08X)", bus_address, cpu_address);
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if (type == MemoryAccessType::Write)
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str.AppendFormattedString(" (value 0x%08X)", value);
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Log_ErrorPrint(str);
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if (type == MemoryAccessType::Read)
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value = UINT32_C(0xFFFFFFFF);
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return true;
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}
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bool Bus::ReadExpansionRegion2(MemoryAccessSize size, u32 offset, u32& value)
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{
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offset &= EXP2_MASK;
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// rx/tx buffer empty
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if (offset == 0x21)
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{
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value = 0x04 | 0x08;
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return true;
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}
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return DoInvalidAccess(MemoryAccessType::Read, size, EXP2_BASE | offset, EXP2_BASE | offset, value);
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}
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bool Bus::WriteExpansionRegion2(MemoryAccessSize size, u32 offset, u32 value)
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{
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offset &= EXP2_MASK;
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if (offset == 0x23)
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{
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if (value == '\r')
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return true;
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if (value == '\n')
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{
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if (!m_tty_line_buffer.IsEmpty())
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Log_InfoPrintf("TTY: %s", m_tty_line_buffer.GetCharArray());
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m_tty_line_buffer.Clear();
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}
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else
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{
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m_tty_line_buffer.AppendCharacter(Truncate8(value));
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}
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return true;
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}
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if (offset == 0x41)
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{
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Log_WarningPrintf("BIOS POST status: %02X", value & UINT32_C(0x0F));
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return true;
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}
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return DoInvalidAccess(MemoryAccessType::Write, size, EXP2_BASE | offset, EXP2_BASE | offset, value);
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}
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bool Bus::ReadSPU(MemoryAccessSize size, u32 offset, u32& value)
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{
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if (offset == 0x1AE)
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{
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value = 0;
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return true;
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}
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return DoInvalidAccess(MemoryAccessType::Write, size, SPU_BASE | offset, SPU_BASE | offset, value);
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}
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bool Bus::WriteSPU(MemoryAccessSize size, u32 offset, u32 value)
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{
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return DoInvalidAccess(MemoryAccessType::Write, size, SPU_BASE | offset, SPU_BASE | offset, value);
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}
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@ -19,6 +19,8 @@ bool Core::Initialize(Bus* bus)
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// From nocash spec.
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m_cop0_regs.PRID = UINT32_C(0x00000002);
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m_cop2.Initialize();
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return true;
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}
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@ -38,6 +40,8 @@ void Core::Reset()
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m_cop0_regs.sr.bits = 0;
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m_cop0_regs.cause.bits = 0;
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m_cop2.Reset();
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SetPC(RESET_VECTOR);
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}
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@ -70,6 +74,10 @@ bool Core::DoState(StateWrapper& sw)
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sw.Do(&m_branched);
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sw.Do(&m_cache_control);
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sw.DoBytes(m_dcache.data(), m_dcache.size());
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if (!m_cop2.DoState(sw))
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return false;
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return !sw.HasError();
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}
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@ -893,17 +901,24 @@ void Core::ExecuteInstruction(Instruction inst)
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}
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break;
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// COP1/COP3 are not present
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case InstructionOp::cop1:
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case InstructionOp::cop2:
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{
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RaiseException(Exception::CpU, inst.cop.cop_n);
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if (!m_cop0_regs.sr.CU0 && InUserMode())
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{
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Log_WarningPrintf("Coprocessor 2 not present in user mode");
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RaiseException(Exception::CpU, 2);
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return;
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}
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ExecuteCop2Instruction(inst);
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}
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break;
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// COP1/COP3 are not present
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case InstructionOp::cop1:
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case InstructionOp::cop3:
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{
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Panic("GTE not implemented");
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RaiseException(Exception::CpU, inst.cop.cop_n);
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}
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break;
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@ -1059,4 +1074,34 @@ void Core::ExecuteCop0Instruction(Instruction inst)
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}
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}
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void Core::ExecuteCop2Instruction(Instruction inst)
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{
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if (inst.cop.IsCommonInstruction())
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{
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// TODO: Combine with cop0.
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switch (inst.cop.cop2_op())
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{
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case Cop2Instruction::mfc2:
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case Cop2Instruction::cfc2:
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case Cop2Instruction::mtc2:
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case Cop2Instruction::ctc2:
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{
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const u32 index = static_cast<u32>(inst.r.rd.GetValue());
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const u32 value = ReadReg(inst.r.rt);
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m_cop2.WriteControlRegister(index, value);
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}
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break;
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case Cop2Instruction::bc2c:
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default:
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Panic("Missing implementation");
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break;
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}
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}
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else
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{
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m_cop2.ExecuteInstruction(GTE::Instruction{inst.bits});
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}
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}
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} // namespace CPU
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@ -1,6 +1,7 @@
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#pragma once
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#include "common/bitfield.h"
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#include "cpu_types.h"
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#include "gte.h"
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#include "types.h"
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#include <array>
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@ -74,6 +75,7 @@ private:
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bool FetchInstruction();
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void ExecuteInstruction(Instruction inst);
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void ExecuteCop0Instruction(Instruction inst);
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void ExecuteCop2Instruction(Instruction inst);
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void Branch(u32 target);
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// exceptions
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@ -121,6 +123,8 @@ private:
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// data cache (used as scratchpad)
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std::array<u8, DCACHE_SIZE> m_dcache = {};
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GTE::Core m_cop2;
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};
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extern bool TRACE_EXECUTION;
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@ -168,6 +168,13 @@ static const std::array<std::pair<Cop0Instruction, const char*>, 6> s_cop0_table
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{Cop0Instruction::bc0c, "bc0$copcc $rel"},
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{Cop0Instruction::rfe, "rfe"}}};
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static const std::array<std::pair<Cop2Instruction, const char*>, 6> s_cop2_common_table = {
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{{Cop2Instruction::mfc2, "mfc2 $rt, $coprd"},
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{Cop2Instruction::cfc2, "cfc2 $rt, $copcr"},
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{Cop2Instruction::mtc2, "mtc2 $rt, $coprd"},
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{Cop2Instruction::ctc2, "ctc2 $rt, $copcr"},
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{Cop2Instruction::bc2c, "bc2$copcc $rel"}}};
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static void FormatInstruction(String* dest, const Instruction inst, u32 pc, const char* format)
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{
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dest->Clear();
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@ -266,7 +273,7 @@ void FormatCopInstruction(String* dest, u32 pc, const Instruction inst, const st
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}
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}
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dest->Format("<cop%u 0x%07X>", ZeroExtend32(inst.cop.cop_n.GetValue()), inst.cop.imm25.GetValue());
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dest->Format("<cop%u 0x%08X>", ZeroExtend32(inst.cop.cop_n.GetValue()), inst.cop.imm25.GetValue());
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}
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void DisassembleInstruction(String* dest, u32 pc, u32 bits)
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@ -282,10 +289,23 @@ void DisassembleInstruction(String* dest, u32 pc, u32 bits)
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FormatCopInstruction(dest, pc, inst, s_cop0_table.data(), s_cop0_table.size(), inst.cop.cop0_op());
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return;
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case InstructionOp::cop1:
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case InstructionOp::cop2:
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{
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if (inst.cop.IsCommonInstruction())
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{
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FormatCopInstruction(dest, pc, inst, s_cop2_common_table.data(), s_cop2_common_table.size(),
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inst.cop.cop2_op());
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}
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else
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{
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dest->Format("<cop%u 0x%08X>", ZeroExtend32(inst.cop.cop_n.GetValue()), inst.cop.imm25.GetValue());
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}
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}
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break;
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case InstructionOp::cop1:
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case InstructionOp::cop3:
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dest->Format("<cop%u 0x%07X>", ZeroExtend32(inst.cop.cop_n.GetValue()), inst.cop.imm25.GetValue());
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dest->Format("<cop%u 0x%08X>", ZeroExtend32(inst.cop.cop_n.GetValue()), inst.cop.imm25.GetValue());
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break;
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// special case for bltz/bgez{al}
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@ -127,6 +127,15 @@ enum class Cop0Instruction : u32 // 25:21 | 0:5
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rfe = 0b10000'010000,
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};
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enum class Cop2Instruction : u32 // 25:21
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{
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mfc2 = 0b0000,
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cfc2 = 0b0010,
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mtc2 = 0b0100,
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ctc2 = 0b0110,
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bc2c = 0b1000,
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};
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union Instruction
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{
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u32 bits;
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@ -164,10 +173,17 @@ union Instruction
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BitField<u32, u16, 0, 16> imm16;
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BitField<u32, u32, 0, 25> imm25;
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bool IsCommonInstruction() const { return (bits & (UINT32_C(1) << 25)) == 0; }
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Cop0Instruction cop0_op() const
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{
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return static_cast<Cop0Instruction>(((bits >> 15) & UINT32_C(0b11111000000)) | (bits & UINT32_C(0b111111)));
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}
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Cop2Instruction cop2_op() const
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{
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return static_cast<Cop2Instruction>((bits >> 21) & UINT32_C(0b1111));
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}
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} cop;
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};
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@ -653,7 +653,7 @@ bool GPU::HandleCopyRectangleVRAMToCPUCommand()
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Log_DebugPrintf("Copy rectangle from VRAM to CPU offset=(%u,%u), size=(%u,%u)", src_x, src_y, width, height);
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if ((src_x + width) > VRAM_WIDTH || (src_x + height) > VRAM_HEIGHT)
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if ((src_x + width) > VRAM_WIDTH || (src_y + height) > VRAM_HEIGHT)
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{
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Panic("Out of bounds VRAM copy");
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return true;
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@ -0,0 +1,24 @@
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#include "gte.h"
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namespace GTE {
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Core::Core() = default;
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Core::~Core() = default;
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void Core::Initialize() {}
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void Core::Reset()
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{
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m_regs = {};
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}
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bool Core::DoState(StateWrapper& sw)
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{
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sw.DoPOD(&m_regs);
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return !sw.HasError();
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}
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void Core::ExecuteInstruction(Instruction inst) {}
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} // namespace GTE
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@ -0,0 +1,32 @@
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#pragma once
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#include "common/state_wrapper.h"
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#include "gte_types.h"
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namespace GTE {
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class Core
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{
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public:
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Core();
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~Core();
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void Initialize();
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void Reset();
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bool DoState(StateWrapper& sw);
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u32 ReadRegister(u32 index) const { return m_regs.r32[index]; }
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void WriteRegister(u32 index, u32 value) { m_regs.r32[index] = value; }
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u32 ReadDataRegister(u32 index) const { return m_regs.r32[index]; }
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void WriteDataRegister(u32 index, u32 value) { m_regs.r32[index] = value; }
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u32 ReadControlRegister(u32 index) const { return m_regs.r32[index + 32]; }
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void WriteControlRegister(u32 index, u32 value) { m_regs.r32[index + 32] = value; }
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void ExecuteInstruction(Instruction inst);
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private:
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Regs m_regs = {};
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};
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} // namespace GTE
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@ -0,0 +1,103 @@
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#pragma once
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#include "common/bitfield.h"
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#include "types.h"
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namespace GTE {
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static constexpr u32 NUM_REGS = 64;
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union Regs
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{
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u32 r32[NUM_REGS];
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#pragma pack(push, 1)
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struct
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{
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s16 V0[3]; // 0-1
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u16 pad1; // 1
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s16 V1[3]; // 2-3
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u16 pad2; // 3
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s16 V2[3]; // 4-5
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u16 pad3; // 5
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u8 RGBC[4]; // 6
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u16 OTZ; // 7
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u16 pad4; // 7
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s16 IR0; // 8
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u16 pad5; // 8
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s16 IR1; // 9
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u16 pad6; // 9
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s16 IR2; // 10
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u16 pad7; // 10
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s16 IR3; // 11
|
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u16 pad8; // 11
|
||||
s16 SXY0; // 12
|
||||
u16 pad9; // 12
|
||||
s16 SXY1; // 13
|
||||
u16 pad10; // 13
|
||||
s16 SXY2; // 14
|
||||
u16 pad11; // 14
|
||||
s16 SXYP; // 15
|
||||
u16 pad12; // 15
|
||||
u16 SZ0; // 16
|
||||
u16 pad13; // 16
|
||||
u16 SZ1; // 17
|
||||
u16 pad14; // 17
|
||||
u16 SZ2; // 18
|
||||
u16 pad15; // 18
|
||||
u16 SZ3; // 19
|
||||
u16 pad16; // 19
|
||||
u32 RGB0; // 20
|
||||
u32 RGB1; // 21
|
||||
u32 RGB2; // 22
|
||||
u32 RES1; // 23
|
||||
s32 MAC0; // 24
|
||||
s32 MAC1; // 25
|
||||
s32 MAC2; // 26
|
||||
s32 MAC4; // 27
|
||||
u16 IRGB; // 28
|
||||
u16 ORGB; // 29
|
||||
s32 LZCS; // 30
|
||||
s32 LZCR; // 31
|
||||
u16 RT[3][3]; // 32-36
|
||||
u16 pad17; // 36
|
||||
s32 TR[3]; // 37-39
|
||||
u16 L[3][3]; // 40-44
|
||||
u16 pad18; // 44
|
||||
u32 RBK; // 45
|
||||
u32 GBK; // 46
|
||||
u32 BBK; // 47
|
||||
u16 LR[3][3]; // 48-52
|
||||
u16 pad19; // 52
|
||||
u32 RFC; // 53
|
||||
u32 GFC; // 54
|
||||
u32 BFC; // 55
|
||||
u32 OFX; // 56
|
||||
u32 OFY; // 57
|
||||
u16 H; // 58
|
||||
u16 pad20; // 58
|
||||
u16 DQA; // 59
|
||||
u16 pad21; // 59
|
||||
u32 DQB; // 60
|
||||
u16 ZSF3; // 61
|
||||
u16 pad22; // 61
|
||||
u16 ZSF4; // 62
|
||||
u16 pad23; // 62
|
||||
u32 FLAG; // 63
|
||||
};
|
||||
#pragma pack(pop)
|
||||
};
|
||||
static_assert(sizeof(Regs) == (sizeof(u32) * NUM_REGS));
|
||||
|
||||
union Instruction
|
||||
{
|
||||
u32 bits;
|
||||
|
||||
BitField<u32, u8, 20, 5> fake_command;
|
||||
BitField<u32, u8, 19, 1> sf; // shift fraction in IR registers, 0=no fraction, 1=12bit fraction
|
||||
BitField<u32, u8, 17, 2> mvmva_multiply_matrix;
|
||||
BitField<u32, u8, 15, 2> mvmva_multiply_vector;
|
||||
BitField<u32, u8, 13, 2> mvmva_translation_vector;
|
||||
BitField<u32, bool, 10, 1> lm; // saturate IR1, IR2, IR3 result
|
||||
BitField<u32, u8, 0, 6> command;
|
||||
};
|
||||
|
||||
} // namespace GTE
|
|
@ -39,6 +39,7 @@
|
|||
<ClCompile Include="cdrom.cpp" />
|
||||
<ClCompile Include="cpu_core.cpp" />
|
||||
<ClCompile Include="cpu_disasm.cpp" />
|
||||
<ClCompile Include="gte.cpp" />
|
||||
<ClCompile Include="dma.cpp" />
|
||||
<ClCompile Include="gpu.cpp" />
|
||||
<ClCompile Include="gpu_hw.cpp" />
|
||||
|
@ -52,11 +53,13 @@
|
|||
<ClInclude Include="cdrom.h" />
|
||||
<ClInclude Include="cpu_core.h" />
|
||||
<ClInclude Include="cpu_disasm.h" />
|
||||
<ClInclude Include="gte.h" />
|
||||
<ClInclude Include="cpu_types.h" />
|
||||
<ClInclude Include="dma.h" />
|
||||
<ClInclude Include="gpu.h" />
|
||||
<ClInclude Include="gpu_hw.h" />
|
||||
<ClInclude Include="gpu_hw_opengl.h" />
|
||||
<ClInclude Include="gte_types.h" />
|
||||
<ClInclude Include="host_interface.h" />
|
||||
<ClInclude Include="interrupt_controller.h" />
|
||||
<ClInclude Include="save_state_version.h" />
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
<ClCompile Include="host_interface.cpp" />
|
||||
<ClCompile Include="interrupt_controller.cpp" />
|
||||
<ClCompile Include="cdrom.cpp" />
|
||||
<ClCompile Include="gte.cpp" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="types.h" />
|
||||
|
@ -28,6 +29,8 @@
|
|||
<ClInclude Include="host_interface.h" />
|
||||
<ClInclude Include="interrupt_controller.h" />
|
||||
<ClInclude Include="cdrom.h" />
|
||||
<ClInclude Include="gte.h" />
|
||||
<ClInclude Include="gte_types.h" />
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<None Include="cpu_core.inl" />
|
||||
|
|
Loading…
Reference in New Issue