CPU: Refactoring, implement LWC/SWC
This commit is contained in:
Connor McLaughlin
parent
2875a22987
commit
948ac50020
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@ -283,6 +283,117 @@ void Core::WriteRegDelayed(Reg rd, u32 value)
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m_regs.r[static_cast<u8>(rd)] = value;
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}
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u32 Core::ReadCop0Reg(Cop0Reg reg)
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{
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switch (reg)
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{
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case Cop0Reg::BPC:
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return m_cop0_regs.BPC;
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case Cop0Reg::BPCM:
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return m_cop0_regs.BPCM;
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case Cop0Reg::BDA:
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return m_cop0_regs.BDA;
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case Cop0Reg::BDAM:
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return m_cop0_regs.BDAM;
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case Cop0Reg::DCIC:
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return m_cop0_regs.dcic.bits;
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case Cop0Reg::JUMPDEST:
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return m_cop0_regs.JUMPDEST;
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case Cop0Reg::BadVaddr:
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return m_cop0_regs.BadVaddr;
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case Cop0Reg::SR:
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return m_cop0_regs.sr.bits;
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case Cop0Reg::CAUSE:
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return m_cop0_regs.cause.bits;
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case Cop0Reg::EPC:
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return m_cop0_regs.EPC;
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case Cop0Reg::PRID:
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return m_cop0_regs.PRID;
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default:
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Panic("Unknown COP0 reg");
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return 0;
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}
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}
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void Core::WriteCop0Reg(Cop0Reg reg, u32 value)
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{
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switch (reg)
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{
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case Cop0Reg::BPC:
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{
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m_cop0_regs.BPC = value;
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Log_WarningPrintf("COP0 BPC <- %08X", value);
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}
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break;
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case Cop0Reg::BPCM:
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{
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m_cop0_regs.BPCM = value;
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Log_WarningPrintf("COP0 BPCM <- %08X", value);
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}
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break;
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case Cop0Reg::BDA:
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{
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m_cop0_regs.BDA = value;
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Log_WarningPrintf("COP0 BDA <- %08X", value);
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}
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break;
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case Cop0Reg::BDAM:
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{
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m_cop0_regs.BDAM = value;
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Log_WarningPrintf("COP0 BDAM <- %08X", value);
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}
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break;
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case Cop0Reg::JUMPDEST:
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{
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Log_WarningPrintf("Ignoring write to Cop0 JUMPDEST");
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}
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break;
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case Cop0Reg::DCIC:
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{
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m_cop0_regs.dcic.bits =
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(m_cop0_regs.dcic.bits & ~Cop0Registers::DCIC::WRITE_MASK) | (value & Cop0Registers::DCIC::WRITE_MASK);
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Log_WarningPrintf("COP0 DCIC <- %08X (now %08X)", value, m_cop0_regs.dcic.bits);
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}
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break;
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case Cop0Reg::SR:
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{
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m_cop0_regs.sr.bits =
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(m_cop0_regs.sr.bits & ~Cop0Registers::SR::WRITE_MASK) | (value & Cop0Registers::SR::WRITE_MASK);
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Log_WarningPrintf("COP0 SR <- %08X (now %08X)", value, m_cop0_regs.sr.bits);
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}
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break;
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case Cop0Reg::CAUSE:
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{
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m_cop0_regs.cause.bits =
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(m_cop0_regs.cause.bits & ~Cop0Registers::CAUSE::WRITE_MASK) | (value & Cop0Registers::CAUSE::WRITE_MASK);
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Log_WarningPrintf("COP0 CAUSE <- %08X (now %08X)", value, m_cop0_regs.cause.bits);
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}
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break;
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default:
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Panic("Unknown COP0 reg");
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break;
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}
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}
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void Core::WriteCacheControl(u32 value)
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{
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Log_WarningPrintf("Cache control <- 0x%08X", value);
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@ -895,7 +1006,7 @@ void Core::ExecuteInstruction(Instruction inst)
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case InstructionOp::cop0:
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{
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if (!m_cop0_regs.sr.CU0 && InUserMode())
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if (InUserMode() && !m_cop0_regs.sr.CU0)
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{
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Log_WarningPrintf("Coprocessor 0 not present in user mode");
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RaiseException(Exception::CpU, 0);
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@ -908,7 +1019,7 @@ void Core::ExecuteInstruction(Instruction inst)
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case InstructionOp::cop2:
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{
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if (!m_cop0_regs.sr.CU0 && InUserMode())
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if (InUserMode() && !m_cop0_regs.sr.CU2)
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{
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Log_WarningPrintf("Coprocessor 2 not present in user mode");
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RaiseException(Exception::CpU, 2);
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@ -919,9 +1030,46 @@ void Core::ExecuteInstruction(Instruction inst)
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}
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break;
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case InstructionOp::lwc2:
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{
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if (InUserMode() && !m_cop0_regs.sr.CU2)
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{
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Log_WarningPrintf("Coprocessor 2 not present in user mode");
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RaiseException(Exception::CpU, 2);
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return;
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}
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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u32 value;
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if (!ReadMemoryWord(addr, &value))
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return;
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m_cop2.WriteDataRegister(ZeroExtend32(static_cast<u8>(inst.i.rt.GetValue())), value);
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}
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break;
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case InstructionOp::swc2:
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{
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if (InUserMode() && !m_cop0_regs.sr.CU2)
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{
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Log_WarningPrintf("Coprocessor 2 not present in user mode");
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RaiseException(Exception::CpU, 2);
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return;
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}
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const VirtualMemoryAddress addr = ReadReg(inst.i.rs) + inst.i.imm_sext32();
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const u32 value = m_cop2.ReadDataRegister(ZeroExtend32(static_cast<u8>(inst.i.rt.GetValue())));
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WriteMemoryWord(addr, value);
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}
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break;
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// COP1/COP3 are not present
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case InstructionOp::cop1:
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case InstructionOp::cop3:
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case InstructionOp::lwc1:
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case InstructionOp::swc1:
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case InstructionOp::lwc3:
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case InstructionOp::swc3:
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{
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RaiseException(Exception::CpU, inst.cop.cop_n);
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}
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@ -935,147 +1083,38 @@ void Core::ExecuteInstruction(Instruction inst)
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void Core::ExecuteCop0Instruction(Instruction inst)
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{
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switch (inst.cop.cop0_op())
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if (inst.cop.IsCommonInstruction())
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{
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case Cop0Instruction::mtc0:
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switch (inst.cop.CommonOp())
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{
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const u32 value = ReadReg(inst.r.rt);
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switch (static_cast<Cop0Reg>(inst.r.rd.GetValue()))
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case CopCommonInstruction::mfcn:
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WriteRegDelayed(inst.r.rt, ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue())));
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break;
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case CopCommonInstruction::mtcn:
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WriteCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()), ReadReg(inst.r.rt));
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break;
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default:
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Panic("Missing implementation");
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break;
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}
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}
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else
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{
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switch (inst.cop.Cop0Op())
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{
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case Cop0Instruction::rfe:
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{
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case Cop0Reg::BPC:
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{
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m_cop0_regs.BPC = value;
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Log_WarningPrintf("COP0 BPC <- %08X", value);
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}
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break;
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case Cop0Reg::BPCM:
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{
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m_cop0_regs.BPCM = value;
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Log_WarningPrintf("COP0 BPCM <- %08X", value);
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}
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break;
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case Cop0Reg::BDA:
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{
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m_cop0_regs.BDA = value;
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Log_WarningPrintf("COP0 BDA <- %08X", value);
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}
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break;
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case Cop0Reg::BDAM:
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{
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m_cop0_regs.BDAM = value;
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Log_WarningPrintf("COP0 BDAM <- %08X", value);
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}
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break;
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case Cop0Reg::JUMPDEST:
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{
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Log_WarningPrintf("Ignoring write to Cop0 JUMPDEST");
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}
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break;
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case Cop0Reg::DCIC:
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{
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m_cop0_regs.dcic.bits =
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(m_cop0_regs.dcic.bits & ~Cop0Registers::DCIC::WRITE_MASK) | (value & Cop0Registers::DCIC::WRITE_MASK);
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Log_WarningPrintf("COP0 DCIC <- %08X (now %08X)", value, m_cop0_regs.dcic.bits);
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}
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break;
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case Cop0Reg::SR:
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{
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m_cop0_regs.sr.bits =
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(m_cop0_regs.sr.bits & ~Cop0Registers::SR::WRITE_MASK) | (value & Cop0Registers::SR::WRITE_MASK);
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Log_WarningPrintf("COP0 SR <- %08X (now %08X)", value, m_cop0_regs.sr.bits);
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}
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break;
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case Cop0Reg::CAUSE:
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{
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m_cop0_regs.cause.bits =
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(m_cop0_regs.cause.bits & ~Cop0Registers::CAUSE::WRITE_MASK) | (value & Cop0Registers::CAUSE::WRITE_MASK);
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Log_WarningPrintf("COP0 CAUSE <- %08X (now %08X)", value, m_cop0_regs.cause.bits);
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}
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break;
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default:
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Panic("Unknown COP0 reg");
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break;
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// restore mode
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m_cop0_regs.sr.mode_bits = (m_cop0_regs.sr.mode_bits & UINT32_C(0b110000)) | (m_cop0_regs.sr.mode_bits >> 2);
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}
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}
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break;
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case Cop0Instruction::mfc0:
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{
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u32 value;
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switch (static_cast<Cop0Reg>(inst.r.rd.GetValue()))
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{
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case Cop0Reg::BPC:
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value = m_cop0_regs.BPC;
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break;
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case Cop0Reg::BPCM:
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value = m_cop0_regs.BPCM;
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break;
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case Cop0Reg::BDA:
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value = m_cop0_regs.BDA;
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break;
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case Cop0Reg::BDAM:
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value = m_cop0_regs.BDAM;
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break;
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case Cop0Reg::DCIC:
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value = m_cop0_regs.dcic.bits;
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break;
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case Cop0Reg::JUMPDEST:
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value = m_cop0_regs.JUMPDEST;
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break;
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case Cop0Reg::BadVaddr:
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value = m_cop0_regs.BadVaddr;
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break;
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case Cop0Reg::SR:
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value = m_cop0_regs.sr.bits;
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break;
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case Cop0Reg::CAUSE:
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value = m_cop0_regs.cause.bits;
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break;
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case Cop0Reg::EPC:
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value = m_cop0_regs.EPC;
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break;
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case Cop0Reg::PRID:
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value = m_cop0_regs.PRID;
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break;
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default:
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Panic("Unknown COP0 reg");
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value = 0;
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break;
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}
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WriteRegDelayed(inst.r.rt, value);
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}
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break;
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case Cop0Instruction::rfe:
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{
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// restore mode
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m_cop0_regs.sr.mode_bits = (m_cop0_regs.sr.mode_bits & UINT32_C(0b110000)) | (m_cop0_regs.sr.mode_bits >> 2);
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}
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break;
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default:
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Panic("Unhandled instruction");
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break;
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default:
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Panic("Missing implementation");
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break;
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}
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}
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}
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@ -1084,20 +1123,25 @@ void Core::ExecuteCop2Instruction(Instruction inst)
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if (inst.cop.IsCommonInstruction())
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{
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// TODO: Combine with cop0.
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switch (inst.cop.cop2_op())
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switch (inst.cop.CommonOp())
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{
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case Cop2Instruction::mfc2:
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case Cop2Instruction::cfc2:
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case Cop2Instruction::mtc2:
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case Cop2Instruction::ctc2:
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{
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const u32 index = static_cast<u32>(inst.r.rd.GetValue());
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const u32 value = ReadReg(inst.r.rt);
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m_cop2.WriteControlRegister(index, value);
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}
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break;
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case CopCommonInstruction::cfcn:
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WriteRegDelayed(inst.r.rt, m_cop2.ReadControlRegister(static_cast<u32>(inst.r.rd.GetValue())));
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break;
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case Cop2Instruction::bc2c:
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case CopCommonInstruction::ctcn:
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m_cop2.WriteControlRegister(static_cast<u32>(inst.r.rd.GetValue()), ReadReg(inst.r.rt));
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break;
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case CopCommonInstruction::mfcn:
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WriteRegDelayed(inst.r.rt, m_cop2.ReadDataRegister(static_cast<u32>(inst.r.rd.GetValue())));
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break;
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case CopCommonInstruction::mtcn:
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m_cop2.WriteDataRegister(static_cast<u32>(inst.r.rd.GetValue()), ReadReg(inst.r.rt));
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break;
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case CopCommonInstruction::bcnc:
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default:
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Panic("Missing implementation");
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break;
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@ -103,6 +103,10 @@ private:
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// write to cache control register
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void WriteCacheControl(u32 value);
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// read/write cop0 regs
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u32 ReadCop0Reg(Cop0Reg reg);
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void WriteCop0Reg(Cop0Reg reg, u32 value);
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Bus* m_bus = nullptr;
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// ticks the CPU has executed
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@ -160,20 +160,14 @@ static const std::array<const char*, 64> s_special_table = {{
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"UNKNOWN" // 63
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}};
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static const std::array<std::pair<Cop0Instruction, const char*>, 6> s_cop0_table = {
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{{Cop0Instruction::mfc0, "mfc0 $rt, $coprd"},
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{Cop0Instruction::cfc0, "cfc0 $rt, $copcr"},
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{Cop0Instruction::mtc0, "mtc0 $rt, $coprd"},
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{Cop0Instruction::ctc0, "ctc0 $rt, $copcr"},
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{Cop0Instruction::bc0c, "bc0$copcc $rel"},
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{Cop0Instruction::rfe, "rfe"}}};
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static const std::array<std::pair<CopCommonInstruction, const char*>, 5> s_cop_common_table = {
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{{CopCommonInstruction::mfcn, "mfc$cop $rt, $coprd"},
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{CopCommonInstruction::cfcn, "cfc$cop $rt, $copcr"},
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{CopCommonInstruction::mtcn, "mtc$cop $rt, $coprd"},
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{CopCommonInstruction::ctcn, "ctc$cop $rt, $copcr"},
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{CopCommonInstruction::bcnc, "bc$cop$copcc $rel"}}};
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static const std::array<std::pair<Cop2Instruction, const char*>, 6> s_cop2_common_table = {
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{{Cop2Instruction::mfc2, "mfc2 $rt, $coprd"},
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{Cop2Instruction::cfc2, "cfc2 $rt, $copcr"},
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{Cop2Instruction::mtc2, "mtc2 $rt, $coprd"},
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{Cop2Instruction::ctc2, "ctc2 $rt, $copcr"},
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{Cop2Instruction::bc2c, "bc2$copcc $rel"}}};
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static const std::array<std::pair<Cop0Instruction, const char*>, 1> s_cop0_table = {{{Cop0Instruction::rfe, "rfe"}}};
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static void FormatInstruction(String* dest, const Instruction inst, u32 pc, const char* format)
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{
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@ -286,28 +280,37 @@ void DisassembleInstruction(String* dest, u32 pc, u32 bits)
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return;
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case InstructionOp::cop0:
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FormatCopInstruction(dest, pc, inst, s_cop0_table.data(), s_cop0_table.size(), inst.cop.cop0_op());
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return;
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case InstructionOp::cop1:
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case InstructionOp::cop2:
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case InstructionOp::cop3:
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{
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if (inst.cop.IsCommonInstruction())
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{
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FormatCopInstruction(dest, pc, inst, s_cop2_common_table.data(), s_cop2_common_table.size(),
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inst.cop.cop2_op());
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FormatCopInstruction(dest, pc, inst, s_cop_common_table.data(), s_cop_common_table.size(), inst.cop.CommonOp());
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}
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else
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{
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dest->Format("<cop%u 0x%08X>", ZeroExtend32(inst.cop.cop_n.GetValue()), inst.cop.imm25.GetValue());
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switch (inst.op)
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{
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case InstructionOp::cop0:
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{
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FormatCopInstruction(dest, pc, inst, s_cop0_table.data(), s_cop0_table.size(), inst.cop.Cop0Op());
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}
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break;
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case InstructionOp::cop1:
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case InstructionOp::cop2:
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case InstructionOp::cop3:
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default:
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{
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dest->Format("<cop%u 0x%08X>", ZeroExtend32(inst.cop.cop_n.GetValue()), inst.cop.imm25.GetValue());
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}
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break;
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}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case InstructionOp::cop1:
|
||||
case InstructionOp::cop3:
|
||||
dest->Format("<cop%u 0x%08X>", ZeroExtend32(inst.cop.cop_n.GetValue()), inst.cop.imm25.GetValue());
|
||||
break;
|
||||
|
||||
// special case for bltz/bgez{al}
|
||||
case InstructionOp::b:
|
||||
{
|
||||
|
|
|
|||
|
|
@ -74,7 +74,15 @@ enum class InstructionOp : u8
|
|||
sh = 41,
|
||||
swl = 42,
|
||||
sw = 43,
|
||||
swr = 46
|
||||
swr = 46,
|
||||
lwc0 = 48,
|
||||
lwc1 = 49,
|
||||
lwc2 = 50,
|
||||
lwc3 = 51,
|
||||
swc0 = 56,
|
||||
swc1 = 57,
|
||||
swc2 = 58,
|
||||
swc3 = 59,
|
||||
};
|
||||
constexpr u8 INSTRUCTION_COP_BITS = 0x10;
|
||||
constexpr u8 INSTRUCTION_COP_MASK = 0x3C;
|
||||
|
|
@ -113,27 +121,22 @@ enum class InstructionFunct : u8
|
|||
sltu = 43
|
||||
};
|
||||
|
||||
enum class Cop0Instruction : u32 // 25:21 | 0:5
|
||||
enum class CopCommonInstruction : u32
|
||||
{
|
||||
mfc0 = 0b00000'000000,
|
||||
cfc0 = 0b00010'000000,
|
||||
mtc0 = 0b00100'000000,
|
||||
ctc0 = 0b00110'000000,
|
||||
bc0c = 0b01000'000000,
|
||||
tlbr = 0b10000'000001,
|
||||
tlbwi = 0b10000'000010,
|
||||
tlbwr = 0b10000'000100,
|
||||
tlbp = 0b10000'001000,
|
||||
rfe = 0b10000'010000,
|
||||
mfcn = 0b0000,
|
||||
cfcn = 0b0010,
|
||||
mtcn = 0b0100,
|
||||
ctcn = 0b0110,
|
||||
bcnc = 0b1000,
|
||||
};
|
||||
|
||||
enum class Cop2Instruction : u32 // 25:21
|
||||
enum class Cop0Instruction : u32
|
||||
{
|
||||
mfc2 = 0b0000,
|
||||
cfc2 = 0b0010,
|
||||
mtc2 = 0b0100,
|
||||
ctc2 = 0b0110,
|
||||
bc2c = 0b1000,
|
||||
tlbr = 0x01,
|
||||
tlbwi = 0x02,
|
||||
tlbwr = 0x04,
|
||||
tlbp = 0x08,
|
||||
rfe = 0x10,
|
||||
};
|
||||
|
||||
union Instruction
|
||||
|
|
@ -175,15 +178,9 @@ union Instruction
|
|||
|
||||
bool IsCommonInstruction() const { return (bits & (UINT32_C(1) << 25)) == 0; }
|
||||
|
||||
Cop0Instruction cop0_op() const
|
||||
{
|
||||
return static_cast<Cop0Instruction>(((bits >> 15) & UINT32_C(0b11111000000)) | (bits & UINT32_C(0b111111)));
|
||||
}
|
||||
CopCommonInstruction CommonOp() const { return static_cast<CopCommonInstruction>((bits >> 21) & UINT32_C(0b1111)); }
|
||||
|
||||
Cop2Instruction cop2_op() const
|
||||
{
|
||||
return static_cast<Cop2Instruction>((bits >> 21) & UINT32_C(0b1111));
|
||||
}
|
||||
Cop0Instruction Cop0Op() const { return static_cast<Cop0Instruction>(bits & UINT32_C(0x3F)); }
|
||||
} cop;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue