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14575 Commits

Author SHA1 Message Date
SaxxonPike e8902b829a C64: Apparently the 6502X core needs interrupts delayed by a cycle, do that with IRQ and NMI 2019-07-14 10:43:52 -05:00
SaxxonPike 3bbfb98fc2 C64: Split out VIC IRQ delays 2019-07-13 19:28:44 -05:00
SaxxonPike 154eefd2ad C64: Give BA/IRQ counting another go, seems to resolve many issues 2019-07-13 16:51:30 -05:00
SaxxonPike db38d5e65b C64: Try counting IRQ and BA correctly 2019-07-13 15:28:57 -05:00
SaxxonPike f22c9b7abd C64: CPU reads open bus when !AEC is asserted 2019-07-13 15:25:40 -05:00
SaxxonPike 894adbb610 C64: Remove an unused variable 2019-07-13 15:02:18 -05:00
SaxxonPike 76679bc8bc C64: Use the correct background color in bitmapped modes for 0 2019-07-13 15:01:11 -05:00
SaxxonPike bd20b355f0 C64: Writing to CPU port writes open bus data to 00/01 2019-07-13 14:06:23 -05:00
SaxxonPike f18e7c8833 C64: Make the system debuggable for once 2019-07-13 13:15:50 -05:00
SaxxonPike cae3340946 C64: No need to expose these with the CPU link in place 2019-07-13 12:53:34 -05:00
SaxxonPike 3369dbf43f C64: IRQ is implemented as a delay line; no delay added (yet) 2019-07-13 12:51:39 -05:00
SaxxonPike d39f3e2e61 6502X: pending IRQs are not delayed when !RDY is asserted 2019-07-13 12:31:09 -05:00
SaxxonPike bf2cba0e23 6502X: remove a comment (this is indeed a dummy fetch) 2019-07-13 11:38:03 -05:00
SaxxonPike d62f2ac3fe C64: 0F7 is a badline eligible raster (fixes 26-line text demo in Frodo test suite) 2019-07-13 01:41:58 -05:00
SaxxonPike e6871b2cc3 C64: Move VIC raster IRQ to phase 1 2019-07-13 00:27:08 -05:00
SaxxonPike dbf6b39e7f C64: Split out VIC phase1/phase2 2019-07-12 23:51:55 -05:00
SaxxonPike 85bc92b688 Merge remote-tracking branch 'origin/c64-refactor' into c64-refactor 
# Conflicts:
#	BizHawk.Emulation.Cores/Computers/Commodore64/MOS/Chip6510.cs
 2019-07-12 22:10:08 -05:00
SaxxonPike 0a7dc52aa0 C64: BA and raster IRQ cleanup 2019-07-09 22:41:12 -05:00
SaxxonPike 3a135c7c26 C64: Raster interrupt bit can be set even if not enabled, just won't actually assert IRQ 2019-07-09 21:40:03 -05:00
SaxxonPike e63d10b608 C64: Interrupts generated in phase 2 by the VIC won't trigger for the CPU until next cycle, also buffer BA 2019-07-09 20:55:14 -05:00
SaxxonPike b471fdc692 C64: The CPU can trigger VIC badlines on its own (needed for VSP) 2019-07-09 20:53:54 -05:00
SaxxonPike 2abe832289 C64: AEC does not prohibit the CPU from functioning, only BA (RDY) does 2019-07-09 20:52:51 -05:00
SaxxonPike 9758efe604 6502X: CPU does a read or write regardless if the result is trashed, even during reset and dummy pushes 2019-07-09 19:46:33 -05:00
SaxxonPike a8fd85157c VIC: Use correct color mapping for non-multicolor bitmap mode 2019-07-09 08:02:55 -05:00
SaxxonPike 83b6553749 VIC: Respect idle state background color registers, plus black in undocumented gfx mode 2019-07-09 06:58:13 -05:00
SaxxonPike 89fa153477 VIC: Resolve background color registers separately to color matrix memory 2019-07-09 06:55:55 -05:00
SaxxonPike 9f733d3e7a VIC: More accurate pixel pipeline 2019-07-09 05:26:26 -05:00
SaxxonPike 3efea15038 6502X: When !RDY is asserted, still do other operations. Plus, do dummy reads on stack ops 2019-07-09 05:24:47 -05:00
SaxxonPike d36e02045b C64: Optimize the RNG for 1541 flux transitions. (same output) 2019-07-06 16:32:21 -05:00
SaxxonPike 3bf37f1c17 C64: No need for LagCycles anymore. 2019-07-06 16:29:14 -05:00
SaxxonPike 6ed11de85b C64: Soft/Hard reset: it's about time 2019-07-06 01:19:58 -05:00
SaxxonPike d48964b642 6502X: According to the datasheet, RDY must be high in order for interrupts to trigger 
- this has implications for C64, as it may cause VIC interrupts to fire quite later than they currently do
 2019-07-06 00:00:51 -05:00
SaxxonPike 400b04b690 C64: CIA was sometimes delaying too long to fire interrupts by 1 cycle. 
- This could have implications for existing TASes (!)
 2019-07-05 23:59:01 -05:00
SaxxonPike 69f8b143a3 C64: Foreground pixels are black when VIC is in idle state. 2019-07-05 21:05:38 -05:00
SaxxonPike 8698aa41be Merge branch 'master' into c64-refactor 2019-07-05 20:14:28 -05:00
alyosha-tas 9cbc78778f Vectrex: interrupt fixes 2019-07-05 20:25:03 -04:00
alyosha-tas 6a5fc8b47e Vectrex: Implement interrupts, fixes Bedlam 2019-07-05 19:57:55 -04:00
alyosha-tas b0123ea133 Vectrex: fix control stick in some cases 2019-07-05 17:16:11 -04:00
alyosha-tas e9ca6f82bc Trace Logger: Fix exception when scrolling 2019-07-05 10:06:00 -04:00
alyosha-tas 275ccb381a Vectrex: ramp overscan more accurate, fixes numerous display bugs 2019-07-04 21:26:13 -04:00
alyosha-tas 9b2d926bc0 Vectrex: working controllers 2019-07-04 20:00:59 -04:00
SaxxonPike 49b613962e C64: Fix a typo disabling voice 3 when high pass filter is set 2019-07-04 17:32:35 -05:00
SaxxonPike f45e934fec C64: Reset the SID filter on hard reset. 2019-07-04 17:24:22 -05:00
SaxxonPike 579ffe5c25 C64: Had the flag with the wrong polarity. Thanks, C64Anabalt. 2019-07-04 14:20:12 -05:00
SaxxonPike 691577499f C64: When a sprite is eligible for display, initialize it with the correct crunch state based on Y expansion 2019-07-04 14:12:46 -05:00
SaxxonPike 36ac592193 C64: Individual IRQ flags for S/S or S/D collisions are always set even if not eligible to assert IRQ externally 2019-07-04 13:59:41 -05:00
SaxxonPike 5c9445fb96 C64: Reuse some local memory in the sprite renderer. 2019-07-04 12:47:09 -05:00
SaxxonPike 55145ff7ba C64: The T64 format was never supported, but at least make the core aware of it 2019-07-04 12:46:28 -05:00
SaxxonPike 2c804cab34 C64: Fix a function ambiguity in the CIA class. 2019-07-04 00:51:19 -05:00
SaxxonPike 2dd80eb0f4 C64: Implement more CIA features and CIA/VIA defaults. 2019-07-04 00:31:48 -05:00