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Vectrex: interrupt fixes

This commit is contained in:
alyosha-tas 2019-07-05 20:25:03 -04:00
parent 6a5fc8b47e
commit 9cbc78778f
3 changed files with 8 additions and 5 deletions
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6
BizHawk.Emulation.Cores/CPUs/MC6809/Interrupts.cs
View File

@ -8,7 +8,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
{
Regs[ADDR] = 0xFFF8;
PopulateCURINSTR(IDLE,
IDLE,
SET_E,
DEC16, SP,
WR_DEC_LO, SP, PC,
WR_DEC_HI, SP, PC,
@ -34,7 +34,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
{
Regs[ADDR] = 0xFFF6;
PopulateCURINSTR(IDLE,
IDLE,
CLR_E,
DEC16, SP,
WR_DEC_LO, SP, PC,
WR_DEC_HI, SP, PC,
@ -51,7 +51,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
{
Regs[ADDR] = 0xFFFC;
PopulateCURINSTR(IDLE,
IDLE,
SET_E,
DEC16, SP,
WR_DEC_LO, SP, PC,
WR_DEC_HI, SP, PC,

4
BizHawk.Emulation.Cores/CPUs/MC6809/MC6809.cs
View File

@ -78,6 +78,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
public const ushort LD_8 = 67;
public const ushort LD_16 = 68;
public const ushort LEA = 69;
public const ushort CLR_E = 70;
public MC6809()
{
@ -360,6 +361,9 @@ namespace BizHawk.Emulation.Common.Components.MC6809
case SET_E:
FlagE = true;
break;
case CLR_E:
FlagE = false;
break;
case ANDCC:
Regs[CC] &= Regs[instr_pntr++];
break;

3
BizHawk.Emulation.Cores/CPUs/MC6809/OP_Tables.cs
View File

@ -472,8 +472,7 @@ namespace BizHawk.Emulation.Common.Components.MC6809
RD_INC, ALU, SP,
RD_INC_OP, ALU2, SP, SET_ADDR, US, ALU, ALU2,
RD_INC, ALU, SP,
RD_INC_OP, ALU2, SP,
SET_ADDR, PC, ALU, ALU2);
RD_INC_OP, ALU2, SP, SET_ADDR, PC, ALU, ALU2);
IRQS = 14;
}