zilmar
|
479e2e518c
|
Core: Syscall should increment cycle count
|
2022-09-05 20:00:28 +09:30 |
|
zilmar
|
c380571d8b
|
Core: Update when branch goes to the opcode after the delay slot
|
2022-09-05 19:42:22 +09:30 |
|
zilmar
|
17b78bc705
|
Core: Clean up CExitInfo::EXIT_REASON enum
|
2022-09-05 17:42:41 +09:30 |
|
zilmar
|
18b9892bc7
|
Core: Add handling of overflow exception
|
2022-09-05 16:35:13 +09:30 |
|
zilmar
|
7d55fdca37
|
Core: Fix bug in CX86RegInfo::FreeX86Reg where x86RegIndex_Size was introduced
|
2022-09-05 10:42:49 +09:30 |
|
zilmar
|
a5c6f25ee3
|
Core: CX86RecompilerOps::BaseOffsetAddress should not unprotect unless it actually protected
|
2022-09-05 10:41:18 +09:30 |
|
zilmar
|
f7b1891c91
|
Core: Add base 64bit Recompiler classes
|
2022-08-29 17:57:17 +09:30 |
|
zilmar
|
d82a370e59
|
Core: Create a x86RegIndex enum
|
2022-08-29 11:49:20 +09:30 |
|
zilmar
|
b88a1ccc1e
|
Core: Fix bug in div for recompiler
|
2022-08-29 08:33:13 +09:30 |
|
zilmar
|
6782599687
|
Core: Create a x86 call for calling this functions
|
2022-08-29 08:32:02 +09:30 |
|
zilmar
|
52a30b78fb
|
Core: Handle div/0 better
|
2022-08-22 22:13:53 +09:30 |
|
zilmar
|
f3a392489a
|
Core: Do not fail on checking delay slot, if it is invalid memory
|
2022-08-22 13:02:25 +09:30 |
|
zilmar
|
9b16d29792
|
Core: Add rom write decay and some code clean up
|
2022-08-22 12:47:44 +09:30 |
|
zilmar
|
3e198d04a8
|
core: change CX86RecompilerOps to have a variable for CX86Ops instead of inheriting it
|
2022-08-15 12:39:34 +09:30 |
|
zilmar
|
e724595ac2
|
Core: Add DADDI
|
2022-08-15 10:05:16 +09:30 |
|
zilmar
|
51c9867e76
|
Core: Get the recompiler to be use globals less
|
2022-08-08 20:22:51 +09:30 |
|
zilmar
|
7b851e6b6e
|
Core: Break on unhandled memory
|
2022-08-01 10:00:07 +09:30 |
|
zilmar
|
c59a0efcab
|
Core: fix LB_KnownAddress for reading rom
|
2022-07-25 17:22:47 +09:30 |
|
zilmar
|
09b535551d
|
Core: Move DelaySlotEffectsCompare into R4300iInstruction
|
2022-07-25 16:35:42 +09:30 |
|
zilmar
|
15466b6a9b
|
Core: Fix unaligned rom access with LH/LB
|
2022-07-25 14:08:09 +09:30 |
|
zilmar
|
7f3b8e3601
|
Core: Start to add R4300iInstruction to do analysis of an opcode
|
2022-07-18 18:01:00 +09:30 |
|
zilmar
|
47e27b591c
|
Android: Fix some compile issues
|
2022-07-11 13:39:57 +09:30 |
|
zilmar
|
079e493728
|
Core: Improve PI Dma
|
2022-07-04 17:14:27 +09:30 |
|
zilmar
|
3913fb5c28
|
Core: Improve accuracy of SP_DMA_READ and SP_DMA_WRITE
|
2022-06-20 14:21:32 +09:30 |
|
zilmar
|
837e93d775
|
Core: Move PI_DMA_READ & PI_DMA_WRITE into PeripheralInterfaceHandler
|
2022-06-20 09:10:01 +09:30 |
|
zilmar
|
cec55c7fd9
|
Core: clean up some read/writes to SP register for recompiler
|
2022-06-13 15:44:07 +09:30 |
|
zilmar
|
81b52143ca
|
Core: CX86RecompilerOps::CompileLoadMemoryValue should not minus count any more
|
2022-06-13 14:23:31 +09:30 |
|
zilmar
|
b557dcf187
|
Android: Do some work to try to get it to build
|
2022-06-06 19:49:44 +09:30 |
|
zilmar
|
d83f90f2d2
|
Core: Have store/load use non memory functions
|
2022-06-06 12:01:47 +09:30 |
|
zilmar
|
8f1f7e9cf3
|
core: move add opcode count from pre to post op for recompiler
|
2022-06-06 11:53:31 +09:30 |
|
zilmar
|
dc106c0df8
|
Core: Start to add store instruction self mod
|
2022-06-06 11:41:09 +09:30 |
|
zilmar
|
603ed853bc
|
Core: Some code clean up for load/store non memory
|
2022-05-30 20:20:25 +09:30 |
|
zilmar
|
535de2ad49
|
Core: Modularize Load Memory Value
|
2022-05-23 16:20:13 +09:30 |
|
zilmar
|
17a7f31bc2
|
Core: allow CompileStoreMemoryValue to generate address
|
2022-05-23 07:14:26 +09:30 |
|
zilmar
|
068fad47e5
|
Core: remove Compile_StoreInstructClean
|
2022-05-23 06:52:31 +09:30 |
|
zilmar
|
cc0c139f7e
|
Core: modularize store memory values using CompileStoreMemoryValue
|
2022-05-23 06:24:56 +09:30 |
|
zilmar
|
f95c0f7ef1
|
Core: Fix bug in SDC1
|
2022-05-20 10:32:15 +09:30 |
|
zilmar
|
1b871fcb15
|
Core: x86RecompilerOps rename m_TempValue to m_TempValue32
|
2022-05-16 15:51:37 +09:30 |
|
zilmar
|
7fb67450a1
|
Core: X86 recompile modularize loading address in store/load ops
|
2022-05-16 11:01:18 +09:30 |
|
zilmar
|
718d7e0359
|
[Core] Clean up load/store usage in MemoryVirtualMem
|
2022-05-09 10:06:10 +09:30 |
|
zilmar
|
5a49331c0b
|
Core: Direct tlb method to read and write to memory
|
2022-05-02 20:22:31 +09:30 |
|
zilmar
|
bac3517c86
|
[Core] Change tlb empty to be -1 and remove rdram from tlb value
|
2022-05-02 19:10:35 +09:30 |
|
zilmar
|
b74a2dc69f
|
[Core] Change TranslateVaddr to VAddrToPAddr
|
2022-05-02 07:36:50 +09:30 |
|
zilmar
|
2f1074a287
|
Core: Add handler for cartridge domains
|
2022-04-25 17:12:07 +09:30 |
|
zilmar
|
653e15a296
|
Core: Add RomMemoryHandler
|
2022-04-18 20:57:59 +09:30 |
|
zilmar
|
f683d080ed
|
[Core] CX86RecompilerOps::SW always update counters on unknown addresses
|
2022-04-11 09:07:47 +09:30 |
|
zilmar
|
fbf65bce12
|
Core: Add a look up table for Memory Reads or Writes
|
2022-04-04 10:30:27 +09:30 |
|
zilmar
|
fcdda04da5
|
Core: Move Audio Interface code in to handler
|
2022-03-21 10:59:02 +10:30 |
|
zilmar
|
df422238c9
|
Core: Fix up handling VideoInterfaceHandler in recompiler
|
2022-03-14 15:29:10 +10:30 |
|
zilmar
|
80d8e6edaa
|
Core: Move Video Interface code in to handler
|
2022-03-08 10:18:56 +10:30 |