zilmar
|
a2981ff4d8
|
Core: Make Load/Store use 64bit vaddr
|
2022-09-19 21:36:36 +09:30 |
|
zilmar
|
1c77f6f0fd
|
Core: Make Cop0 64bit
|
2022-09-19 16:36:44 +09:30 |
|
zilmar
|
21b193152a
|
Core: Fix CMipsMemoryVM::MemoryValue64 for sdl/sdr
|
2022-09-19 12:13:19 +09:30 |
|
zilmar
|
05d46c9487
|
Core: Handle reserve instruction 31
|
2022-09-19 12:12:08 +09:30 |
|
zilmar
|
a640ecfbc0
|
Core: CMipsMemoryVM::SB_NonMemory should return false just on exception
|
2022-09-05 21:20:07 +09:30 |
|
zilmar
|
e171adfef6
|
Core: Clean up formatting of register names
|
2022-09-05 16:47:51 +09:30 |
|
zilmar
|
29526583a6
|
Core: Give cop0 registers names
|
2022-09-05 16:38:30 +09:30 |
|
zilmar
|
18b9892bc7
|
Core: Add handling of overflow exception
|
2022-09-05 16:35:13 +09:30 |
|
zilmar
|
0371c20d32
|
Core: Use BreakOnUnhandledMemory in SPRegistersHandler when breaking
|
2022-09-05 11:00:15 +09:30 |
|
zilmar
|
4218cbad23
|
Core: R4300iInstruction::DecodeSpecialName - Fix up SLL param
|
2022-08-29 08:27:47 +09:30 |
|
zilmar
|
9b16d29792
|
Core: Add rom write decay and some code clean up
|
2022-08-22 12:47:44 +09:30 |
|
zilmar
|
51c9867e76
|
Core: Get the recompiler to be use globals less
|
2022-08-08 20:22:51 +09:30 |
|
zilmar
|
5ea06d958e
|
Core: have SB/SH be able to write to rom handler
|
2022-08-08 19:33:16 +09:30 |
|
zilmar
|
18870634a5
|
Core: Clean up some 64bit warnings
|
2022-08-01 13:15:52 +09:30 |
|
zilmar
|
10d23486c6
|
Core: Add option to break on address exception
|
2022-08-01 10:38:12 +09:30 |
|
zilmar
|
cffeceef70
|
Core: Handle rom written to better
|
2022-08-01 10:15:56 +09:30 |
|
zilmar
|
d37d0dc7a5
|
Core: Dissasm of DMFC0 was showing the wrong reg
|
2022-08-01 10:02:07 +09:30 |
|
zilmar
|
7b851e6b6e
|
Core: Break on unhandled memory
|
2022-08-01 10:00:07 +09:30 |
|
zilmar
|
63051df71e
|
Core: Another fix at 64dd
|
2022-07-25 22:00:41 +09:30 |
|
zilmar
|
09b535551d
|
Core: Move DelaySlotEffectsCompare into R4300iInstruction
|
2022-07-25 16:35:42 +09:30 |
|
zilmar
|
0abc7ccaa4
|
Core: Move OpHasDelaySlot into R4300iInstruction
|
2022-07-25 14:23:12 +09:30 |
|
zilmar
|
15466b6a9b
|
Core: Fix unaligned rom access with LH/LB
|
2022-07-25 14:08:09 +09:30 |
|
zilmar
|
1a8a4dd50f
|
Core: Fix some bugs added to R4300iInstruction Param
|
2022-07-25 11:57:19 +09:30 |
|
zilmar
|
acd5f8ecd5
|
Core: Add ISViewerHandler
|
2022-07-18 19:06:34 +09:30 |
|
zilmar
|
f62f8207ec
|
Core: Initiate PREVID
|
2022-07-18 18:56:52 +09:30 |
|
zilmar
|
7f3b8e3601
|
Core: Start to add R4300iInstruction to do analysis of an opcode
|
2022-07-18 18:01:00 +09:30 |
|
zilmar
|
079e493728
|
Core: Improve PI Dma
|
2022-07-04 17:14:27 +09:30 |
|
zilmar
|
8b2c66cc07
|
Core: Move plugin specs to a central location
|
2022-06-27 19:32:38 +09:30 |
|
zilmar
|
837e93d775
|
Core: Move PI_DMA_READ & PI_DMA_WRITE into PeripheralInterfaceHandler
|
2022-06-20 09:10:01 +09:30 |
|
zilmar
|
f0760ff1cf
|
Core: Move SP_DMA_WRITE into SPRegistersHandler
|
2022-06-13 11:46:06 +09:30 |
|
zilmar
|
86aa483a38
|
Core: Move memory exceptions out of interrupter ops and in to Memory Manager
|
2022-06-13 11:24:36 +09:30 |
|
zilmar
|
8f1f7e9cf3
|
core: move add opcode count from pre to post op for recompiler
|
2022-06-06 11:53:31 +09:30 |
|
zilmar
|
dc106c0df8
|
Core: Start to add store instruction self mod
|
2022-06-06 11:41:09 +09:30 |
|
zilmar
|
603ed853bc
|
Core: Some code clean up for load/store non memory
|
2022-05-30 20:20:25 +09:30 |
|
zilmar
|
cc0c139f7e
|
Core: modularize store memory values using CompileStoreMemoryValue
|
2022-05-23 06:24:56 +09:30 |
|
zilmar
|
f95c0f7ef1
|
Core: Fix bug in SDC1
|
2022-05-20 10:32:15 +09:30 |
|
zilmar
|
487ed8b54d
|
Core: If SMM_PIDMA, clear physical memory code before doing the dma
|
2022-05-16 15:33:36 +09:30 |
|
zilmar
|
1617e63b84
|
Core: make memory reads/write to go through new CMipsMemoryVM::MemoryPtr
|
2022-05-16 15:26:20 +09:30 |
|
zilmar
|
1fe8fd1299
|
Core: have MemoryValue32 be able to read from rom
|
2022-05-16 11:00:20 +09:30 |
|
zilmar
|
718d7e0359
|
[Core] Clean up load/store usage in MemoryVirtualMem
|
2022-05-09 10:06:10 +09:30 |
|
zilmar
|
de366db6c1
|
[Core] Clean up some warnings
|
2022-05-03 22:46:12 +09:30 |
|
zilmar
|
5a49331c0b
|
Core: Direct tlb method to read and write to memory
|
2022-05-02 20:22:31 +09:30 |
|
zilmar
|
bac3517c86
|
[Core] Change tlb empty to be -1 and remove rdram from tlb value
|
2022-05-02 19:10:35 +09:30 |
|
zilmar
|
b74a2dc69f
|
[Core] Change TranslateVaddr to VAddrToPAddr
|
2022-05-02 07:36:50 +09:30 |
|
zilmar
|
2f1074a287
|
Core: Add handler for cartridge domains
|
2022-04-25 17:12:07 +09:30 |
|
zilmar
|
016ded2b56
|
Core: Move Save types
|
2022-04-19 11:17:43 +09:30 |
|
zilmar
|
e9d2b9793f
|
Core: Add Pif Ram Handler
|
2022-04-19 09:37:57 +09:30 |
|
zilmar
|
653e15a296
|
Core: Add RomMemoryHandler
|
2022-04-18 20:57:59 +09:30 |
|
zilmar
|
fbf65bce12
|
Core: Add a look up table for Memory Reads or Writes
|
2022-04-04 10:30:27 +09:30 |
|
zilmar
|
a249705bce
|
Core: Add CartridgeDomain2Address1Handler
|
2022-03-21 20:57:57 +10:30 |